CD4049UB and CD4050B CMOS Hex Inverting Buffer and Converter
1 Features
• CD4049UB Inverting
• CD4050B Noninverting
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1 µA at 18 V Over Full
Package Temperature Range; 100 nA at 18 V and
25°C
• 5-V, 10-V, and 15-V Parametric Ratings
2 Applications
• CMOS to DTL or TTL Hex Converters
• CMOS Current Sink or Source Drivers
• CMOS High-to-Low Logic Level Converters
3 Description
The CD4049UB and CD4050B devices are inverting
and noninverting hex buffers, and feature logic-level
conversion using only one supply voltage (VCC). The
input-signal high level (VIH) can exceed the VCC
supply voltage when these devices are used for logic-
level conversions. These devices are intended for use
as CMOS to DTL or TTL converters and can drive
directly two DTL or TTL loads. (VCC = 5 V,
VOL ≤ 0.4 V, and IOL ≥ 3.3 mA.)
Device Information
PART NUMBER(1) PACKAGE BODY SIZE (NOM)
CD4049UBE,
CD4050BE PDIP (16) 6.35 mm × 19.30 mm
CD4049UBD,
CD4050BD SOIC (16) 9.90 mm × 3.91 mm
CD4049UBDW,
CD4050BDW SOIC (16) 10.30 mm × 7.50 mm
CD4049UBNS,
CD4050BNS SO (16) 10.30 mm × 5.30 mm
CD4049UBPW,
CD4050BPW TSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
V
OUT
CC
V
P
SS
N
R
IN
Copyright © 2016,
Texas Instruments Incorporated
1 of 6 Identical Units
Schematic Diagram of CD4049UB
P
N
R
IN
V
OUT
CC
V
P
SS
N
Copyright © 2016, Texas Instruments Incorporated
1 of 6 Identical Units
Schematic Diagram of CD4050B
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics: DC..................................... 5
6.6 Electrical Characteristics: AC......................................9
6.7 Typical Characteristics.............................................. 10
7 Parameter Measurement Information.......................... 11
7.1 Test Circuits...............................................................11
8 Detailed Description......................................................13
8.1 Overview................................................................... 13
8.2 Functional Block Diagram......................................... 13
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................14
9 Application and Implementation.................................. 15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
10 Power Supply Recommendations..............................16
11 Layout........................................................................... 16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Documentation Support.......................................... 17
12.2 Related Links.......................................................... 17
12.3 Receiving Notification of Documentation Updates..17
12.4 Support Resources................................................. 17
12.5 Trademarks............................................................. 17
12.6 Electrostatic Discharge Caution..............................17
12.7 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (September 2016) to Revision K (June 2020) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated Device Information Table with correct package dimensions................................................................ 1
Changes from Revision I (May 2004) to Revision J (September 2016) Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted Ordering Information table; see POA at the end of the data sheet....................................................... 1
• Changed Storage temperature minimum value from 65 to –65..........................................................................4
• Changed RθJA values for the CD4049UB device: D (SOIC) from 73 to 81.6, DW (SOIC) from 57 to 81.6, E
(PDIP) from 67 to 49.5, NS (SO) from 64 to 84.3, and PW (TSSOP) from 108 to 108.9................................... 5
• Changed RθJA values for the CD4050B device: D (SOIC) from 73 to 81.6, DW (SOIC) from 57 to 81.2, E
(PDIP) from 67 to 49.7, NS (SO) from 64 to 83.8, and PW (TSSOP) from 108 to 108.4................................... 5
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5 Pin Configuration and Functions
1VCC 16 NC
2G 15 L
3A 14 F
4H 13 NC
5B 12 K
6I 11 E
7C 10 J
8VSS 9 D
Not to scale
Figure 5-1. CD4049UB D, DW, N, NS, and PW
Packages 16-Pin SOIC, PDIP, SO, and TSSOP Top
View
1VCC 16 NC
2G 15 L
3A 14 F
4H 13 NC
5B 12 K
6I 11 E
7C 10 J
8VSS 9 D
Not to scale
Figure 5-2. CD4050B D, DW, N, NS, and PW
Packages 1G6-Pin SOIC, PDIP, SO, and TSSOP Top
View
Pin Functions: CD4049UB
PIN I/O DESCRIPTION
NAME NO.
A 3 I Input 1
B 5 I Input 2
C 7 I Input 3
D 9 I Input 4
E 11 I Input 5
F 14 I Input 6
G 2 O Inverting output 1. G = A
H 4 O Inverting output 2. H = B
I 6 O Inverting output 3. I = C
J 10 O Inverting output 4. J = D
K 12 O Inverting output 5. K = E
L 15 O Inverting output 6. L = F
NC 13, 16 — No connection
VCC 1 — Power pin
VSS 8 — Negative supply
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Pin Functions: CD4050B
PIN I/O DESCRIPTION
NAME NO.
A 3 I Input 1
B 5 I Input 2
C 7 I Input 3
D 9 I Input 4
E 11 I Input 5
F 14 I Input 6
G 2 O Inverting output 1. G = A
H 4 O Inverting output 2. H = B
I 6 O Inverting output 3. I = C
J 10 O Inverting output 4. J = D
K 12 O Inverting output 5. K = E
L 15 O Inverting output 6. L = F
NC 13, 16 — No connection
VCC 1 — Power pin
VSS 8 — Negative supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage VCC to VSS –0.5 20 V
DC input current, IIK Any one input ±10 mA
Lead temperature (soldering, 10 s) SOIC, lead tips only 265 °C
Junction temperature, TJ150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage 3 18 V
TAOperating temperature –55 125 °C
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6.4 Thermal Information
THERMAL METRIC(1)
CD4049UB CD4050B
UNIT
D
(SOIC)
DW
(SOIC)
E
(PDIP)
NS
(SO)
PW
(TSSOP)
D
(SOIC)
DW
(SOIC)
E
(PDIP)
NS
(SO)
PW
(TSSOP)
16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS
RθJA
Junction-to-ambient
thermal resistance(2) 81.6 81.6 49.5 84.3 108.9 81.6 81.2 49.7 83.8 108.4 °C/W
RθJC(top)
Junction-to-case (top)
thermal resistance 41.5 44.5 36.8 43 43.7 41.5 44.1 37 42.5 43.2 °C/W
RθJB
Junction-to-board
thermal resistance 39 46.3 29.4 44.6 54 39 45.9 29.6 44.1 53.5 °C/W
ψJT
Junction-to-top
characterization
parameter
10.7 16.5 21.7 12.8 4.6 10.7 16.1 21.9 12.5 4.5 °C/W
ψJB
Junction-to-board
characterization
parameter
38.7 45.8 29.3 44.3 53.4 38.7 45.4 29.5 43.8 52.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
6.5 Electrical Characteristics: DC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDD(Max) Quiescent device current
VIN = 0 or 5 V, VCC = 5 V
TA = –55 °C 1
µA
TA = –40 °C 1
TA = 25 °C 0.02 1
TA = 85 °C 30
TA = 125 °C 30
VIN = 0 or 10 V, VCC = 10 V
TA = –55 °C 2
TA = –40 °C 2
TA = 25 °C 0.02 2
TA = 85 °C 60
TA = 125 °C 60
VIN = 0 or 15 V, VCC = 4 V
TA = –55 °C 4
TA = –40 °C 4
TA = 25 °C 0.02 4
TA = 85 °C 120
TA = 125 °C 120
VIN = 0 or 20 V, VCC = 20 V
TA = –55 °C 20
TA = –40 °C 20
TA = 25 °C 0.04 20
TA = 85 °C 600
TA = 125 °C 600
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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOL(Min) Output low (sink) current
VOUT = 0.4 V, VIN = 0 or 5 V, VCC = 4.5 V
TA = –55 °C 3.3
mA
TA = –40 °C 3.1
TA = 25 °C 2.6 5.2
TA = 85 °C 2.1
TA = 125 °C 1.8
VOUT = 0.4 V, VIN = 0 or 5 V, VCC = 5 V
TA = –55 °C 4
TA = –40 °C 3.8
TA = 25 °C 3.2 6.4
TA = 85 °C 2.9
TA = 125 °C 2.4
VOUT = 0.5 V, VIN = 0 or 10 V, VCC = 10 V
TA = –55 °C 10
TA = –40 °C 9.6
TA = 25 °C 8 16
TA = 85 °C 6.6
TA = 125 °C 5.6
VOUT = 1.5 V, VIN = 0 or 15 V, VCC = 15 V
TA = –55 °C 26
TA = –40 °C 25
TA = 25 °C 24 48
TA = 85 °C 20
TA = 125 °C 18
IOH(Min) Output high (source)
current
VOUT = 4.6 V, VIN = 0 or 5 V, VCC = 5 V
TA = –55 °C –0.81
mA
TA = –40 °C –0.73
TA = 25 °C –0.65 –1.2
TA = 85 °C –0.58
TA = 125 °C –0.48
VOUT = 2.5 V, VIN = 0 or 5 V, VCC = 5 V
TA = –55 °C –2.6
TA = –40 °C –2.4
TA = 25 °C –2.1 –3.9
TA = 85 °C –1.9
TA = 125 °C –1.55
VOUT = 9.5 V, VIN = 0 or 10 V, VCC = 10 V
TA = –55 °C –2
TA = –40 °C –1.8
TA = 25 °C –1.65 –3
TA = 85 °C –1.35
TA = 125 °C –1.18
VOUT = 1.3 V, VIN = 0 or 15 V, VCC = 15 V
TA = –55 °C –5.2
TA = –40 °C –4.8
TA = 25 °C –4.3 –8
TA = 85 °C –3.5
TA = 125 °C –3.1
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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL(Max) Out voltage low level
VIN = 0 or 5 V, VCC = 5 V
TA = –55 °C 0.05
V
TA = –40 °C 0.05
TA = 25 °C 0 0.05
TA = 85 °C 0.05
TA = 125 °C 0.05
VIN = 0 or 10 V, VCC = 10 V
TA = –55 °C 0.05
TA = –40 °C 0.05
TA = 25 °C 0 0.05
TA = 85 °C 0.05
TA = 125 °C 0.05
VIN = 0 or 15 V, VCC = 15 V
TA = –55 °C 0.05
TA = –40 °C 0.05
TA = 25 °C 0 0.05
TA = 85 °C 0.05
TA = 125 °C 0.05
VOH(Min) Output voltage high level
VIN = 0 or 5 V, VCC = 5 V
TA = –55 °C 4.95
V
TA = –40 °C 4.95
TA = 25 °C 4.95 5
TA = 85 °C 4.95
TA = 125 °C 4.95
VIN = 0 or 10 V, VCC = 10 V
TA = –55 °C 9.95
TA = –40 °C 9.95
TA = 25 °C 9.95 10
TA = 85 °C 9.95
TA = 125 °C 9.95
VIN = 0 or 15 V, VCC = 15 V
TA = –55 °C 14.95
TA = –40 °C 14.95
TA = 25 °C 14.95 15
TA = 85 °C 14.95
TA = 125 °C 14.95
VIL(Max)
Input low voltage
(CD4049UB)
VOUT = 4.5 V, VCC = 5 V, Full temperature range 1
V
VOUT = 9 V, VCC = 10 V, Full temperature range 2
VOUT = 13.5 V, VCC = 15 V, Full temperature range 2.5
Input low voltage
(CD4050B)
VOUT = 0.5 V, VCC = 5 V, Full temperature range 1.5
VOUT = 1 V, VCC = 10 V, Full temperature range 3
VOUT = 1.5 V, VCC = 15 V, Full temperature range 4
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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH(Min) Input high voltage
(CD4049UB)
VOUT = 0.5 V, VCC = 5 V
TA = –55 °C 4
V
TA = –40 °C 4
TA = 25 °C 4
TA = 85 °C 4
TA = 125 °C 4
VOUT = 1 V, VCC = 10 V
TA = –55 °C 8
TA = –40 °C 8
TA = 25 °C 8
TA = 85 °C 8
TA = 125 °C 8
VOUT = 1.5 V, VCC = 15 V
TA = –55 °C 12.5
TA = –40 °C 12.5
TA = 25 °C 12.5
TA = 85 °C 12.5
TA = 125 °C 12.5
VIH
Input high voltage
(CD4050B)
VOUT = 4.5 V, VCC = 5 V
TA = –55 °C 3.5
V
TA = –40 °C 3.5
TA = 25 °C 3.5
TA = 85 °C 3.5
TA = 125 °C 3.5
VOUT = 9 V, VCC = 10 V
TA = –55 °C 7
TA = –40 °C 7
TA = 25 °C 7
TA = 85 °C 7
TA = 125 °C 7
VOUT = 13.5 V, VCC = 15 V
TA = –55 °C 11
TA = –40 °C 11
TA = 25 °C 11
TA = 85 °C 11
TA = 125 °C 11
IIN(Max) Input current VIN = 0 or 18 V, VCC = 18 V
TA = –55 °C ±0.1
µA
TA = –40 °C ±0.1
TA = 25 °C ±10–5 ±0.1
TA = 85 °C ±1
TA = 125 °C ±1
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6.6 Electrical Characteristics: AC
TA = 25°C, Input tr and tf = 20 ns, CL = 50 pF, RL = 200 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH
Propagation delay time
Low to high (CD4049UB)
VIN = 5 V, VCC = 5 V 60 120
ns
VIN = 10 V, VCC = 10 V 32 65
VIN = 10 V, VCC = 5 V 45 90
VIN = 15 V, VCC = 15 V 25 50
VIN = 15 V, VCC = 5 V 45 90
Propagation delay time
Low to high (CD4050B)
VIN = 5 V, VCC = 5 V 70 140
ns
VIN = 10 V, VCC = 10 V 40 80
VIN = 10 V, VCC = 5 V 45 90
VIN = 15 V, VCC = 15 V 30 60
VIN = 15 V, VCC = 5 V 40 80
tPHL
Propagation delay time
High to low (CD4049UB)
VIN = 5 V, VCC = 5 V 32 65
ns
VIN = 10 V, VCC = 10 V 20 40
VIN = 10 V, VCC = 5 V 15 30
VIN = 15 V, VCC = 15 V 15 30
VIN = 15 V, VCC = 5 V 10 20
Propagation delay time
High to low (CD4050B)
VIN = 5 V, VCC = 5 V 55 110
ns
VIN = 10 V, VCC = 10 V 22 55
VIN = 10 V, VCC = 5 V 50 100
VIN = 15 V, VCC = 15 V 15 30
VIN = 15 V, VCC = 5 V 50 100
tTLH
Transition time
Low to high
VIN = 5 V, VCC = 5 V 80 160
nsVIN = 10 V, VCC = 10 V 40 80
VIN = 15 V, VCC = 15 V 30 60
tTHL
Transition time
High to low
VIN = 5 V, VCC = 5 V 30 60
nsVIN = 10 V, VCC = 10 V 20 40
VIN = 15 V, VCC = 15 V 15 30
CIN
Input capacitance (CD4049UB) 15 22.5 pF
Input capacitance (CD4050B) 5 7.5 pF
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6.7 Typical Characteristics
5
4
3
2
1
0 1 2 3 4
V , INPUT VOLTAGE (V)
I
VO, OUTPUT VOLTAGE (V)
T = 25 C
Ao
SUPPLY VOLTAGE (V ) = 5V
CC
MAXIMUMMINIMUM
Figure 6-1. Minimum and Maximum Voltage
Transfer Characteristics for CD4049UB
5
4
3
2
1
0 1 2 3 4
V , INPUT VOLTAGE (V)
I
VO, OUTPUT VOLTAGE (V)
T = 25 C
Ao
SUPPLY VOLTAGE (V ) = 5V
CC
MAXIMUMMINIMUM
Figure 6-2. Minimum and Maximum Voltage
Transfer Characteristics for CD4050B
50
40
30
20
10
0 1 2 3 4
V , DRAIN TO SOURCE VOLTAGE (V)
DS
IOL, OUTPUT LOW (SINK) CURRENT (mA)
T = 25 C
Ao
GATE TO SOURCE VOLTAGE (V ) = 5V
GS
10V
15V
60
70
5 6 7 8
Figure 6-3. Typical Output Low (Sink) Current
Characteristics
50
40
30
20
10
0 1 2 3 4
V , DRAIN TO SOURCE VOLTAGE (V)
DS
IOL, OUTPUT LOW (SINK) CURRENT (mA)
T = 25 C
Ao
GATE TO SOURCE VOLTAGE (V ) = 5V
GS
10V15V
60
70
5 6 7 8
Figure 6-4. Minimum Output Low (Sink) Current
Drain Characteristics
-5
-10
-15
-20
-25
-30
-35
OUTPUT HIGH (SOURCE)
CURRENT CHARACTERISTICS
-15V
-10V
GATE TO SOURCE VOLTAGE
V = -5V
GS
T = 25 C
Ao
-8 -7 -6 -5 -4 -3 -2 -1 0
V , DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 6-5. Typical Output High (Source) Current
Characteristics
-5
-10
-15
-20
-25
-30
-35
OUTPUT HIGH (SOURCE)
CURRENT CHARACTERISTICS
-15V
-10V
GATE TO SOURCE VOLTAGE
V = -5V
GS
T = 25 C
Ao
-8 -7 -6 -5 -4 -3 -2 -1 0
V , DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 6-6. Minimum Output High (Source) Current
Characteristics
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10
6
5
4
3
2
1
VO, OUTPUT VOLTAGE (V)
-55 C
o
125 C
o
SUPPLY VOLTAGE
V = 10V
CC
T = -55 C
Ao
876543210
V , INPUT VOLTAGE (V)
I
9 10
9
8
7
0
125 C
o
V = 5V
CC
Figure 6-7. Typical Voltage Transfer Characteristics
as a Function of Temperature for CD4049UB
10
6
5
4
3
2
1
VO, OUTPUT VOLTAGE (V)
-55 C
o
125 C
o
SUPPLY VOLTAGE
V = 10V
CC
T = -55 C
Ao
876543210
V , INPUT VOLTAGE (V)
I
9 10
9
8
7
0
125 C
o
V = 5V
CC
Figure 6-8. Typical Voltage Transfer Characteristics
as a Function of Temperature for CD4050B
10
10
10
10
10
5
4
3
2
10 10 10 10 10
2 3 4 5
T = 25 C
Ao
SUPPL
Y VOLTAGE VCC = 15V
10V
10V
5V
LOAD CAPACITANCE
C = 50pF
L
(11pF FIXTURE + 39pF EXT)
(11pF FIXTURE + 4pF EXT)
C = 15pF
L
POWER DISSIPATION PER INVERTER ( W)µ
f, INPUT FREQUENCY (kHz)
Figure 6-9. Typical Power Dissipation versus Frequency Characteristics
7 Parameter Measurement Information
7.1 Test Circuits
I
V
INPUTS
DD
CC
V
V
V
SS
CC
SS
Figure 7-1. Quiescent Device Current Test Circuit
V
OUTPUTS
CC
INPUTS
V
V
V
IH
IL
SS
DVM
+
-
Test any one input with other inputs at VCC or VSS.
Figure 7-2. Input Voltage Test Circuit
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V
OUTPUTS
CC
INPUTS
V
V
V
CC
SS
SS
I
Measure inputs sequentially, to both VCC and VSS connect all
unused inputs to either VCC or VSS.
Figure 7-3. Input Current Test Circuit
V = 5V
CC
OUTPUT
INPUTS
10V = V
0 = V V
TO DTL/TTL
IH
IL SS
CMOS 10V LEVEL TO DTL/TTL 5V LEVEL
COS/MOS
IN
IN Pin: A, B, C, D, E, or F
B. OUT Pin: G, H, I, J, K, or L
C. VCC Pin
D. VSS Pin
Figure 7-4. Logic Level Conversion Application
I
V
500
F
DD µ
0.1 Fµ
C
10kHz,
L
100kHz, 1MHz
1
2
3
4
5
6
7
8
CD4049UB
16
15
14
13
12
11
10
9
CL includes fixture capacitance.
Figure 7-5. Dynamic Power Dissipation Test Circuits
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8 Detailed Description
8.1 Overview
The CD4049UB device is an inverting hex buffer; the CD4050B device is a noninverting hex buffer. These
devices do logic-level conversions and have a high sink current that can drive two TTL loads. These devices
also have low input current of 1 µA across the full temperature range at 18 V.
The CD4049UB and CD4050B devices are designated as replacements for CD4009UB and CD4010B devices,
respectively. Because the CD4049UB and CD4050B require only one power supply, they are preferred over the
CD4009UB and CD4010B and should be used in place of the CD4009UB and CD4010B in all inverter, current
driver, or logic-level conversion applications. In these applications the CD4049UB and CD4050B are pin
compatible with the CD4009UB and CD4010B respectively, and can be substituted for these devices in existing
as well as in new designs. Pin 16 (NC) is not connected internally on the CD4049UB or CD4050B, therefore,
connection to this terminal is of no consequence to circuit operation. TI recommends the CD4069UB hex inverter
is recommended for applications not requiring high sink-current or voltage conversion.
8.2 Functional Block Diagram
CD4050B
3 2
A G A
5 4
B H B
7 6
C I C
9 10
D J D
11 12
E K E
14 15
F L F
1
8
V
V
NC = 13
CC
SS
NC = 16
3 2
A G = A
5 4
B H = B
7 6
C I = C
9 10
D J = D
11 12
E K = E
14 15
F L = F
1
8
V
V
NC = 13
CC
SS
NC = 16
=
=
=
=
=
=
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
CD4049UB and CD4050B have standardized symmetrical output characteristics and a wide operating voltage
from 3 V to 18 V with quiescent current tested at 20 V. These devices have transition times of tTLH = 40 ns and
tTHL = 20 ns (typical) at 10 V. The operating temperature is from –55°C to 125°C.
www.ti.com
CD4049UB, CD4050B
SCHS046K – AUGUST 1998 – REVISED JUNE 2020
Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13
Product Folder Links: CD4049UB CD4050B
8.4 Device Functional Modes
Table 8-1 shows the functional modes for CD4049UB. Table 8-2 shows the functional modes for CD4050B.
Table 8-1. Function Table for
CD4049UB
INPUT
A, B, C, D, E, F
OUTPUT
G, H, I, J, K, L
H L
L H
Table 8-2. Function Table for
CD4050B
INPUT
A, B, C, D, E, F
OUTPUT
G, H, I, J, K, L
H H
L L
CD4049UB, CD4050B
SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com
14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: CD4049UB CD4050B
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The CD4049UB and CD4050B devices have low input currents of 1 µA at 18 V over full package-temperature
range and 100 nA at 18 V, 25°C. These devices have a wide operating voltage from 3 V to 18 V and used in
high-voltage applications.
9.2 Typical Application
C
VCC
Logic signal
R
LED
Copyright © 2016,
Texas Instruments Incorporated
Figure 9-1. CD4049UB Application
9.2.1 Design Requirements
The CD4049UB device is the industry's highest logic inverter operating at 18 V under recommended conditions.
These devices have high sink current capabilities.
9.2.2 Detailed Design Procedure
The recommended input conditions for Figure 9-1 includes rise time and fall time specifications (see Δt/ΔV in
Recommended Operating Conditions) and specified high and low levels (see VIH and VIL in Recommended
Operating Conditions). Inputs are not overvoltage tolerant and must be below VCC level because of the presence
of input clamp diodes to VCC.
The recommended output condition for the CD4049UB application includes specific load currents. Load currents
must be limited so as to not exceed the total power (continuous current through VCC or GND) for the device.
These limits are in the Absolute Maximum Ratings. Outputs must not be pulled above VCC.
www.ti.com
CD4049UB, CD4050B
SCHS046K – AUGUST 1998 – REVISED JUNE 2020
Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 15
Product Folder Links: CD4049UB CD4050B
9.2.3 Application Curves
10
10
10
10
10
5
4
3
2
10 10 10 10 10
2 3 4 5
T = 25 C
Ao
POWER DISSIPATION PER INVERTER ( W)µ
t , t , INPUT RISE AND FALL TIME (ns)
r f
SUPPLY VOLTAGE V = 5V FREQUENCY (f) = 10kHz
CC
15V; 1MHz
15V; 100kHz
10V; 100kHz
15V; 10kHz
10V; 10kHz
15V; 1kHz
Figure 9-2. Typical Power Dissipation vs Input Rise
and Fall Times Per Inverter for CD4049UB
10
10
10
10
1
6
4
3
2
10 10 10 10 10
2 3 4 5
T = 25 C
Ao
POWER DISSIPATION PER INVERTER ( W)µ
t , t , INPUT RISE AND FALL TIME (ns)
r f
SUPPLY VOLTAGE V = 5V FREQUENCY (f) = 10kHz
CC
10 10 10
10
6 7 8
105
15V; 1MHz
15V; 100kHz
10V; 100kHz
15V; 10kHz
10V; 10kHz
Figure 9-3. Typical Power Dissipation vs Input Rise
and Fall Times Per Buffer for CD4050B
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating in
Recommended Operating Conditions.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-µF capacitor. If there are multiple VCC pins, then TI recommends a 0.01-µF or
0.022-µF capacitor for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different
frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor must be
installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must never float.
In many cases, digital logic device functions or parts of these functions are unused (for example, when only two
inputs of a triple-input and gate are used, or only 3 of the 4 buffer gates are used). Such input pins must not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. This rule must be observed under all circumstances specified in the next paragraph.
All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.
See Implications of Slow or Floating CMOS Inputs for more information on the effects of floating inputs. The logic
level must apply to any particular unused input depending on the function of the device. Generally, they are tied
to GND or VCC (whichever is convenient).
11.2 Layout Example
VCC
Unused Input
Input
Output Output
Input
Unused Input
Figure 11-1. Layout Diagram
CD4049UB, CD4050B
SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com
16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: CD4049UB CD4050B
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
CD4049UB Click here Click here Click here Click here Click here
CD4050B Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com
CD4049UB, CD4050B
SCHS046K – AUGUST 1998 – REVISED JUNE 2020
Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 17
Product Folder Links: CD4049UB CD4050B
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD4049UBD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM
CD4049UBDE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM
CD4049UBDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM
CD4049UBDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM
CD4049UBDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM
CD4049UBDT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM
CD4049UBDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM
CD4049UBDWG4 ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM
CD4049UBE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4049UBE
CD4049UBEE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4049UBE
CD4049UBF ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD4049UBF
CD4049UBF3A ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD4049UBF3A
CD4049UBNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UB
CD4049UBPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM049UB
CD4049UBPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM049UB
CD4050BD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM
CD4050BDE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM
CD4050BDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM
CD4050BDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD4050BDT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM
CD4050BDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM
CD4050BDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM
CD4050BE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4050BE
CD4050BEE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4050BE
CD4050BF ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD4050BF
CD4050BF3A ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD4050BF3A
CD4050BNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050B
CD4050BPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM050B
CD4050BPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM050B
JM38510/05553BEA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
05553BEA
JM38510/05554BEA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
05554BEA
M38510/05553BEA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
05553BEA
M38510/05554BEA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
05554BEA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 3
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4049UB, CD4049UB-MIL, CD4050B, CD4050B-MIL :
•Catalog: CD4049UB, CD4050B
•Military: CD4049UB-MIL, CD4050B-MIL
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD4049UBDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4049UBNSR SO NS 16 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
CD4049UBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4050BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4050BDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
CD4050BNSR SO NS 16 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
CD4050BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Dec-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4049UBDR SOIC D 16 2500 333.2 345.9 28.6
CD4049UBNSR SO NS 16 2000 367.0 367.0 38.0
CD4049UBPWR TSSOP PW 16 2000 853.0 449.0 35.0
CD4050BDR SOIC D 16 2500 333.2 345.9 28.6
CD4050BDWR SOIC DW 16 2000 350.0 350.0 43.0
CD4050BNSR SO NS 16 2000 853.0 449.0 35.0
CD4050BPWR TSSOP PW 16 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Dec-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
BNOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
SOIC - 2.65 mm max heightDW 16
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
4224780/A
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
14X 1.27
16X 0.51
0.31
2X
8.89
TYP
0.33
0.10
0 - 8 0.3
0.1
(1.4)
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
10.5
10.1
BNOTE 4
7.6
7.4
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
(9.3)
14X (1.27)
R0.05 TYP
16X (2)
16X (0.6)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:7X
SYMM
1
89
16
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
R0.05 TYP
16X (2)
16X (0.6)
14X (1.27)
(9.3)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1
89
16
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