General Description
The MAX77818 is a high-performance companion PMIC
for the latest smartphones and tablet computers. The
PMIC includes a dual input, smart power path 3.0A switch
mode charger with reverse boost capability and adapter
input protection up to 16VDC withstand, proprietary
ModelGauge™ (mg5) fuel gauge technology.
The switch mode battery charger’s operating frequency
is 4MHz and includes integrated, low-loss switches to
provide the industry’s smallest L/C size, lowest heat, and
fastest battery charging programmable up to 3.0A. The
charger has two inputs that accept adapter/USB (CHIN)
and/or wireless type inputs (WCIN). The wireless input
can simultaneously charge the battery while powering
USB-OTG type accessories. The USB-OTG output pro-
vides true-load disconnect and is protected by an adjust-
able output current limit.
The battery charger includes smart power path and I2C
adjustable settings to accommodate a wide range of
battery sizes and system loads. When external power
is applied from either input, battery charging is enabled.
With a valid input power source (adapter or wireless
charger), the BYP pin voltage is equal to the input voltage
minus resistive voltage drop. During battery-only reverse
boost operation, the BYP output can be regulated with the
reverse boost feature and provides up to 5V at 1.5A and
requires no additional inductor, allowing the MAX77818 to
power USB OTG accessories.
The switching charger is designed with a special CC, CV,
and die temperature regulation algorithm. ModelGauge
(mg5) provides accurate battery fuel gauging without cali-
bration and operates with extremely low battery current.
The safeout LDO drive system USB interface devices.
The MAX77818 features a I2C revision 3.0-compatible
serial interface that comprises a bidirectional serial data
line (SDA) and a serial clock line (SCL).
Applications
●Smartphones and Tablets
●Other Handheld Devices
Benets and Features
●Dual Input Switchmode Battery Charger
• Adapter/USB Input
• Up to 13.4V Adapter Charging
• Up to 4.0A rated, Input Current Protection
(Programmable)
• Wireless Charging Input
• Up to 5.9V Wireless Charging
• Up to 1.26A, Input Current Protection
(Programmable)
• Support USB-OTG Accessories
• Battery Charge Current, Up to 3.0A
• No Sense Resistor
• CC, CV, and Die Temperature Control
• Integrated Battery True-Disconnect FET
• RDS(ON) = 12.8mΩ
• Rated Up to 4.5ARMS, Discharge Current Limit
(Programmable)
• Reverse Boost Capability
• Supports USB-OTG Accessories
• Up to 5.1V/1.5A
• Adjustable OCP
●ModelGauge (mg5) Battery Fuel Gauge
• ±1% SOC Accuracy, No Calibration Cycles, Very
Low IQ
• Time-to-Empty and Time-to-Full Prediction
●Two Safeout LDOs
●I2C Serial Interface
●72-Bump. 3.867mm x 3.608mm WLP with 0.4mm
Pitch
Ordering Information appears at end of data sheet.
19-6902; Rev 0; 10/15
ModelGauge is a trademark of Maxim Integrated Products, Inc
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
EVALUATION KIT AVAILABLE
Switching Charger
CHGIN to GND ...................................................... -0.3V to +16V
BYP to GND ..........................................................-0.3V to +16V
WCIN, PVL, AVL, BAT_SP, BATT, SYS,
DETBATB to GND ...............................................-0.3V to +6V
BST to PVL ............................................................ -0.3V to +16V
BST to CHGLX ........................................................-0.3V to +6V
WCINOKB, INOKB to GND ...........................-0.3V to SYS+0.3V
BAT_SN, CHGPG to GND ...................................-0.3V to +0.3V
CHGLX, CHGPG Continuous Current ..........................3.5ARMS
SYS, BATT Continuous Current ....................................4.5ARMS
CHGIN, BYP Continuous Current .................................4.0ARMS
WCIN Continuous Current.............................................1.5ARMS
Fuel Gauge
VBFG, to GND ......................................................-0.3V to +2.2V
THMB, THM to GND ................................. -0.3V to VAVL + 0.3V
Safeout LDOs
SAFEOUT1, SAFEOUT2 to GND .............................-0.3V to 6V
SAFEOUT1, SAFEOUT2 Continuous Current .................100mA
I2C and Interface Logic
VIO to GND ..............................................................-0.3V to +6V
SDA, SCL to GND .......................................... -0.3V to VIO+0.3V
INTB to GND .........................................-0.3V to VSYS_A + 0.3V
TEST_, VCCTEST, SYS_ to GND ............................ -0.3V to +6V
GND_ to GND ......................................................-0.3V to +0.3V
Thermal Ratings
Operating Temperature Range ........................... -40°C to +85°C
Junction Temperature ...................................................... +150°C
Storage Temperature Range ............................ -65°C to +150°C
Soldering Temperature (reflow) ....................................... +260°C
Continuous Power Dissipation (TA = +70°C)
(derate 28.9mW/°C with 4L board, above 70°C) ........... 2.31W
(Note 1)
WLP
Junction-to-Ambient Thermal Resistance (θJA) .......34.6°C/W
(VSYS = +3.7V, CHGIN = 0V , VIO = 1.8V, TA =-40°C to +85°C, unless otherwise noted. Limits are 100% production tested at TA =
+25°C . Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.
Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
CHGLX has internal clamp diodes to CHGPG and BYP. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation limits.
Electrical Characteristics
General Electrical Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Shutdown Supply Current (BATT) All circuits off 23 50 µA
VBATT = 3.6V
No Load Supply Current (BATT) Fuel gauge is on 50 100 µA
All other circuits off, VBATT = 3.6V
SYS INPUT RANGE
SYS Operating Voltage Guaranteed by VSYSUVLO and
VSYSOVLO
2.8 5 V
SYS Undervoltage Lockout
Threshold VSYS falling, 200mV hysteresis 2.45 2.5 2.55 V
SYS Overvoltage Lockout
Threshold VSYS rising, 200mV hysteresis 5.2 5.36 5.52 V
(VSYS = +3.7V, CHGIN = 0V , VIO = 1.8V, TA =-40°C to +85°C, unless otherwise noted. Limits are 100% production tested at TA =
+25°C . Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.
Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Electrical Characteristics (continued)
General Electrical Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LOGIC AND CONTROL INPUT
SCL, SDA Input Low Level TA = +25°C 0.3 x
VIO
V
SCL, SDA Input High Level TA = +25°C 0.7 x
VIO
V
SCL, SDA Input Hysteresis TA = +25°C 0.05
x VIO
V
SCL, SDA Logic Input Current VIO = 3.6V -10 +10 µA
SCL, SDA Input capacitance 10 pF
SDA Output Low Voltage Sinking 20mA 0.4 V
Output Low Voltage INTB ISINK = 1mA 0.4 V
I2C-COMPATIBLE INTERFACE TIMING FOR STANDARD, FAST, AND FAST-MODE PLUS (Note 2)
Clock Frequency fSCL 1000 kHz
Hold Time (Repeated) START
Condition tHD;STA 0.26 µs
CLK Low Period tLOW 0.5 µs
CLK High Period tHIGH 0.26 µs
Setup Time Repeated START
Condition tSU;STA 0.26 µs
DATA Hold Time tHD:DAT 0 µs
DATA Valid Time tVD:DAT 0.45 µs
DATA Valid Acknowledge Time tVD:ACK 0.45 µs
DATA Setup Time tSU;DAT 50 ns
Setup Time for STOP Condition tSU;STO 0.26 µs
Bus Free Time Between STOP
and START tBUF 0.5 µs
Pulse Width of Spikes that Must
Be Suppressed by the Input Filter (Note 3) 50 ns
(VSYS = +3.7V, CHGIN = 0V , VIO = 1.8V, TA =-40°C to +85°C, unless otherwise noted. Limits are 100% production tested at TA =
+25°C . Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.
Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Electrical Characteristics (continued)
General Electrical Characteristics
PARAMETER SYMBOL CONDITIONS CB = 100pF UNITS
MIN TYP MAX
I2C-COMPATIBLE INTERFACE TIMING FOR HS MODE (Note 2)
Clock Frequency fSCL 3.4 MHz
Setup Time Repeated START
Condition tSU;STA 160 ns
Hold Time (Repeated) START
Condition tHD;STA 160 ns
CLK Low Period tLOW 160 ns
CLK High Period tHIGH 60 ns
DATA Setup time tSU;DAT 10 ns
DATA Hold Time tHD:DAT 0 ns
SCL Rise Time tRCL TA = +25°C 10 40 ns
Rise Time of SCL Signal After a
Repeated START condition and
After an Acknowledge Bit
tRCL1 TA = +25°C 10 80 ns
SCL Fall Time tFCL TA = +25°C 10 40 ns
SDA Rise Time tRDA TA = +25°C 10 80 ns
SDA Fall Time tFDA TA = +25°C 80 ns
Setup Time for STOP Condition tSU;STO 160 ns
Pulse Width of Spikes that Must
be Suppressed by the Input Filter 10 ns
(VCHGIN = 5V, VBATT = 4.2V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Fast-charge current is set
for 1.5A, done current is set for 150mA. Limits are 100% production tested at TA = +25°C . Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Switching Charger Electrical Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CHGIN INPUT
CHGIN Operating Voltage Range Operating voltage 3.2 V
OVLO
V
WCIN Operating Voltage Range Operating voltage 3.2 V
OVLO
V
CHGIN Overvoltage Threshold
(Note 4) V
CHGIN-OVLO
V
CHGIN
rising 13.4 13.7 14 V
WCIN Overvoltage Threshold
(Note 4) V
WCIN-OVLO
V
WCIN
rising 5.9 6 V
WCIN Overvoltage Threshold
Hysteresis V
WCINH-OVLO
V
WCIN
falling 100 mV
CHGIN Overvoltage Threshold
Hysteresis V
CHGINH-OVLO
V
CHGIN
falling 300 mV
WCIN/CHGIN Overvoltage Delay T
D-OVLO
V
WCIN/BUS_DET
rising, 100mV
overdrive, not production tested 10 us
V
WCIN/BUS_DET
falling, 100mV
overdrive, not production tested 20 us
WCIN/CHGIN to GND Minimum
Turn-On Threshold Range
(Note 4)
VWCIN/CHGIN_
UVLO
V
CHGIN
rising, 100mV hysteresis,
programmable at 4.5V, 4.9V, 5.0V,
5.1V, WCIN input is disabled when valid
CHGIN input is detected
4.5 5.1 V
WCIN/CHGIN to GND Minimum
Turn-On Threshold Accuracy
V
WCIN/CHGIN_
UVLO
V
WCIN/CHGIN
rising, 4.5V setting 4.4 4.5 4.6 V
WCIN/CHGIN to SYS Minimum
Turn-On Threshold (Note 4)
V
WCIN/
CHGIN2SYS
V
CHGIN
rising, 50mV hysteresis, WCIN
input is disabled when valid CHGIN
input is detected
V
SYS
+ 0.12
V
SYS
+ 0.20
V
SYS
+ 0.28 V
WCIN/CHGIN Turn-On
Threshold Delay T
D-UVLO
Not production tested 10 us
WCIN/CHGIN Adaptive Current
Regulation Threshold Range
(Note 5)
V
WCIN/
CHGIN_REG
Programmable at 4.3V, 4.7V, 4.8V, 4.9V 4.3 4.9 V
WCIN/CHGIN Adaptive Voltage
Regulation Threshold Accuracy
V
WCIN/
CHGIN_REG
4.9V setting 4.8 4.9 5 V
CHGIN Current-Limit Range
Programmable, 500mA default, factory
programmable option of 100mA,
production tested at 100mA, 500mA,
1000mA, 1800mA, 4000mA settings
only
0.1 4 A
WCIN Current-Limit Range
Programmable, 500mA default, factory
programmable option of 100mA,
production tested at 100mA, 250mA,
500mA, 1000mA settings only
0.06 1.26 A
(VCHGIN = 5V, VBATT = 4.2V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Fast-charge current is set
for 1.5A, done current is set for 150mA. Limits are 100% production tested at TA = +25°C . Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Switching Charger Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
WCIN or CHGIN Supply Current I
IN
V
WCIN/CHGIN
= 2.4V, the input is
undervoltage and R
INSD
is the only
loading
0.075
mA
V
WCIN/CHGIN
= 5.0V, charger disabled 0.17 0.5
V
WCIN/CHGIN
= 5.0V, charger enabled,
V
SYS
= V
BATT
= 4.5V,
(no switching, battery charged)
2.7 4
VWCIN or VCHGIN Input Current
Limit I
INLIMIT
V
WCIN
or V
CHGIN
= 5.0V, charger
enabled, V
BATT
= 3.8V, 100mA input
current setting, T
A
= +25°C
90 102 108
mA
V
WCIN
or V
CHGIN
= 5.0V, charger
enabled, V
BATT
= 3.8V, 500mA Input
current setting, T
A
= +25°C
462.5 487.5 500
V
WCIN
or V
CHGIN
= 5.0V, charger
enabled, V
BATT
= 3.8V, 1000mA Input
current setting, T
A
= +25°C
950 975 1000
V
WCIN
or V
CHGIN
= 5.0V, charger
enabled, V
BATT
= 3.8V, 1000mA input
current setting, T
A
= 0°C to +85°C
926 975 1024
VCHGIN Input Current Limit I
INLIMIT
V
CHGIN
= 5.0V, charger enabled,
V
BATT
= 3.8V, 1800mA input current
setting, T
A
= +25°C
1710 1755 1800
mA
V
CHGIN
= 5.0V, charger enabled,
V
BATT
= 3.8V, 1800mA input current
setting, T
A
= 0°C to +85°C
1667 1755 1843
V
CHGIN
= 5.0V, charger enabled,
V
BATT
= 3.8V, 4000mA input current
setting, T
A
= +25°C
3800 3900 4000
V
CHGIN
= 5.0V, charger enabled,
V
BATT
= 3.8V, 4000mA input current
setting, T
A
= 0°C to +85°C
3705 3900 4095
WCIN, CHGIN Self-Discharge
Down to UVLO Time t
INSD
Time required for the charger input to
cause a 10µF input capacitor to decay
from 6.0V to 4.3V.
100 ms
WCIN, CHGIN Input
Self-Discharge Resistance R
INSD
For CHGIN, this resistor is
disconnected from the CHGIN pin
during MUIC microphone mode
35 kΩ
WCINOK/CHGINOK to Start
Switching t
START
150 ms
(VCHGIN = 5V, VBATT = 4.2V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Fast-charge current is set
for 1.5A, done current is set for 150mA. Limits are 100% production tested at TA = +25°C . Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Switching Charger Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SWITCH IMPEDANCES AND LEAKAGE CURRENTS
CHGIN to BYP Resistance R
IN2BYP
Bidirectional 0.0144 0.04 Ω
WCIN to BYP Resistance R
WCIN2BYP
0.093 0.26 Ω
CHGLX High-Side Resistance R
HS
0.0327 0.1 Ω
CHGLX Low-Side Resistance R
LS
0.0543 0.14 Ω
BATT to SYS Dropout Resistance R
BAT2SYS
0.0128 0.04 Ω
CHGIN to BATT Dropout
Resistance R
IN2BAT
Calculation estimates a 0.04Ω inductor
resistance (R
L
) 0.0999 Ω
R
IN2BAT
= R
IN2BYP
+ R
HS
+R
L
+
R
BAT2SYS
CHGLX Leakage Current CHGLX = CHGPG or
BYP
T
A
= +25°C 0.01 10 µA
T
A
= +85°C 1 µA
BST Leakage Current V
BST
= 5.5V T
A
= +25°C 0.01 10 µA
T
A
= +85°C 1 µA
BYP Leakage Current
V
BYP
= 5.5V, V
CHGIN
= 0V, V
CHGLX
= 0V,
charger disabled
T
A
= +25°C 0.01 10 µA
T
A
= +85°C 1 µA
WCIN Leakage Current
V
BYP
= 0V,
V
CHGIN
= 0V,
V
WCIN
= 5.5V
T
A
= +25°C 0.01 µA
T
A
= +85°C 1 µA
SYS Leakage Current
V
SYS
= 0V,
V
BATT
= 4.2V,
charger disabled
T
A
= +25°C 0.01 10 µA
T
A
= +85°C 1 µA
(VCHGIN = 5V, VBATT = 4.2V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Fast-charge current is set
for 1.5A, done current is set for 150mA. Limits are 100% production tested at TA = +25°C . Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Switching Charger Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BATT Quiescent Current
(I
SYS
= 0A, I
BYP
= 0A )
I
MBAT
V
CHGIN
= 0V,
V
SYS
= 0V,
V
BATT
= 4.2V,
QBAT is off
T
A
= +25°C 20 30 µA
T
A
= +85°C 20 µA
V
CHGIN
= 0V,
V
BATT
= 4.2V, QBAT
is on, main-battery
overcurrent protection
disabled
T
A
= +25°C 15.3 µA
T
A
= +85°C 15.3 µA
V
CHGIN
= 0V,
V
BATT
= 4.2V, QBAT
is on, main-battery
overcurrent protection
enabled
T
A
= +25°C 20 µA
T
A
= +85°C 20 µA
V
SYS
= 4.2V,
V
BATT
= 0V, charger
disabled
T
A
= +25°C 0.01 10 µA
T
A
= +85°C 1 µA
I
MBDN
V
CHGIN
= 5V,
V
BATT
= 4.2V, QBAT
is off, main-battery
overcurrent protection
disabled, Charger is
enabled but in its done
mode
T
A
= +25°C 3 10 µA
T
A
= +85°C 3 µA
CHARGER DC-DC BUCK
Minimum On-Time t
ON-MIN
75 ns
Minimum Off-Time t
OFF
75 ns
Current Limit
(Note 6) I
LIM
T
A
= 0°C to +85°C
I
ND
= 0 (0.47µH
inductor option)
Production tested at
I
LIM
= 00 setting
(Note 7)
I
LIM
= 00
(3.00A out) 4.15 5.05 5.95
A
I
LIM
= 01
(2.75A out) 4.75
I
LIM
= 10
(2.50A out) 4.45
I
LIM
= 11
(2.25A out) 4.15
T
A
= 0°C to +85°C
I
ND
= 1 (1.0µH inductor
option)
Production tested at
I
LIM
= 11 setting
(Note 7)
I
LIM
= 00
(3.00A out) 4.60
A
I
LIM
= 01
(2.75A out) 4.30
I
LIM
= 10
(2.50A out) 4.00
I
LIM
= 11
(2.25A out) 3.00 3.70 4.40
(VCHGIN = 5V, VBATT = 4.2V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Fast-charge current is set
for 1.5A, done current is set for 150mA. Limits are 100% production tested at TA = +25°C . Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
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3A Switching Mode Charger with FG
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Switching Charger Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REVERSE BOOST
BYP Voltage Adjustment Range
2.5V < V
BATT
< 4.5V. Adjustable from
3V to 5.75V, production tested at 3V,
5.0V and 5.75V settings
3 5.75 V
Reverse Boost Quiescent Current I
BYP
Not switching: output forced 200mV
above its target regulation voltage 1150 µA
Reverse Boost BYP Voltage in
OTG Mode V
BYP.OTG
5.1V setting 4.94 5.1 5.26 V
CHGIN Voltage in OTG Mode V
CHGIN.OTG
Mode = 0x05 or 0x0F, WCIN switch is
on, VCHGIN_REG = 4.9V, RIN2WCIN
+ RDSCHGIN < 300mI, OTG load
current ≤ 450mA
4.75 V
CHGIN Output Current Limit I
CHGIN.OTG.LIM
3.4V < V
BATT
< 4.5V, T
A
= +25°C
OTG_ILIM = 00 500 550 mA
OTG_ILIM = 01 900 990 mA
OTG_ILIM = 10 1200 1320 mA
OTG_ILIM=11 1500 1650 mA
Reverse Boost Output Voltage
Ripple
Discontinuous inductor current
(i.e., skip mode) ±150 mV
Continuous inductor current ±150 mV
CHARGER
BATT Regulation Voltage Range V
BATTREG
Programmable in 25mV steps (4 bits),
production tested at 3.65V and 4.4V
only.
3.65 4.7 V
BATT Regulation Voltage
Accuracy 3.65V and 4.7V
settings
T
A
= +25°C -0.75 +0.75 %
T
A
= 0°C to
+85°C -1 +1 %
Fast-Charge Current Program
Range
0A to 3.0A in 50mA steps, production
tested at 500,1000, 2000 and 3000mA
settings
0 3 A
Fast-Charge Current Accuracy
Programmed
currents ≥ 500mA,
V
BATT
> V
SYSMIN
(short mode),
production tested
at 500mA, 800mA,
1000mA, 2000mA,
3000mA settings
T
A
= +25°C -2.5 +2.5 %
T
A
= 0°C to
+85°C -5 +5 %
Programmed currents ≥ 500mA, V
BATT
< V
SYSMIN
(LDO mode), production
test at 800mA
-10 +10 %
(VCHGIN = 5V, VBATT = 4.2V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Fast-charge current is set
for 1.5A, done current is set for 150mA. Limits are 100% production tested at TA = +25°C . Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Switching Charger Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Fast-Charge Currents I
FC
T
A
= +25°C,
V
BATT
>
V
SYSMIN
Programmed for 3.0A 2925 3000 3075 mA
Programmed for 2.0A 1950 2000 2050 mA
Programmed for 1.0A 975 1000 1025 mA
Programmed for 0.5A 487.5 500 512.5 mA
Low-Battery Prequalication
Threshold V
PQLB
V
BATT
rising 2.8 2.9 3 V
Dead-Battery Prequalication
Threshold V
PQDB
V
BATT
rising 1.9 2 2.1 V
Prequalication Threshold
Hysteresis V
PQ-H
Applies to both V
PQLB
and V
PQDB
100 mV
Low-Battery Prequalication
Charge Current I
PQLB
Default setting = disabled 75 100 140 mA
Dead-Battery Prequalication
Charge Current I
PQDB
40 55 80 mA
Charger Restart Threshold
Range V
RSTRT
Adjustable, 100, 150, and 200; it can
also be disabled 100 150 200 mV
Charger Restart Deglitch Time 10mV overdrive, 100ns rise time 130 ms
Top-Off Current Program Range Programmable from 100 to 350mA in
8 steps. 100 350 mA
Top-Off Current Accuracy
(Note 8)
Gain 5 %
Offset 20 mA
Charge Termination Deglitch
Time t
TERM
2mV overdrive, 100ns rise/fall time 30 ms
Charger State Change Interrupt
Deglitch Time t
SCIDG
Excludes transition to timer fault state,
watchdog timer state 30 ms
Charger Soft-Start Time t
SS
1.5 ms
(VCHGIN = 5V, VBATT = 4.2V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Fast-charge current is set
for 1.5A, done current is set for 150mA. Limits are 100% production tested at TA = +25°C . Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Switching Charger Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SMART POWER SELECTOR
BATT to SYS Reverse Regulation
Voltage V
BSREG
I
BATT
= 10mA 30 mV
I
BATT
= 1A 60 mV
Load regulation during the reverse
regulation mode 30 mV/A
Minimum SYS Voltage Accuracy V
SYSMIN
Programmable from 3.4V to 3.7V in
100mV steps, V
BATT
= 2.8V, tested at
3.4V and 3.7V settings
-3 3 %
Maximum SYS Voltage V
SYSMAX
The maximum
system voltage:
V
SYSMAX
=
V
BATREG
+
R
BAT2SYS
x
I
BATT
V
BATREG
= 4.2V,
I
BATT
= 3.0A 4.245 4.32 V
The maximum
system voltage:
V
SYSMAX
=
V
BATREG
+
R
BAT2SYS
x
I
BATT
.
V
BATREG
= 4.7V,
I
BATT
= 3.0A 4.745 4.82 V
WATCHDOG TIMER
Watchdog Timer Period t
WD
80 s
Watchdog Timer Accuracy -20 0 +20 %
CHARGE TIMER
Prequalication Time t
PQ
Applies to both low-battery
prequalication and dead-battery
prequalication modes
35 min
Fast-Charge Constant Current +
Fast-Charge Constant Voltage
Time
t
FC
Adjustable from 4hrs to 16hrs in 2 hour
steps including a disable setting 8 hrs
Top-Off Time t
TO
Adjustable from 0min to 70min in 10min
steps 30 min
Timer Accuracy -20 +20 %
AVL FILTER
Internal AVL Filter Resistance 12.5 Ω
(VCHGIN = 5V, VBATT = 4.2V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Fast-charge current is set
for 1.5A, done current is set for 150mA. Limits are 100% production tested at TA = +25°C . Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Switching Charger Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
THERMAL FOLDBACK
Junction Temperature Thermal
Regulation Loop Setpoint
Program Range
T
JREG
Junction temperature when charge
current is reduced. Programmable from
+85°C to +130°C in 15°C steps, default
value is +100°C
85 130 °C
Thermal Regulation Gain A
TJREG
The charge current is decreased
6.7% of the fast charge current setting
for every degree that the junction
temperature exceeds the thermal
regulation temperature. This slope
ensures that the full-scale current of
3.0A is reduced to 0A by the time the
junction temperature is 20°C above
the programmed loop set point. For
lower programmed charge currents
such as 500mA, this slope is valid
for charge current reductions down
to 100mA; below 100mA the slope
becomes shallower but the charge
current still reduced to 0A if the
junction temperature is 20°C above the
programmed loop set point.
-150 mA/°C
BATTERY OVERCURRENT PROTECTION
Battery Overcurrent Threshold
Range I
BOVCR
Programmable from 3.0A to 4.5A in
0.25A steps, can be disabled 3 4.5 A
Battery Overcurrent Debounce
Time t
BOVRC
This is the response time for generating
the overcurrent interrupt ag 3 6 10 ms
Battery Overcurrent Protection
Quiescent Current I
BOVRC
3 +
I
BATT
/22000
µA
System Power-Up Current I
SYSPU
35 50 80 mA
System Power-Up Voltage V
SYSPU
V
SYS
rising, 100mV hysteresis 2 2.1 2.2 V
System Power-Up Response
Time t
SYSPU
Time required for circuit to activate from
an unpowered state (i.e., main-battery
hot insertion)
1 µs
SYSTEM SELF DISCHARGE WITH NO POWER
BATT Self-Discharge Resistor 600 Ω
SYS Self-Discharge Resistor 600 Ω
Self-Discharge Latch Time 300 ms
(VCHGIN = 5V, VBATT = 4.2V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Fast-charge current is set
for 1.5A, done current is set for 150mA. Limits are 100% production tested at TA = +25°C . Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
(VSYS = 2.8V to 4.5V, TA = -40°C to 85°C, typical values are at TA = +25°C, unless otherwise noted. Limits are 100% production tested
at TA = +25°C . Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and charac-
terization. Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Switching Charger Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DETBATB, INOKB, WCINOKB
DETBATB Logic Threshold V
IH
4% hysterisis 0.8 x
V
IO
V
Logic Input Leakage Current I
DETBATB
0.1 1 µA
Output Low Voltage INOKB,
WCINOKB I
SINK
= 1mA 0.4 V
Output High Leakage INOKB,
WCINOKB V
SYS
= 5.5V T
A
= +25°C -1 0 +1 µA
T
A
= +85°C 0.1 µA
Safeout LDOs Electrical Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SAFEOUT1
Output Voltage (Default On)
5V < VCHGIN < 5.5V, IOUT = 10mA,
SAFEOUT1 = 01 (default) 4.8 4.9 5 V
SAFEOUT1 = 00 4.85 V
SAFEOUT1 = 10 4.95 V
SAFEOUT1 = 11 3.3 V
Maximum Output Current
60 mA
Output Current Limit
60 150 320 mA
Dropout Voltage
VCHGIN = 5V, IOUT = 60mA 120 mV
Load Regulation
VCHGIN = 5.5V, 30µA < IOUT < 30mA 50 mV
Quiescent Supply Current
Not production tested 72 µA
Output Capacitor for Stable
Operation (Note 9)
0µA < IOUT < 30mA,
MAX ESR = 50mΩ 1 µF
Minimum Output Capacitor for
Stable Operation (Note 9)
0µA < IOUT < 30mA,
MAX ESR = 50mΩ 0.7 µF
Internal Off-Discharge
Resistance
1200 Ω
Note 9: Not production tested.
(VSYS = 2.8V to 4.5V, TA = -40°C to 85°C, typical values are at TA = +25°C, unless otherwise noted. Limits are 100% production tested
at TA = +25°C . Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and charac-
terization. Typical values are not guaranteed.))
(VSYS = 2.8V to 4.5V, TA = -40°C to 85°C, typical values are at TA = +25°C, unless otherwise noted. Limits are 100% production tested
at TA = +25°C . Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and charac-
terization. Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Safeout LDOs Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SAFEOUT2
Output Voltage (Default Off)
5V < VCHGIN < 5.5V, IOUT = 10mA,
SAFEOUT2 = 01 (default) 4.8 4.9 5 V
SAFEOUT2 = 00 4.85 V
SAFEOUT2 = 10 4.95 V
SAFEOUT2 = 11 3.3 V
Maximum Output Current
60 mA
Output Current Limit
60 150 320 mA
Dropout Voltage
VCHGIN = 5V, IOUT = 60mA 120 mV
Load Regulation
VCHGIN = 5.5V, 30µA < IOUT < 30mA 50 mV
Quiescent Supply Current
Not production tested 72 µA
Output Capacitor for Stable
Operation (Note 9)
0µA < IOUT < 30mA,
MAX ESR = 50mΩ 1 µF
Minimum Output Capacitor for
Stable Operation (Note 9)
0FA < IOUT < 30mA,
MAX ESR = 50mΩ 0.7 µF
Internal Off-Discharge
Resistance
1200 Ω
Fuel Gauge Electrical Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current
IDD0 Fuel gauge shut down (Note 10) 0.5 µA
IDD1
Fuel gauge active, average with
7.5% ADC duty cycle (Note 10) 35 70 µA
ADC Duty Cycle Duty 7.5 %
Parameter Capture Rate tACQ Period of ADC activation loop 0.1758 s
Regulator Output VBFG 1.5 1.8 1.98 V
VOLTAGE CHANNEL
VBATT Measurement Error VGERR
VBATT = 2.8V to 4.5V, TA = +25°C -7.5 +7.5 mV
TA = -40°C to +85°C -20 +20 mV
VBATT Measurement
Resolution VLSB 1.25 mV
VBATT Measurement Range VRANGE 2.8 4.98 V
(VSYS = 2.8V to 4.5V, TA = -40°C to 85°C, typical values are at TA = +25°C, unless otherwise noted. Limits are 100% production tested
at TA = +25°C . Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and charac-
terization. Typical values are not guaranteed.)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Fuel Gauge Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CURRENT CHANNEL
Current Measurement
Resolution ILSB 1.25 mA
Current Measurement Range IRANGE -3.6 +3.6 A
Current Measurement Offset IOERR
Long term average at zero input
current ±0.25 mA
Current Measurement
Symmetrical Error ISERR (Notes 11, 12, 13) 2% %
Current Measurement
Asymmetrical Error IAERR
±3000mA
(Notes 12, 13, 14)
-150 +150
mA±1000mA -20 +20
±300mA -9.5 +9.5
Linear Regulator Mode Current
Measurement Error ILRERR
+1500mA (Note 15) -225 +225 mA
+100mA -40 +40
Time-Base Accuracy tERR
VSYS = 3.7V at TA = +25°C ±1 %
TA = -40°C to +85°C -3.5 +3.5
THERMAL CHANNEL
Ratiometric Measurement
Accuracy, THM TGERR (Note 13) -0.5 +0.5
% of
full
scale
Ratiometric Measurement
Resolution, THM TLSB 0.0244
% of
full
scale
THMB Output Drive VOH_THMB IOH_THMB = -0.5mA VAVL -
0.1 V
THMB Precharge Time tPRE_THMB 12.7 ms
THMB Operating Range VTHMB 2.8 VAVL V
THMB Input Leakage IIN_THMB VTHMB = 5V -1 +1 µA
THM Input leakage IIN_THM -1 +1 µA
Note 2: Design guidance only, not tested during nal test.
Note 3: Input lters on the SDA and SCL inputs suppress noise spikes of less than 50ns.
Note 4: The CHGIN input must be less than VOVLO and greater than both VCHGIN_UVLO and VCHGIN2SYS for the charger to turn-on.
Note 5: The input voltage regulation loop decreases the input current to regulate the input voltage at VCHGIN_REG. If the input
current is decreased to ICHGIN_REG_OFF and the input voltage is below VCHGIN_REG, then the charger input is turned off.
Note 6: Production tested to ¼ of the threshold with LPM bit = 1 (¼ FET configuration).
Note 7: Production tested in charger DC-DC low-power mode (CHG_LPM bit = 1).
Note 8: Not production tested. Note 10: The total chip supply current includes the charger supply current in addition to the
supply current for the fuel gauge.
Note 11: Symmetrical error is the sum of odd order errors in the measured values at two inputs symmetrical around zero;
for example, ISERR_0.3A = (Error 0.3A - Error -0.3A)/2/0.3A x 100.
Note 12: Total current measurement error is the sum of the symmetrical and asymmetrical errors. Fuel gauge accuracy is sensitive to
asymmetrical error but insensitive to symmetrical error.
Note 13: Current and ratiometric measurement errors are production tested at VSYS = 3.7V and guaranteed by design at VSYS =
2.8V and 4.5V.
Note 14: Asymmetrical error is the sum of even order errors in the measured values at two inputs symmetrical around zero;
for example IAERR_0.3A = (Error 0.3A + Error -0.3A)/2.
Note 15: Total linear regulator mode current measurement error is simply the total error with respect to the input. This mode exists for
a short duration when charging an empty battery, hence this error has limited consequence.
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Electrical Characteristics (continued)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Pin Conguration
MAX77818
TOP VIEW
(BUMP SIDE DOWN)
A
B
C
D
WLP
(72 BUMPS WLP 9X8 BUMP ARRAY 0.4MM PITCH)
N/C PINS ARE FLOATING AND CAN BE CONNECTED AT BOARD-LEVEL IF NEEDED.
ALL TEST PINS (TEST1-6 AND VCCTEST) SHOULD BE GROUNDED IN THE END-USE APPLICATION.
*TOP VIEW = WAFER BACK-SIDE VIEW (BUMPS NOT VIEWABLE)
E
F
G
1
+
N.C. TEST4 SDA SCL WCINOKB GND_Q WCIN
2 3 4 5 6 7
VCC_TEST TEST3 TEST5 TEST6 VIO DETBATB SAFEOUT2
TEST1 TEST2 INTB N.C.INOKB N.C. BYP
GND_A GND_A GND_A GND_A GND_A AVL BYP
SYS_A N.C. GND_D N.C. SYS N.C. PVL
VBFG SYS_A N.C. N.C. SYS BAT_SN BST
THMB N.C. BATT BATT SYS BAT_SP CHGR
GSUB
N.C.
WCIN N.C.
BYP
SAFEOUT1
CHGIN CHGIN
CHGIN CHGIN
BYP BYP
CHGLX CHGLX
CHGLX CHGLX
THM BATT BATT SYS SYS CHGPG CHGPG CHGPG
H
8 9
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Pin Description
PIN NAME FUNCTION
A1, A9, C4,
C6, E2,
E4, E6, F3,
F4, G2, H1
N.C. No Connection
A2 TEST4 Test I/O Pin. Ground this pin in the application.
A3 SDA I2C Serial Data. Add an external 2.2kΩ pullup resistor to VIO.
A4 SCL I2C Serial Clock. Add an external 2.2kΩ pullup resistor to VIO.
A5 WCINOKB Wireless Charger Input Valid, Active-Low Logic Output Flag. Open-drain, active-low output that
indicates when valid voltage is present at WCIN and SYS.
A6 GND_Q Quiet Ground. Short to GND_A and GND_D.
A7, A8 WCIN
Wireless Charger Input. 6VDC protected input pin connected to Wireless charger power source.
The wireless charger may be active during OTG mode, or disabled using the WCINSEL bit.
Connect a 4.7µF/10V ceramic capacitor from WCIN to GND plane
B1 VCCTEST Test Mux Supply. Ground this pin in the application.
B2 TEST3 Test I/O. Ground this pin in the application.
B3 TEST5 Test I/O. Ground this pin in the application.
B4 TEST6 Test I/O. Ground this pin in the application.
B5 VIO Digital I/O Supply Input for I2C Interface.
B6 DETBATB
Battery Detection Active-Low Input. Connect this pin to the ID pin on the battery pack. If DETBATB
is pulled below 80% of the externally applied VIO voltage, this is an indication that the battery is
present and the charger starts when valid CHGIN and/or WCIN power is present. If DETBATB is
driven high to VIO voltage or left unconnected, this is an indication that the battery is not present
and the charger does not start. DETBATB is pulled high to VIO pin through an off-chip pullup
resistor.
B7 SAFEOUT2 Safeout LDO2 Output. Default off. Bypass with a 1µF ceramic capacitor to GND.
B8, C7,
D7, E8, E9 BYP
CHGIN Bypass. This pin can see up to OVP limit. Output of adapter Input current Limit block and
input to switching charger. BYP is also the boost converter output when the charger is operating
in reverse boost mode. Bypass with 2x10µF/16V ceramic capacitors from BYP to CHGPG ground
plane.
B9 SAFEOUT1 Safeout LDO1 Output. Default 4.9V and on when CHGIN power is valid. Bypass with a 1µF
ceramic capacitor to GND.
C1 TEST1 Test I/O. Ground this pin in the application.
C2 TEST2 Test I/O. Ground this pin in the application.
C3 INTB Interrupt Output. Active-low, open-drain output. Add a 200kΩ pullup resistor to VIO.
C5 INOKB Charger Input Valid, Active-Low Logic Output Flag. Open-drain output indicates when valid
voltage is present at both CHGIN and SYS or WCIN and SYS.
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Pin Description (continued)
PIN NAME FUNCTION
C8, C9,
D8, D9 CHGIN Charger Input. The adapter/USB charger input may be active, or disabled using the CHGINSEL
bit. Connect a 2.2µF/16V ceramic capacitor from CHGIN to GND plane.
D1–D5 GND_A Analog Ground. Short to GND_D and GND_Q.
E3 GND_D Digital Ground. Short to GND_A and GND_Q.
D6 AVL
Analog Voltage Level. Output of on-chip 5V LDO used to power on-chip, low-noise circuits.
Bypass with a 2.2µF/10V ceramic capacitor to GND. Powering external loads from AVL is not
recommended, other than pulldown resistors.
E1, F2 SYS_A Analog SYS Input
E5, F5, G5,
H5, H6 SYS System Power Connection. Connect system loads to this node. Bypass with 2x10µF ceramic
capacitors from SYS to CHGPG ground plane.
E7 PVL Internal Bias Regulator High-Current Output Bypass. Supports internal noisy and high-current
gate drive loads. Bypass to GND with a minimum 10µF/10V ceramic capacitor.
F1 VBFG
1.8V power supply output for Fuel Gauge. Bypass VBFG with a 0.1µF ceramic capacitor, VBFG is
not intended to power external circuitry.
F6 BAT_SN Battery Negative Differential Sense Connection. Connect to the negative or ground terminal close
to the battery.
F7 BST High-Side FET Driver Supply. Bypass BST to LX with a 0.1µF ceramic capacitor.
F8, F9,
G8, G9 CHGLX Charger Switching Node. Connect the inductor between CHGLX and SYS.
G1 THMB Pullup Voltage for THM Pin Pullup Resistor. Can be switched to save power.
G3, G4,
H3, H4 BATT Battery Power Connection. Connect to the positive terminal of a single-cell (or parallel cell) Li Ion
battery. Bypass BATT to CHGPG ground plane with a 10µF ceramic capacitor.
G6 BAT_SP Battery Positive Differential Sense Connection. Connect to the positive terminal close to the
battery.
G7 CHGRGSUB Substrate Charger Ground Connection. Connect with GND_A.
H2 THM Thermistor Connection. Determines battery temperature using ratiometric measurement.
H7–H9 CHGPG Charger Power Ground Connection
Detailed Description
System Faults
MAX77818 monitors the system for the following faults:
VSYS undervoltage lockout
VSYS overvoltage lockout
VSYS Fault
The system monitors the VSYS node for undervoltage and
overvoltage. The following describes the IC behavior if
any of these events is to occur.
VSYS Undervoltage Lockout (VSYSUVLO)
When charger input is valid and SYS node falls below
SYS UVLO, all charger and fuel gauge O type registers
are reset and following happen:
when DEADBAT < SYS < UVLO (= 2.5V), QBAT is on and
SYS is shorted to BAT.
when 0 < SYS < DEADBAT (= 2.0V), QBAT is off, but the
charger pulls up SYS from BAT with a constant current
of 50mA.
when charger input is invalid and battery is present.
when DEADBAT < SYS < UVLO (= 2.5V), QBAT is on and
SYS is shorted to BAT.
when 0 < SYS < DEADBAT (= 2.0V), QBAT is off.
VSYS Overvoltage Lockout (VSYSUVLO)
The absolute maximum ratings state that the SYS node
withstands up to 6V. The SYS OVLO threshold is set to
5.36V (typ). Ideally, VSYS should not exceed the battery
charge termination threshold. Systems must be designed
so that VSYS never exceeds 4.8V (transient and stead-
state). If the VSYS should exceed VSYSOVLO during a
fault, the MAX77818 resets the charger and fuel gauge
O type registers.
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Block Diagram
2.2µF
/16V
4CHGIN
4.7µF
/10V
2WCIN
10µF
/10V
PVL
2.2µF
/10V
AVL
INOKB
VSYS
VIO
WCINOKB
FROM
WC PAD
MICRO USB
CONNECTOR
CHARGER
INPUT SENSE
AND
CONTROL
VBUS
GND
AP
VIO
SDA
SCL
INTB
VIO
1µF
/6.3V I2C
INTERFACE
AND LOGIC
CONTROL
5V USBLDO
SAFEOUT1
1µF
/10V
AP
5V USBLDO
SAFEOUT2
1µF
/10V
CP
TEST
VCCTEST
TEST_
6
FUEL GAUGE
mg5
CHARGER SW
CONTROL,
REVERSE
BOOST, FUEL
GUAGE
BST
CHGLX
BYP 2 x 10µF/16V
5
CHGRGSUB
4
0.1µF
VSYS
CHGPG
SYS
2 x 10µF/10V
REVERSE
BLOCKING
BATT
3
5
4
10µF/
10V
VIO
BAT_SP
BAT_SN
THM
THMB 10kΩ
DETBAT
VBFG
0.1µF
GND_A GND_Q GND_D N.C.
11
MAX77818
SYS_A2
VSYS
5
0.47µH
Smart Power Selector is a trademark of Maxim Integrated
Products, Inc.
INTB
The MAX77818 uses one interrupt pin: INTB. The inter-
rupt is meant to indicate to the application processor that
the status of MAX77818 has changed. The INTB signal
is asserted whenever one or more interrupts are toggled,
and those interrupts are not masked. The application
processor reads the interrupts in two steps. First, the AP
reads the INTSRC register. This is a read-only register
that indicates which functional block is generating the
interrupt (i.e., charger and FG). Depending on the result
of the read, the next step is to read the actual interrupt
registers pertaining to the functional block.
For example, if the application processor reads 0x02
from INTSRC register, it means the top-level MAX77818
block has an interrupt generated. The next step is to read
the related interrupt register of the MAX77818 functional
block.
The INTB pin becomes high (cleared) as soon as the read
sequence of the last INT_ register that contains an active
interrupt starts. FG interrupts are cleared by setting new
threshold values. All interrupts can be masked to prevent
the INTB from being asserted for masked interrupts. A
mask bit in the INTM register implements masking. The
INTSRC register can still provide the actual interrupt
status of the masked interrupts, but the INTB pin is not
asserted.
Charger, Safeout LDO, and Charger Type
Detection Interaction
The charger type detection circuit performs charger
type detection and gates whether or not the charger is
enabled. The charger type detection circuit allows the
charger to be enabled once charge detection is complete,
depending on the type of charger detected and whether or
not it is USB 2.0 compliant. A manual override bit allows
the user to enable the charger regardless of the charger
type detection circuit charger detection status.
SAFEOUT1 is enabled by default once charger detection
is complete and CHGIN is valid regardless of DETBATB.
SAFEOUT2 can also be enabled once the same condi-
tions are met, and the user sets the ENSAFEOUT2 reg-
ister bit.
Switching Mode Charger
Features:
●Complete Li+/Li-poly battery charger
●Prequalification, constant current, constant voltage
●55mA dead-battery prequalification
●100mA low-battery prequalification current
●Adjustable constant current charge
• 0A to 3.0A in 50mA steps
• ±5% accuracy
●Adjustable charge termination threshold
• 100mA to 200mA in 25mA steps and 200mA to
350mA in 50mA steps
• ±5% accuracy
●Adjustable battery regulation voltage
• 3.625V to 4.700V in 25mV steps
• ±0.5% accuracy at T = +25°C
• ±1% accuracy
• Remote differential sensing
●Synchronous switch-mode design
●Reverse boost mode with adjustable VBYP from 3.0V
to 5.8V
●Smart Power Selector™
• Optimally distributes power between charge
adapter, system, and main battery
• When powered by a charge adapter, the main
battery can provide supplemental current to the
system
• The charge adapter and can support the system
without a main battery
●No external MOSFETs required
●Dual input
• Reverse leakage protection prevents the battery
leaking current to the inputs
• 4.0A adapter input
• 16V withstand, 14V operating
• Adjustable input current limit (100mA to 4.0A in
33.3mA steps (CHGIN_ILIM), 500mA default)
• Support AC-to-DC wall warts and USB adapters
• 1.26A wireless charger input
• 6V fault tolerant
• Adjustable input current limit (60mA to 1.26A in
20mA steps (WCIN_ILIM), 500mA default)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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21
●Charge safety timer
• Selectable: 4hr to 16hr in 2hr steps plus a disable
setting
●Die temperature monitor with thermal foldback loop
• Selectable die temperature thresholds (°C): 70,
85,100, and 115
●Input voltage dropout control allows operation from
high-impedance sources. Charge current is reduced
so input is not pulled below 4.3V.
● BATT to SYS switch is 12.8mΩ (typ).
●Dead battery detection
●Short-circuit protection
• Programmable BAT to SYS overcurrent threshold
from 3.0A to 4.5A in 0.25A steps plus a disable
setting
• DISIBS bit allows the host to disable the battery to
system discharge path to protect against a short-
circuit
• SYS short to ground
• BUCK current is limited by by the ILIM current
limit. BATT currents above the programmed by
B2SOVRC threshold generate an interrupt. The
host can then disable the battery to system dis-
charge path by setting DISIBS.
Figure 1. Simplified Charger Functional Diagram
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
www.maximintegrated.com Maxim Integrated
│
22
REVERSE
BLOCKING
CHGLX
BATT
CHGIN
CHGPGND
BST
BYP
SYS
UP TO 3.0A
CHARGE CURRENT
5.05V
(REVERSE BOOST MODE)
CHGIN INPUT CURRENT
LIMIT SWITCH
WCIN INPUT CURRENT
LIMIT AND 5.9V
OVERVOLTAGE SWITCH
WCIN
AVL
PVL
VBYP
VSYS
WCIN
CHGIN
VUSB/VADP
WIRELESS
+3.2V TO +14V OPERATING
UP TO 4.0A INPUT CURRENT
CHARGE AND
SMART
POWER PATH
CONTROLLER
BUCK/BOOST
CONTROLLER
MAX77818
Figure 2. Main Battery Charger Detailed Functional Diagram
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
www.maximintegrated.com Maxim Integrated
│
23
CHGIN
SYS
CHGLX
CHGPGND
BYP
BATT
INPUT CONTROL
2x10uF
25V
0603
2.2uF
10V
0402
Q
BAT
2x4.7uF
6.3V
0402
1.0µF
6.3V
0402
CONTROL
REGISTERS
0.47uH
BYP
MBATT
VUSB/VADP
JUNCTION
TEMPERATURE
SENSOR TEMP.
TO SYSTEM
UP TO 7.5A TOTAL
(3.0A FROM THE
INPUT AND 4.5A
FROM BATTERY.)
SYS
AVL
DRV_OUT
4MHZ
BUCK CONTROLLER
CHARGE
CONTROLLER
REVERSE BOOST
CONTROLLER
CHARGE
TIMER
4.7uF
25V
0603
VMBATT
VSYS
TJ
WATCHDOG
Q
HS
Q
LS
UP TO 3.0A OF
CHARGE
CURRENT AND
UP TO 4.5A OF
DISCHARGE
CURRENT
BAT_SP
BAT_SN
VBYP
ID
VIMBAT
+ID
R
INSD
+3.2V TO +14V OPERATING
UP TO 4.0A INPUT CURRENT
DETBATB
BATTGND
Q
WCIN
VUSB/VADP WCIN
10uF
6.3V
0603
Q
CHGIN
BST
2.2uF
10V
0402
PVL
REG
0.1uF
6.3V
0402
REVERSE
BLOCKING
VCHGIN
MAX77818
Detailed Description
The MAX77818 includes a full-featured switch-mode
charger for a one-cell lithium ion (Li+) or lithium polymer
(Li-poly) battery. As shown in Figure 2, the current limit
for CHGIN input is independently programmable from 0 to
3.0A in 33.3mA steps allowing the flexibility for connection
to either an AC-to-DC wall charger or a USB port. CHGIN
current limit default is set between 100mA and 500mA
with 500mA being the programmed default.
The synchronous switch-mode DC-DC converter uti-
lizes a high 4.0MHz switching frequency which is ideal
for portable devices because it allows the use of small
components while eliminating excessive heat genera-
tion. The DC-DC has both a buck and a boost mode of
operation. When charging the main battery the converter
operation as a buck. The DC-DC buck operates from a
3.2V to 14V source and delivers up to 3.0A to the battery.
Battery charge current is programmable from 0A to 3.0A.
As a boost converter, the DC-DC uses energy from the
main battery to boost the voltage at BYP. The boosted
BYP voltage is useful to provide the supply the USB OTG
voltage.
Maxim’s Smart Power Selector architecture makes the
best use of the limited adapter power and the battery’s
power at all times to supply up to 3.0A continuous (4A
peak) from the buck to the system. Additionally, supple-
ment mode provides additional current from the battery
to the system up to 4.5ARMS. Adapter power that is not
used for the system goes to charging the battery. All
power switches for charging and switching the system
load between battery and adapter power are included on
chip. No external MOSFETs are required.
Maxim’s proprietary process technology allows for low-
RDSON devices in a small solution size. The total dropout
resistance from adapter power input to the battery is
0.0999Ω (typ) assuming that the inductor has 0.04Ω of
ESR. This 0.0999Ω typical dropout resistance allows for
charging a battery up to 3.0A from a 5V supply. The resis-
tance from the BATT to SYS node is 0.0128Ω, allowing for
low power dissipation and long battery life.
A multitude of safety features ensures reliable charging.
Features include a charge timer, watchdog, junction ther-
mal regulation, over/undervoltage protection, and short-
circuit protection.
The BATT to SYS switch has overcurrent protection. See
the Main battery Overcurrent Protection section for more
information.
Smart Power Selector
The Smart Power Selector architecture is a network of
internal switches and control loops that distributes energy
between an external power source CHGIN, BYP, SYS,
and BATT.
Figure 1 shows a simplified arrangement for the smart
power selector’s power steering switches. Figure 2 shows
a more detailed arrangement of the smart power selector
switches and gives them the following names: QCHGIN,
QHS, QLS, and QBAT.
Switch and Control Loop Descriptions
Input Switch: QCHGIN provides the input current limit.
The input switch is completely on and does not provide
forward blocking. As shown in Figure 2, there are SPS
control loops that monitor the current through the input
switches as well as the input voltage.
DC-DC Switches: QHS and QLS are the DC-DC switches
that can operate as a buck (step-down) or a boost (step-
up). When operating as a buck, energy is moved from
BYP to SYS. When operating as a boost, energy is moved
from SYS to BYP. SPS control loops monitor the DC-DC
switch current, the SYS voltage, and the BYP voltage.
Battery-to-System Switch: QBAT controls the battery
charging and discharging. Additionally QBAT allows the
battery to be isolated from the system (SYS). An SPS
control loop monitors the QBAT current.
Control Bits
MODE configures the Smart Power Selector.
MINVSYS sets the minimum system voltage.
VBYPSET sets the BYP regulation voltage target.
B2SOVRC configures the main battery overcurrent pro-
tection.
Energy Distribution Priority:
With a valid external power source:
The external power source is the primary source of
energy.
The main battery is the secondary source of energy.
Energy delivery to BYP is the highest priority.
Energy delivery to SYS is the second priority.
Any energy that is not required by BYP or SYS is avail-
able to the main battery charger.
With no power source available at CHGIN:
The main battery is the primary source of energy.
Energy delivery to BYP is the highest priority.
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
www.maximintegrated.com Maxim Integrated
│
24
BYP includes the CHGIN if they are asked to supply
energy in a USB OTG type of application.
Energy delivery to SYS is the second priority.
BYP Regulation Voltage
When the DC-DC is enabled in boost only mode (MODE
= 0x08), the voltage from BYP to ground (VBYP) is regu-
lated to VBYPSET.
When the DC-DC is enabled in one of its USB OTG
modes (MODE = 0x09 or MODE = 0x0A), VBYP is set for
5.1V (VBYP.ORG).
When the DC-DC is off or in one of its buck modes
(MODE = 0x00 or MODE = 0x04 or MODE = 0x05) and
there is a valid power source at CHGIN, VBYP = VCHGIN -
ICHGIN x RQCHGIN When the DC-DC is off and there is no
valid power source at CHGIN, BYP is connected to SYS
with an internal 200Ω resistor. This 200Ω resistor keeps
BYP biased as SYS and allows for the system to draw
very light loads from BYP. IF the system loading on BYP
is more than 1.0mA then the DC-DC should be operated
in boost mode. Note that the inductor and the high-side
switch’s body diode are in parallel with the 200Ω from
SYS to BYP.
SYS Regulation Voltage
When the DC-DC is enabled as a buck and the charger is
disabled (MODE = 0x04), VSYS is regulated to VBATREG
(CHG_CV_PRM) and QBAT is off.
When the DC-DC is enabled as a buck and the charger
enabled but in a non-charging state such as done, watch-
dog suspend or timer fault (MODE = 0x05 and not charg-
ing), VSYS is regulated to VBATREG (CHG_CV_PRM) and
QBAT is off.
When the DC-DC is enabled as a buck and charging in
prequalification, fast-charge, or top-off modes (MODE
= 0x05 and charging), VSYS is regulated to VSYSMIN
when the VBATT < VSYSMIN; in this mode the QBAT
switch acts like a linear regulator and dissipates power
[P = (VSYSMIN - VBATT) x IBATT]. When VBATT>VSYSMIN,
then VSYS = VBATT - IBATT x RBAT2SYS; in this mode the
QBAT switch is closed.
In all of the above modes, if the combined SYS and BYP
loading exceed the input current limit, then VSYS drops to
VBATT - VBSREG and the battery provides supplemental
current. If the fuel gauge requests main battery informa-
tion (voltage and current) during this supplement mode,
then the QBAT switch is closed (VSYS = VBATT - IBATT
x RBAT2SYS) during the fuel gauge sample. If the fuel
gauge wants requests continuous samples from the main
battery during supplement mode, then the QBAT switch
eventually opens when IBATT decreases below 40mA.
When the DC-DC is enabled as a boost (MODE = 0x08 or
0x09 or 0x0A), then the QBAT switch is closed and VSYS
= VBATT - IBATT x RBAT2SYS
Battery Detect Input Pin (DETBATB)
DETBATB is tied to the ID pin of the battery pack. If
DETBATB is pulled below 80% of VIO pin voltage, this is
an indication that the main battery is present and the bat-
tery charger starts upon valid CHGIN. If DETBATB is left
unconnected or equal to VIO voltage, this indicates that
the battery is not present and the charger does not start
upon valid CHGIN, see Figure 3. The DETBATB is inter-
nally pulled to BATT through an external resistor.
DETBATB status bit is valid when BATT is not present.
Input Validation
As shown in Figure 4, the charger input is compared with
several voltage thresholds to determine if it is valid. A
charger input must meet the following three characteris-
tics to be valid:
CHGIN must be above VCHGIN_UVLO to be valid.
CHGIN must be below its overvoltage lockout threshold
(VOVLO).
CHGIN must be above the system voltage by VCHGIN2SYS.
CHGIN input generates a CHGIN_I interrupt when its
status changes. The input status can be read with
CHGIN_OK and CHGIN_DTLS. Interrupts can be masked
with CHGIN_M.
Figure 3. DETBATB Internal Circuitry and System Diagram
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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BATTERY
PACK
VCC
DETBATB
VIO
RBIAS
GND
NEG-
ID
2R
8R
SYSTEM
IC
RP
VCC
ADC
MAX77818
Input Current Limit
The default settings of the CHGIN_ILIM and MODE con-
trol bits are such that when a charge source is applied to
CHGIN, the MAX77818 turns its DC-DC converter on in
BUCK mode, limit VSYS to VBATREG, and limit the charge
source current to 500mA. All control bits are reset on
global shutdown.
Input Voltage Regulation Loop
An input voltage regulation loop allows the charger to be
well behaved when it is attached to a poor quality power
source (CHGIN pin) or wireless charger (WCIN pin). The
loop improves performance with relatively high-resistance
charge sources that exist when long cables are used or
devices are charged with noncompliant USB hub con-
figurations. Additionally, this input voltage regulation loop
improves performance with current limited adapters. If the
MAX77818’s input current limit is programmed above the
current limit threshold of given adapter, the input voltage
loop allows the MAX77818 to regulate at the current limit
of the adapter. Finally, the input voltage regulation loop
allows the MAX77818 to perform well with adapters that
have poor transient load response times.
The input voltage regulation loop automatically reducing
the input current limit in order to keep the input voltage
at VCHGIN_REG, VWCIN_REG. If the input current limit is
reduced to ICHGIN_REG_OFF (50mA typ) and the input
voltage is below VCHGIN_REG, then the charger input is
turned off. VCHGIN_REG, VWCIN_REG is programmable
with VCHGIN_REG and VWCIN_REG.
After operating with the input voltage regulation active,
a BYP_I interrupt is generated, BYP_OK is cleared and
BYP_DTLS = 0b1xxx. To optimize input power when
working with a current limited charge source, monitor the
BYP_DTLS while decreasing the input current limit. When
the input current limit is set below the limit of the adapter,
the input voltage rises. Although the input current limit
is lowered, more power can be extracted from the input
source when the input voltage is allowed to rise.
Example 1: Optimum use of the input voltage regulation
loop along with a current limited adapter.
Sequence of Events
VBATT = 3.2V, the system is operating normally
A 5.0V 1.2A current limited dedicated USB charger is
applied to CHGIN.
The DC-DC buck regulator turns on, VSYS is regulated
to VBATREG (4.2V) and the input is allowed to provide
100mA to the system.
The system detects that the charge source is a dedicated
USB charger and enables the battery charger (MODE
= 0x05) and programs an input current limit to 1.8A
(CHGIN_ILIM = 0x36 = 1.8A).
The input current limit starts to ramp up from 100mA to
1.8A, but at the input current limit of the adapter (1.2A),
the adapter voltage collapses. The MAX77818’s input-
voltage regulation loop prevents the adapter voltage from
falling below 4.3V (VCHGIN_REG = 4.3V). A BYP_I inter-
rupt is generated and BYP_DTLS3 is set.
With the input voltage regulation loop active, the adapter
provides 1.2A at 4.3V, which is a total of 5.04W being
delivered to the system.
Figure 4. Charger Input Validation
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
www.maximintegrated.com Maxim Integrated
│
26
INPUT IS
UNDERVOLTAGE
INPUT IS
OVERVOLTAGE
LOW INPUT TO SYS
HEADROOM
V
CHGIN2SYS
VCHGIN IS
INVALID
BAT
V
CHGINUVLO
V
VCHGINOVLO
VCHGIN
CHGIN
VCHGIN_OVLO
LIN2SYS
VCHGIN_UVLO VCHGIN_INVLD
The system software detects that the input voltage regu-
lation loop is active and it begins to ramp down the pro-
grammed input current limit. When the current limit ramps
down to 1.167A (CHGIN_ILIM), the adapter is no longer
in current limit and the adapter voltage increases from
4.3V to 5.0V.
With the adapter operating just below its current limit, it
provides 1.167A at 5.0V which is a total of 5.84W to the
system. This is 800mW more than when the adapter was
in current limit.
Input Self-Discharge
for Reliable Charger Input Interrupt
To ensure that a rapid removal and reinsertion of a charge
source always results in a charger input interrupt, the char-
ger input presents loading to the input capacitor to ensure
that when the charge source is removed the input voltage
decays below the UVLO threshold in a reasonable time.
A 10µF input capacitance charged up to the maximum
OVLO threshold (6.0V - VOVLO) decays down to the mini-
mum UVLO threshold (4.3V - VCHGINx_UVLO_MIN) within
300ms (tINSD). The input self-discharge is implemented by
with a 30kΩ resistor (RINSD) from CHGIN input to ground.
System Self-Discharge with No Power
To ensure a timely, complete, repeatable, and reliable
reset behavior when the system has no power, the
MAX77818 actively discharges the BATT and SYS nodes
when the main battery is removed and VSYS is less than
VSYSUVLO. As shown in Figure 5, the BATT and SYS
discharge resistors are both 600Ω.
Figure 5. Main Battery Charger High-Current Paths with Typical Parasitic Resistances and Self-Discharging Resistors
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
www.maximintegrated.com Maxim Integrated
│
27
SYS
CHGLX
BATT
DRV_OUT
4MHz
BUCK CONTROLLER
CHARGE CONTROLLER
REVERSE BOOST
CONTROLLER
QHS
QLS
SWITCHED
BODY DIODE
BAT_SP
BAT_SN
ID
BYP
VBUS
DM
DP
ID
GND
USB
CONNECTOR
CHGIN
RPAR1
20mΩ
2x 600Ω
VSYSUVLO
SYSTEM IS
UNDERVOLTAGE
MAIN-BATTERY IS
DISCONNECTED
RPAR8
20mΩ
DETBATB
WCIN
CHGPGND
VMBDC
VMBAT
BST
Q
BAT
R
PAR2
20mΩ
R
PAR4
20mΩ
R
PAR5
20mΩ
R
PAR6
20mΩ
R
PAR7
20mΩ
ID
MAX77818
Charge States
The MAX77818 utilizes several charging states to safely and quickly charge batteries as shown in Figure 6 and Figure
7. Figure 6 shows an exaggerated view of a Li+/Li-Poly battery progressing through the following charge states when
there is not system load and the die and battery are close to room temperature: prequalification fast-charge top-off
done.
Figure 6. Li+/Li-Poly Charge Profile
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
www.maximintegrated.com Maxim Integrated
│
28
V
PQLB
V
BATREG
I
CHG
≤ I
SET
I
TO
LOW-BATTERY
PREQUALIFICATION
CHG_DTLS[3:0]=0b0000
FAST CHARGE (CC)
CHG_DTLS[3:0]=0b0001
BATTERY VOLTAGEBATTERY CHARGE CURRENT
I
PQLB
V
PQDB
TIME
TIME
V
RSTRT
RESTART
FAST CHARGE (CV)
CHG_DTLS[3:0]=0b0010
0V
FAST CHARGE (CV)
CHG_DTLS[3:0]=0b0010
TOP-OFF
CHG_DTLS[3:0]=0b0011
DONE
CHG_DTLS[3:0]=0b0100
DONE
CHG_DTLS[3:0]=0b0100
STATES
0A
I
PQDB
CHARGER
ENABLED
DEAD-BATTERY
PREQUALIFICATION
CHG_DTLS[3:0]=0b0000
NOTE1
NOTE 1: A TYPICAL LI+/LI-POLY HAS AN INTERNAL BATTERY PACK PROTECTION CIRCUIT THAT WILL OPEN THE BATTERY CONNECTION
WHEN THE BATTERY’S CELL VOLTAGE IS LOWER THAN A DEAD BATTERY THRESHOLD (V
DB.FALLING
~2.5V). TO GET THE PACK PROTECTION
TO CLOSE AGAIN, THE CHARGER CHARGES THE BATTERY CAPACITOR WITH I
PQDB
UNTIL THE VOLTAGE EXCEEDS V
PQDB
. THEN THE
CHARGER CHARGES THE BATTERY CAPACITOR WITH I
PQLB
. WHEN THE BATTERY CAPACITOR’S VOLTAGE EXCEEDS V
DB.RISING
~2.6V,
THEN THE BATTERY PACK PROTECTION CIRCUIT CLOSES WHICH CONNECTS THE CELL TO THE CHARGER. V
DB.FALLING
AND V
DB.RISING
ARE NOT DETERMINED BY THE CHARGER – THEY ARE PROPERTIES OF THE BATTERY.
NOT TO SCALE, V
CHGIN
= 5.0V, I
SYS
= 0A, T
J
= 25°C
TOP-OFF
CHG_DTLS[3:0]=0b0011
Figure 7. Charger State Diagram
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
www.maximintegrated.com Maxim Integrated
│
29
FAST CHARGE (CC)
CHG_DTLS = 0x01
CHG_OK = 1
I
CHG
< = I
FC
V
MBATT
> V
PQLB
(SOFT START, CHG TIMER = 0)
V
MBATT
< V
PQLB
(CHG TIMER = 0)
TOP OFF
CHG_DTLS[3:0] = 0x03
CHG_OK = 1
I
CHG
< = I
FC
I
MBATT
< I
TO
FOR t
TERM
(CHG TIMER = 0 AND SUSPEND)
CHG TIMER > t
TO
DONE
CHG_DTLS = 0x04
CHG_OK = 1
I
CHG
= 0
TIMER FAULT
CHG_DTLS = 0x06
CHG_OK = 0
I
BAT
= 0
CHG TIMER > t
PQ
CHG TIMER > t
FC
LOW-BATTERY
PREQUALIFICATION
CHG_DTLS = 0x00
CHG_OK = 1
If PQEN = 1, then I
CHG
< = I
PQLB
If PQEN = 0, then I
CHG
< = I
FC
V
MBATT
= V
BATREG
FOR 56ms
V
MBATT
< V
BATREG
FAST CHARGE (CV)
CHG_DTLS = 0x02
CHG_OK = 1
I
CHG
< = I
FC
AND I
CHG
> I
TO
CHG TIMER > t
FC
V
MBATT
< (V
BATREG
- V
RSTRT
)
(NO SOFT START,
CHG TIMER = RESUME)
NO INPUT POWER OR
CHARGER DISABLED
CHG_DTLS = 0X08
CHG_OK = 1
I
CHG
= 0
CHG TIMER = 0
WD TIMER = 0
CHGIN IS VALID
AND MODE PROGRAMMED
FOR CHARGER ENABLED
(CHG TIMER = RESUME
WD TIMER = RESUME)
CHGIN IS INVALID
T
J
> T
SHDN
(CHG TIMER = 0
WD TIMER = 0)
ANY STATE
EXCEPT THERMAL
SHUTDOWN
MODE[3:0]
PROGRAMED THE
CHARGER TO BE OFF
THERMAL SHUTDOWN
CHG_DTLS = 0X0A
CHG_OK = 0
I
CHG
= 0
T
J
< T
SHDN
(CHG TIMER = SUSPEND
WD TIMER = SUSPEND)
V
MBATT
> V
PQDB
(SOFT START)
V
MBATT
< (V
BATREG
- V
RSTRT
)
(NO SOFT START,
CHG TIMER = RESUME)
CHG TIMER > t
PQ
DEAD-BATTERY
PREQUALIFICATION
CHG_DTLS = 0x00
CHG_OK = 1
I
CHG
< = I
PQDB
V
MBATT
< V
PQDB
(SOFT START)
FROM: ANY PREQUAL STATE, ANY FAST CHARGE STATE,
TOP-OFF, DONE OR TIMER FAULT.
RETURNS TO: THE SAME STATE THAT IT CAME FROM.
WATCHDOG Suspend
CHG_DTLS = 0x0B
CHG_OK = 0
I
CHG
= 0
WD TIMER > T
WD
(CHG TIMER = SUSPEND,
ONLY IF WDTEN = 1)
WDTCLR[1:0] = 0B10
(WD TIMER = 0 AND RESUME
CHG TIMER = RESUME)
No Input Power or Charger Disabled State
From any state shown in Figure 7 except thermal shut-
down, the no input power or charger disabled state is
entered whenever the charger is programmed to be off or
the charger input CHGIN is invalid. After being in this state
for tSCIDG, a CHG_I interrupt is generated, CHG_OK is
set and CHG_DTLS is set to 0x08
While in the no input power or charger disabled state, the
charger current is 0mA, the watchdog and charge timers
are forced to 0, and the power to the system is provided
by either the battery or the adapter. When both battery
and adapter power is available, the adapter provides
primary power to the system and the battery contributes
supplemental energy to the system if necessary.
To exit the no input power or charger disabled state, the
charger input must be valid and the charger must be
enabled.
Dead Battery Prequaliciation State
As shown in Figure 7, the dead battery prequalification
state occurs when the main battery voltage is less than
VPQDB. After being in this state for tSCIDG, a CHG_I inter-
rupt is generated, CHG_OK is set and CHG_DTLS is set
to 0x00. In the dead battery prequalification state charge
current into the battery is IPQDB.
Following events causes the state machine to exit this
state:
The main battery voltage rises above VPQDB and the
charger enters the next state in the charging cycle: low
battery prequalification.
If the battery charger remains in this state for longer than
tPQ, the charger state machine transitions to the timer
fault state.
If the watchdog timer is not serviced, the charger state
machine transitions to the watchdog suspend state.
Note that the dead battery prequalification state works
with battery voltages down to 0V. The low 0V operation
typically allows this battery charger to recover batteries
that have an open internal pack protector. Typically a
packs internal protection circuit opens if the battery has
seen an over current, undervoltage, or overvoltage. When
a battery with an open internal pack protector is used with
this charger, the low battery prequalification mode current
flows into the 0V battery. This current raises the pack’s
terminal voltage to the pointer where the internal pack
protection switch closes.
Note that a normal battery typically stays in the low bat-
tery prequalification state for several minutes or less.
Therefore, a battery that stays in low battery prequalifica-
tion for longer than tPQ may be experiencing a problem.
Fast-Charge Constant Current State
As shown in Figure 7, the fast-charge constant cur-
rent (CC) state occurs when the main battery voltage is
greater than the low battery prequalification threshold and
less than the battery regulation threshold (VPQLB < VBATT
< VBATREG). After being in the fast-charge CC state for
tSCIDG, a CHG_I interrupt is generated, CHG_OK is set
and CHG_DTLS = 0x01.
In the fast-charge CC state, the current into the battery is
less than or equal to IFC. Charge current can be less than
IFC for any of the following reasons:
The charger input is in input current limit.
The charger input voltage is low.
The charger is in thermal foldback.
The system load is consuming adapter current. Note
that the system load always gets priority over the battery
charge current.
Following events causes the state machine to exit this
state:
When the main battery voltage rises above VBATREG, the
charger enters the next state in the charging cycle: fast
charge (CV).
If the battery charger remains in this state for longer than
tFC, the charger state machine transitions to the timer
fault state.
If the watchdog timer is not serviced, the charger state
machine transitions to the watchdog suspend state.
The battery charger dissipates the most power in the
fast-charge constant current state. This power dissipa-
tion causes the internal die temperature to rise. If the die
temperature exceeds TREG, IFC is reduced.
Fast-Charge Constant Voltage State
As shown in Figure 7, the fast-charge constant volt-
age (CV) state occurs when the battery voltage rises to
VBATREG from the fast-charge CC state. After being in
the fast-charge CV state for tSCIDG, a CHG_I interrupt is
generated, CHG_OK is set and CHG_DTLS = 0x02.
In the fast-charge CV state the battery charger maintains
VBATREG across the battery and the charge current is
less than or equal to IFC. As shown in Figure 6, charger
current decreases exponentially in this state as the bat-
tery becomes fully charged.
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The smart power selector control circuitry may reduce
the charge current lower than the battery may otherwise
consume for any of the following reasons:
The charger input is in input current limit.
The charger input voltage is low.
The charger is in thermal foldback.
The system load is consuming adapter current. Note
that the system load always gets priority over the battery
charge current.
Following events causes the state machine to exit this
state:
When the charger current is below ITO for tterm, the char-
ger enters the next state in the charging cycle: TOP OFF.
If the battery charger remains in this state for longer than
tFC, the charger state machine transitions to the timer
fault state.
If the watchdog timer is not serviced, the charger state
machine transitions to the watchdog suspend state.
Top-Off State
As shown in Figure 7, the top-off state can only be
entered from the fast-charge CV state when the charger
current decreases below ITO for tTERM. After being in the
top-off state for tSCIDG, a CHG_I interrupt is generated,
CHG_OK is set and CHG_DTLS = 0x03. In the top-off
state the battery charger tries to maintain VBATREG
across the battery and typically the charge current is less
than or equal to ITO.
The smart power selector control circuitry can reduce
the charge current lower than the battery is able to.
Otherwise, consume for any of the following reasons:
The charger input is in input current limit.
The charger input voltage is low.
The charger is in thermal foldback.
The system load is consuming adapter current. Note
that the system load always gets priority over the battery
charge current.
Following events causes the state machine to exit this
state:
After being in this state for the top-off time (tTO), the char-
ger enters the next state in the charging cycle: DONE.
If VBATT < VBATREG - VRSTRT, the charger goes back to
the FAST CHARGE (CC) state.
If the watchdog timer is not serviced, the charger state
machine transitions to the watchdog suspend state.
Done State
As shown in Figure 7, the battery charger enters its done
state after the charger has been in the top-off state for
tTO. After being in this state for tSCIDG, a CHG_I inter-
rupt is generated, CHG_OK is cleared and CHG_DTLS
= 0x04.
Following events causes the state machine to exit this
state:
If VBATT < VBATREG – VRSTRT, the charger goes back to
the fast charge (CC) state.
If the watchdog timer is not serviced, the charger state
machine transitions to the watchdog suspend state.
In the done state, the charge current into the battery
(ICHG) is 0A. In the done state, the charger presents a
very low load (IMBDN) to the battery. If the system load
presented to the battery is low (<< 100µA), then a typical
system can remain in the done state for many days. If left
in the done state long enough, the battery voltage decays
below the restart threshold (VRSTRT) and the charger
state machine transitions back into the fast-charge CV
state. There is no soft-start (di/dt limiting) during the done
to fast-charge state transition.
Timer Fault State
The battery charger provides both a charge timer and
a watchdog timer to ensure safe charging. As shown
in Figure 7, the charge timer prevents the battery from
charging indefinitely. The time that the charger is allowed
to remain in its each of its prequalification states is tPQ.
The time that the charger is allowed to remain in the
fast-charge CC and CV states is tFC which is program-
mable with FCHGTIME. Finally, the time that the charger
is in the top-off state is tTO, which is programmable with
TO_TIME. Upon entering the timer fault state a CHG_I
interrupt is generated without a delay, CHG_OK is cleared
and CHG_DTLS = 0x06.
In the timer fault state the charger is off. The charger can
exit the timer fault state by programming the charger to
be off and then programming it to be on again through
the MODE bits. Alternatively, the charger input can be
removed and reinserted to exit the timer fault state. See
the any state bubble in the upper right of Figure 7.
Watchdog Timer
The battery charger provides both a charge timer and
a watchdog timer to ensure safe charging. As shown in
Figure 7, the watchdog timer protects the battery from
charging indefinitely in the event that the host hangs or
otherwise cannot communicate correctly. The watchdog
timer is disabled by default with WDTEN = 0. To use
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the watchdog timer feature enable the feature by setting
WDTEN. While enabled, the system controller must reset
the watchdog timer within the timer period (tWD) for the
charger to operate normally. Reset the watchdog timer by
programming WDTCLR = 0x01.
If the watchdog timer expires while the charger is in dead
battery prequalification, low battery prequalification, fast
charge CC or CV, top-off, done, or timer fault, the charg-
ing stops, a CHG_I interrupt is generated without a delay,
CHG_OK is cleared, and CHG_DTLS indicates that the
charger is off because the watchdog timer expired. Once
the watchdog timer has expired, the charger can be restart-
ed by programming WDTCLR = 0x01. The SYS node can
be supported by the battery and/or the adapter through the
DC-DC buck while the watchdog timer is expired.
Thermal Shutdown State
As shown in Figure 7, the thermal shutdown state occurs
when the battery charger is in any state and the junction
temperature (TJ) exceeds the device’s thermal shutdown
threshold (TSHDN). When TJ is close to TSHDN, the
charger has folded back the input current limit to 0A so
the charger and inputs are effectively off. Upon entering
this state, CHG_I interrupt is generated without a delay,
CHG_OK is cleared, and CHG_DTLS = 0x0A.
In the thermal shutdown state the charger is off and tim-
ers are suspended. The charger exits the temperature
suspend state and returns to the state it came from once
the die temperature has cooled. The timers resume once
the charger exits this state.
Main Battery Differential Voltage Sense
As shown in Figure 2, BAT_SP and BAT_SN are differ-
ential remote sense lines for the main battery. To improve
accuracy and decrease charging times, the battery char-
ger voltage sense is based on the differential voltage
between BAT_SP and BAT_SN.
Figure 5 shows the high-current paths of the battery
charger along with some example parasitic resistances. A
Maxim battery charger without the remote-sensing func-
tion would typically measure the battery voltage between
BATT and GND. In the case Figure 5 with a charge
current of 1A measuring from BATT to GND leads to a
VBATT that is 40mV higher than the real voltage because
of RPAR1 and RPAR7 (ICHG x (RPAR1 + RPQR7) = 1A x
40mΩ = 40mV). Since the charger thinks the battery volt-
age is higher than it actually is, it will enter its fast-charge
CV state sooner and the effective charge time may be
extended by 10 minutes (based on real lab measure-
ments). This charger with differential remote sensing does
not experience this type of problem because BAT_SP and
BAT_SN sense the battery voltage directly. To get the
maximum benefit from these sense lines connect them as
close as possible to the main battery connector.
OTG Mode
The DC-DC converter topology of the MAX77818 allows
it to operate as a forward buck converter or as a reverse
boost converter. The modes of the DC-DC converter are
controlled with MODE. When MODE = 0x09 or 0x0A the
DC-DC converter operates in reverse boost mode allow-
ing it to source current to CHGIN. These two modes
allow current to be sourced from CHGIN are commonly
referred to as OTG modes (the term OTG is based off of
the Universal Serial Bus’s On the Go concept).
When MODE = 0x09 or 0x0A the DC-DC converter
operates in reverse boost mode and regulates VBYP to
VBYP.OTG (5.1V typ) and the switch from BYP to CHGIN
is closed. The current through the BYP to CHGIN switch
is limited to the value programmed by OTG_ILIM. The two
OTG_ILIM options allow for supplying 100mA or 500mA
to an external load.. When the OTG mode is selected,
the unipolar CHGIN transfer function measures current
going out of CHGIN. When OTG mode is not selected,
the unipolar CHGIN transfer function measures current
going into CHGIN.
If the external OTG load at CHGIN exceeds ICHGIN.OTG.
ILIM, then a BYP_I interrupt is generated, BYP_OK = 0,
and BYP_DTLS = 0bxxx1. In response to an overload at
CHGIN during OTG mode operation, the BYP to CHGIN
switch is latched off. The BYP to CHGIN switch will auto-
matically try to retry in ~300ms. If the overload at CHGIN
persists, then the switch will toggle on and off with ~30ms
on and ~300ms off.
Main Battery Overcurrent Protection During
System Power-Up
The main battery overcurrent protection during system
power-up feature limits the main battery to system cur-
rent to ISYSPU as long as VSYS is less than VSYSPU.
This feature limits the surge current that typically flows
from the main battery to the device’s low-impedance
system bypass capacitors during a system power-up.
System power-up is anytime that energy from the battery
is supplied to SYS when VSYS < VSYSPU. This system
power-up condition typically occurs when a battery is hot-
inserted into an otherwise unpowered device. Similarly,
the system power-up condition could occur when the
DISIBS bit is driven low.
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When system power-up occurs due to hot insertion into
an otherwise unpowered device, a small delay of (tSYS-
PU) is required in order for this feature’s control circuits
to activate. A current spike over ISYSPU can occur during
this time.
Main Battery Overcurrent Protection Due to Fault
The MAX77818 protects itself, the battery, and the system
from potential damage due to excessive battery discharge
current. Excessive battery discharge current may occur
in a smartphone for several reasons such as exposure
to moisture, a software problem, an IC failure, a compo-
nent failure, or a mechanical failure that causes a short
circuit. The main battery overcurrent protection feature is
enabled with B2SOVRC; disabling this feature reduces
the main battery current consumption by IMBOVRC.
When the main battery (BATT) to system (SYS) discharge
current (IBATT) exceeds the programmed overcurrent
threshold for at least tMBOVRC, a BAT_I interrupt is
generated, BAT_OK is cleared, and BAT_DTLS reports
and overcurrent condition. Typically when the system’s
processor detects this overcurrent interrupt it executes a
housekeeping routine that tries to mitigate the overcurrent
situation. If the processor cannot correct the overcurrent,
then it can disable the BATT to SYS discharge path (B2S
switch) by driving DISIBS bit to a logic high.
There are different scenarios of how the MAX77818
responds to setting the DISIBS bit high depending on the
available power source and the state of the charger.
The MAX77818 is only powered from BATT and DISIBS
bit is set.
SYS collapses and is allowed to go to 0V.
DISIBS holds state.
To exit from this state, plug in a valid input charger, then
SYS is powered up, and the system wakes up.
The MAX77818 is powered from BATT and CHGIN, and
the charger buck is not switching and DISIBS bit is set.
To exit from this state, plug in a valid input charger, then
SYS is powered up and the system wakes up.
The MAX77818 is powered from BATT and CHGIN and
the charger buck is switching and DISIBS bit is set.
The DISIBIS bit is ignored.
Thermal Management
The MAX77818 charger uses several thermal manage-
ment techniques to prevent excessive battery and die
temperatures.
Thermal Monitor
The user can monitor thermistor temperature using the
fuel gauge and adjust the charger voltage/current as
needed.
Thermal Foldback
Thermal foldback maximizes the battery charge current
while regulating the MAX77818 junction temperature. As
shown in Figure 8, when the die temperature exceeds the
value programmed by REGTEMP (TJREG), a thermal lim-
iting circuit reduces the battery charger’s target current by
105mA/°C (ATJREG). The target charge current reduction
is achieved with an analog control loop (i.e., not a digital
reduction in the input current). When the thermal foldback
loop changes state a CHG_I interrupt is generated and
the system’s microprocessor may want to read the status
of the thermal regulation loop through the TREG status
bit. Note that the thermal foldback loop being active is
not considered to be abnormal operation and the thermal
foldback loop status does not affect the CHG_OK bit
(only information contained within CHG_DTLS affects
CHG_OK).
Analog Low-Noise Power Input (AVL) and PVL
As shown in Figure 2, AVL is a regulated output from
BYPC node. AVL is the power input for the MAX77818
charger’s analog circuitry. PVL has a 12.5Ω resistor
internal to the MAX77818 and a 10µF ceramic capacitor
external bypass capacitor to isolate noises from AVL.
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3A Switching Mode Charger with FG
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Figure 8. Charge Currents vs. Junction Temperature
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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CURRENT (A)
JUNCTION TEMPERATURE (°C)
I
FC
= 3.0A
I
FC
= 2.0A
1.0A
3.0A
2.0A
I
FC
= 1.0A
T
JREG
0.0A
BATTERY CHARGER OPERATION IN
THERMAL REGULATION GENERATES
A CHG_I INTERRUPT BIT AND SETS
THE TREG STATUS BIT
A
JTREG
= -105mA/°C
T
JREG
+9.5°C
T
JREG
+19°C
T
JREG
+28.6°C
DRAWN TO SCALE, V
CHGIN
= 5.0V, V
SYS
= 0A, CHGINA_ILIM IS SET FOR MAXIMUM
Figure 9: Power State Diagram
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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START OTG
(MODE B)
CHGIN OR WCIN
PRESENCE
I
OTG
> I
LIM.OTG
I
OTG
< I
LIM.OTG
START BOOST/OTG
I
OTG
> I
LIM.OTG
I
OTG
< I
LIM.OTG
END BOOST/OTG
END OTG
START OTG
END OTG
BOTH V
IN
< V
IN_UVLO_FALL
BOTH I
IN
< I
IN_low
(50mA)
BOTH V
IN
> V
IN_UVLO_RISE
V
WCIN
< V
IN_UVLO_FALL
I
WCIN
< I
WCIN_low
(50mA)
V
WCIN
> V
IN_UVLO_RISE
BATTERY-BOOST (OTG)
CHGIN = ON
WCIN = OFF
QBAT = ON
(MODE = 0x0A)
V
BYP
= V
BYP_OTG
V
SYS
= max(V
BAT
+ ΔV, V
SYSMIN
)
BATTERY ONLY
CHGIN = OFF
WCIN = OFF
QBAT = ON
(MODE = 0x00)
V
BYP
= V
CHGIN/WCIN
– IxR
V
SYS
= V
BAT
- IxR
CHGIN OR WCIN VALID
BATTERY DETECT,
FAULT REMOVED
BATTERY REMOVED,
FAULT
BATTERY DETECT,
FAULT REMOVED
BATTERY REMOVED,
FAULT
CHARGE-BUCK
CHGIN=ON or
WCIN=ON
QBAT=ON
(MODE=0x0D)
V
BYP
= V
CHGIN/WCIN
– IxR
V
SYS
= V
BAT
– IxR
NO INPUT POWER
CHGIN
AND WCIN INVALID
BATTERY-BOOST
CHGIN = OFF
WCIN = OFF
QBAT = ON
(MODE = 0x08)
V
BYP
= V
BYPSET
V
SYS
= max(V
BAT
+ ΔV, V
SYSMIN
)
NO CHGIN
AND NO WCIN
OTG FAULT (OCP)
OTG Interrupt 0xB0[7] = 1
NO CHARGE-BUCK (OTG)
CHGIN = ON
WCIN = ON
QBAT = OFF
(MODE = 0x0E)
V
BYP
= V
CHGIN/WCIN
– IxR
V
SYS
= V
EOC
START OTG
END OTG
BATTERY DETECT
BATTERY REMOVED
CHARGE-BUCK (OTG)
CHGIN = ON
WCIN = ON
QBAT = ON
(MODE = 0x0F)
V
BYP
= V
CHGIN/WCIN
– IxR
V
SYS
= V
BAT
– IxR
NO CHARGE-BUCK
QCHGIN = ON or
QWCIN = ON
QBAT = OFF
(MODE = 0x0C)
V
BYP
= V
CHGIN/WCIN
- IxR
Power States
The MAX77818 transitions between power states as
input/battery and load conditions dictate; see Figure 9.
The MAX77818 provides seven (7) power states and one
(1) no power state. Under power-limited conditions, the
power path feature maintains SYS and USB-OTG loads
at the expense of battery charge current. In addition, the
battery supplements the input power when required. As
shown, transitions between power states are initiated by
detection/removal of valid power sources, OTG events,
and under-voltage conditions. Details of the BYP and SYS
voltages are provided for each state.
No Input Power, MODE = undefined: No input adapter
or battery is detected. The charger and system is off.
Battery is disconnected and charger is off.
Battery Only, MODE = 0x00: Adapter and wireless char-
ger are invalid, outside the input voltage operating range
(QCHGIN = off, QWCIN = off). Battery is connected to
power the SYS load (QBAT = on), and boost is ready to
power OTG (Boost=standby), see Figure 10. Battery Only.
Battery Boost, MODE = 0x08: Adapter and Wireless
inputs are invalid, outside the input voltage operating
range (QCHGIN = off, QWCIN = off). Battery is connected
to power the SYS load (QBAT = on), and charger is oper-
ating in Boost mode (Boost = on). See Figure 11.
Figure 10. Battery-Only
Figure 11. Battery-Boost
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CHGIN BYP
CHGLX
SYS
OPEN
QLS
QHS
QCHGIN
QWCIN
REVERSE
BLOCKING
OPEN WCIN
V-SYS =
V- BATT– I- BATT
x R(QBAT)
I-BATT BATT
QBAT
MAX77818
V-BYP =
V- BYPSET
CHGIN BYP
CHGLX
SYS
OPEN
QLS
QHS
QCHGIN
QWCIN
REVERSE
BLOCKING
OPEN WCIN
V-SYS =
V- BATT– I- BATT
x R(QBAT)
I-BATT BATT
QBAT
MAX77818
Battery Boost
Battery Boost (OTG), MODE = 0x0A: Wireless input is
turned off (QWCIN = off) and OTG is active (QCHGIN =
on). Battery is connected to support SYS and OTG loads
(QBAT = on), and charger is operating in boost mode
(boost = on). See Figure 12.
No Charge Buck, MODE = 0x0C: Adapter or wireless
charger are detected, within the input voltage operating
range (QCHGIN = on or QWCIN = on). Battery is discon-
nected (QBAT = off), and charger is operating in buck
mode powering the SYS node. See Figure 13.
Figure 12. Battery Boost (OTG)
Figure 13. No Charge Buck
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3A Switching Mode Charger with FG
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V-BYP =
V- BYPSET
CHGIN BYP
CHGLX
SYS
V- OTG =
5.1V– I- OTG
x R(QCHGIN)
QLS
QHS
QCHGIN
QWCIN
REVERSE
BLOCKING
OPEN WCIN
V-SYS =
V- BATT– I- BATT
x R(QBAT)
I-BATT BATT
QBAT
I-OTG
MAX77818
V-BYP = V- CHGIN– I- QCHGIN x R(QCHGIN)
OR
V- BYP = V- WCIN– I- QWCIN x R(QWCIN)
CHGIN BYP
CHGLX
SYS
ADP
QLS
QHS
QCHGIN
QWCIN
REVERSE
BLOCKING
WC WCIN
V-SYS = V- BATT
BATT
QBAT
V- BATT = CHG_CV_PRM
OR
MAX77818
Charge Buck, MODE = 0x0D: Adapter or wireless char-
ger are detected, within the input voltage operating range
(QCHGIN = on or QWCIN = on). Battery is connected in
charge mode (QBAT = on), and charger is operating in
buck mode. See Figure 14.
No Change Buck (OTG), MODE = 0x0E: Wireless char-
ger is detected within the input voltage operating range
(QWCIN = on) and OTG is active (QCHGIN = of). Battery
is connected in charge mode (QBAT = on), and charger is
operating in buck mode. See Figure 15.
Figure 14. Charge Buck
Figure 15. No Charge Buck (OTG)
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3A Switching Mode Charger with FG
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V-BYP = V- CHGIN– I- QCHGIN x R(QCHGIN)
OR
V- BYP = V- WCIN– I- QWCIN x R(QWCIN)
CHGIN BYP
CHGLX
SYS
ADP
QLS
QHS
QCHGIN
QWCIN
REVERSE
BLOCKING
WC WCIN
V-SYS = MAX(MINVSYS, V-BATT+?)
BATT
QBAT
I- BATT
*MAY BE 0A(MAINTAIN CHARGE)
OR
MAX77818
V-BYP =
V- WCIN– [I- WC– I-OTG] x
R(QCHGIN)
CHGIN BYP
CHGLX
SYS
QLS
QHS
QCHGIN
QWCIN
REVERSE
BLOCKING
V- WC >
V- WCIN. UVLO
WCIN
V-SYS =
MAX(MINVSYS, V-BATT+?)
BATT
QBAT
I- BATT
I-OTG
V- OTG =
V - BYP– IOTG x
R(QCHGIN)
I- WCIN
MAX77818
Charge Buck (OTG), MODE = 0x0F: Wireless charger
is detected within the input voltage operating range
(QWCIN = on) and OTG is active (QCHGIN = on). Battery
is connected in charge mode (QBAT = on), and charger
is operating in buck mode powering the SYS node. See
Figure 16.
Safeout LDOs
Safeout with Input Overvoltage Protection
The safeout LDOs are linear regulators that provides an
output voltage of 3.3V, 4.85V, 4.9V, or 4.95V and can
be used to supply low voltage rated USB systems. The
SAFEOUT1 linear regulator turns on when CHGIN ≥
CHGIN_UVLO and ENSAFEOUT_ = logic-high regard-
less of charger enable or DETBATB. SAFEOUT_ is
disabled when CHGIN is greater than the overvoltage
threshold (13.7V typ). The safeout LDOs integrate high-
voltage MOSFETs to provide 14V protection at their
inputs, which are internally connected to the BYP.
SAFEOUT1 is default ON at 4.9V. SAFEOUT2 is default
off.
Fuel Gauge
The MAX77818 incorporates the ModelGauge m5 algo-
rithm that combines the excellent short-term accuracy and
linearity of a coulomb counter with the excellent long-term
stability of a voltage-based fuel gauge, along with tempera-
ture compensation to provide industry-leading fuel-gauge
accuracy. ModelGauge m5 cancels offset accumulation
error in the coulomb counter, while providing better short-
term accuracy than any purely voltage-based fuel gauge.
Additionally, the ModelGauge m5 algorithm does not suffer
from abrupt corrections that normally occur in coulomb-
counter algorithms, since tiny continual corrections are
distributed over time.
The device automatically compensates for aging, tem-
perature, and discharge rate and provides accurate state
of charge (SOC) in mAh or %, as well as time-to-empty
over a wide range of operating conditions. The device
provides two methods for reporting the age of the bat-
tery: reduction in capacity and cycle odometer.
The device provides precision measurements of current,
voltage, and temperature. Temperature of the battery
pack is measured using an external thermistor supported
by ratiometric measurements on an auxiliary input. A
2-wire (I2C) interface provides access to data and control
registers.
Features
●Accurate battery capacity and time-to-empty readings
●Estimation
• Temperature, age, and rate Compensated
• Does not require empty, full, or idle states to
●Maintain accuracy
●Precision measurement system
• No calibration required
Figure 16. Charge-Buck (OTG)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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V-BYP =
V- WCIN– [I- WC– I-OTG] x
R(QCHGIN)
CHGIN BYP
CHGLX
SYS
QLS
QHS
QCHGIN
QWCIN
REVERSE
BLOCKING
V- WC >
V- WCIN. UVLO
WCIN
V-SYS =
MAX(MINVSYS, V-BATT+?)
BATT
QBAT
I- BATT
I-OTG
V- OTG =
V - BYP– IOTG x
R(QCHGIN)
I- WCIN
MAX77818
●ModelGauge m5 algorithm
• Long-term inuence by voltage fuel gauge
●Cancels coulomb-counter drift
• Short-term inuence by coulomb counter
●Provides excellent linearity
• Adapts to cell characteristics
●External temperature-measurement network
• Actively switched thermistor resistive divider
• Reduces current consumption
●Low quiescent current
• 25µA active, < 0.5µA shutdown
●Alert Indicator for SOC, voltage, temperature, and
battery removal/insertion events
●At rate estimation of remaining capacity
I2C Interface
The MAX77818 acts as a slave transmitter/receiver. The
MAX77818 has the following slave address.
Slave Addresses
Charger : 0xD2/D3h
Clogic, GTEST and Safeout LDOs: 0xCCh/0xCDh
Fuel Gauge: 0x6C/0x6D. See the Fuel Gauge I2C
Protocol for details in Fuel Gauge section.
I2C Bit Transfer
One data bit is transferred for each clock pulse. The data
on SDA must remain stable during the high portion of the
clock pulse as changes in data during this time are inter-
preted as a control signal.
I2C Start and Stop Conditions
Both SDA and SCL remain High when the bus is not
busy. A high-to-low transition of SDA, while SCL is high
is defined as the start (S) condition. A low-to-high transi-
tion of SDA while SCL is high is defined as the stop (P)
condition.
Figure 17. I2C Slave Address Structure
Figure 18. I2C Bit Transfer
Figure 19. I2C Start and Stop
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I2C
DISABLED
I2C
ENABLED
IC TOP (CC/CDh)
SAFEOUT LDOs
FUEL GAUGE
(0x6C/0x6Dh)
CHARGER
(0xD2/D3h) I2C ADDRESS
IC ENABLED
STOP CONDITION
ANY STATE EXCEPT
DISABLED
IC DISABLED
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
MBBC821
SDA
SCL
START
CONDITION
STOP
CONDITION
SDA
SCL
MBBC821
S P
I2C System Conguration
A device on the I2C bus that generates a message is
called a transmitter and a device that receives the mes-
sage is a receiver. The device that controls the message
is the master. The devices that are controlled by the mas-
ter are called slaves.
I2C Acknowledge
The number of data bytes between the start and stop
conditions for the transmitter and receiver are unlimited.
Each 8-bit byte is followed by an acknowledge bit. The
acknowledge bit is a high-level signal put on SDA by the
transmitter during the time the master generates an extra
acknowledge-related clock pulse. A slave receiver that
is addressed must generate an acknowledge after each
byte it receives. Also, a master receiver must generate
an acknowledge after each byte it receives that has been
clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable low during the high period of the acknowl-
edge clock pulse (set-up and hold times must also be
met). A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this case,
the transmitter must leave SDA high to enable the master
to generate a stop condition.
Figure 20. I2C System Configuration
Figure 21. I2C Knowledge
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SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
START
CONDITION MBBC602
S
NOT ACKNOWLEDGE
ACKNOWLEDGE
CLOCK PULSE FOR
ACKNOWLEDGE
98
21
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
Master Transmits (Write Mode)
When master writes to slave, use the following format:
Master Reads After Setting Register Address (Write Register Address and Read Data)
When reading a specific register, use the following format:
Master Reads Register Data Without Setting Register Address (Read Mode)
When reading registers from the first address, use the following format:
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S SLAVE ADDRESS 0 AS REGISTER ADDRESS AS DATA AS P
B7 B0 B7 B7B0 B0
S: I2C START CONDITION BY MASTER
AS: ACKNOWLEDGEMENT BY SLAVE
P: I2C STOP CONDITION BY MASTER
R/Wn BYTES
AUTO INCREMENT
REGISTER ADDRESS
B7 B0 B7 B7B0 B0
S: I2C START CONDITION BY MASTER
AS: ACKNOWLEDGEMENT BY SLAVE
P: I2C STOP CONDITION BY MASTER
AM: ACKNOWLEDGEMENT BY MASTER
n BYTES
AUTO INCREMENT
REGISTER ADDRESS
S SLAVE ADDRESS 0 AS REGISTER ADDRESS AS SLAVE ADDRESS DATAS 1 AS AM
B7 B0
R/WR/W
P1DATA
NO ACKNOWLEDGEMENT
FROM MASTER
LAST BYTE
S: I2C START CONDITION BY MASTER
AS: ACKNOWLEDGEMENT BY SLAVE
P: I2C STOP CONDITION BY MASTER
S SLAVE ADDRESS 1 AS DATA AM DATA 1 P
B7 B0 B7 B7B0 B0
n BYTESn BYTES
R/W
AUTO INCREMENT
REGISTER ADDRESS
AUTO INCREMENT
REGISTER ADDRESS
NO ACKNOWLEDGEMENT
FROM MASTER
I2C Register Map and Detail Descriptions
Register Reset Conditions in R column
Type S: Registers are reset each time when SYS < SYS POR (~1.55V)
Type O: Registers are reset each time when SYS < SYS UVLO (2.55V max) or SYS > SYS OVLO or Die temp > 165°
(or MAX77818 transitions from on to off state)
Top Level I2C Registers
The MAX77818 acts as a slave transmitter/receiver. The slave address of the MAX77818 top is 0xCCh/0xCDh (OTP
option for 0xDC/0xDDh). The least significant bit is the read/write indicator.
The MAX77818’s tope level has the following registers:
0x20: PMIC ID Register
0x21: PMIC Version/Rev Register
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NAME FUNCTION ADDR TYPE RESET
PMICID PMIC ID 0x20 O 0x23
BIT MODE NAME RESET DESCRIPTION
3:0 R ID 0011 ID of MAX77818
7:4 R ID 0010
NAME FUNCTION ADDR TYPE RESET
PMICREV PMIC revision 0x21 O 0x80
BIT MODE NAME RESET DESCRIPTION
2:0 R REV —
Pass
0b000 = pass 1
0b001 = pass 2
0b010 = pass 3
7:3 R VERSION —
Version
0b00000 = zmo
0b00001 = ymo
…
Null Trim Version
0b10000 = tmo
0b10001 = umo
0x22: Interrupt Source
0x23: Interrupt Source Mask
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NAME FUNCTION ADDR TYPE RESET
INTSRC Interrupt source 0x22 S 0x00
BIT MODE NAME RESET DESCRIPTION
0 R CHGR_INT 0 0: No charger interrupt.
1: Charger interrupt is detected.
1 R FG_INT 0 0 = No interrupt pending from FG block.
1 = interrupt from FG block is detected .
2 R SYS_INT 0 0: No SYS INT
1: SYS interrupt is detected.
3 R RSVD 0 Reserved
4 R RSVD 0 Reserved
5 R RSVD 0 Reserved
6 R RSVD 0 Reserved
7 R RSVD 0 Reserved
NAME FUNCTION ADDR TYPE RESET
INTSRCMASK Interrupt source mask 0x23 S 0xFF
BIT MODE NAME RESET DESCRIPTION
0 R/W CHGR_INT_MASK 1 1: Charger interrupt is masked.
1 R/W FG_INT_MASK 1 1: FG interrupt is masked.
2 R/W SYS_INT_MASK 1 1: SYS interrupt is masked.
3 R/W RSVD 1 Reserved
4 R/W RSVD 1 Reserved
5 R/W RSVD 1 Reserved
6 R/W RSVD 1 Reserved
7 R/W RSVD 1 Reserved
0x24: SYSTEM Interrupt
0x26: SYSTEM Interrupt Source Mask
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NAME FUNCTION ADDR TYPE RESET
SYSINTSRC SYS interrupt source 0x24 S 0x00
BIT MODE NAME RESET DESCRIPTION
0 R SYSUVLO_INT 0 0: No SYSUVLO INT.
1: SYSUVLO interrupt is detected (falling).
1 R SYSOVLO_INT 0 0: No SYSOVLO interrupt.
1: SYSOVLO interrupt is detected (rising and falling).
2 R TSHDN_INT 0: No TSHDN interrupt.
1: TSHDN interrupt is detected.
3 R RSVD 0 Reserved
4 R RSVD 0 Reserved
5 R RSVD 0 Reserved
6 R RSVD 0 Reserved
7 R TM_INT 0 0: Test mode interrupt is not set.
1: Test mode interrupt is set.
NAME FUNCTION ADDR TYPE RESET
SYSINTMASK System interrupt mask 0x26 S 0xFF
BIT MODE NAME RESET DESCRIPTION
0 R/W SYSUVLO_INT_MASK 1 1: SYSUVLO interrupt is masked.
1 R/W SYSOVLO_INT_MASK 1 1: SYSUVLO interrupt is masked.
2 R/W TSHDN_INT_MASK 1 1: Thermal shutdown interrupt is masked.
3 R/W RSVD 1 Reserved
4 R/W RSVD 1 Reserved
5 R/W RSVD 1 Reserved
6 R/W RSVD 1 Reserved
7 R/W TM_INT_MASK 0 1: INT test mode interrupt is masked.
Charger I2C Registers
The MAX77818’s charger has convenient default register
settings and a complete charger state machine that allow
it to be used with minimal software interaction. Software
interaction with the register map enhances the charger
by allowing a high degree of configurability. An easy-to-
navigate interrupt structure and in-depth status reporting
allows software to quickly track the changes in the char-
ger’s status.
Register Protection
The CHG_CNFG_01, CHG_CNFG_02, CHG_CNFG_03,
CHG_CNFG_04, CHG_CNFG_05, and CHG_CNFG07
registers contain settings for static parameters that are
associated with a particular system and battery. These
static settings are typically set once each time the sys-
tem’s microprocessor runs its boot-up initialization code;
then they are not changed again until the microproces-
sor re-boots. CHGPROT allows for blocking the “write”
access to these static settings to protect them from being
changed unintentionally. This protection is particularly
useful for critical parameters such as the battery charge
current CHG_CC and the battery charge voltage CHG_
CV_PRM
Determine the following registers bit settings by consider-
ing the characteristics of the battery. Maxim recommends
that CHG_CC be set to the maximum acceptable charge
rate for your battery – there is typically no need to actively
adjust the CHG_CC setting based on the capabilities of
the source at CHGIN, system load, or thermal limitations
of the PCB; the smart power selector intelligently manag-
es all these parameters to optimize the power distribution.
Charger Restart Threshold CHG_RSTRT
Fast-Charge Timer (tFC) FCHGTIME
Fast-Charge Current CHG_CC
Top-Off Time TO_TIME
Top-Off Current TO_ITH
Battery Regulation Voltage CHG_CV_PRM
0xC6: SAFEOUT LDO Control
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NAME FUNCTION ADDR TYPE RESET
SAFEOUTCTRL SAFEOUT linear
regulator control 0xC6 O 0x75
BIT MODE NAME RESET DESCRIPTION
1:0 R/W SAFEOUT1[1:0] 01
SAFEOUT1 output voltage
00: 4.85V
01: 4.90V (default)
10: 4.95V
11: 3.3V.
3:2 R/W SAFEOUT2[3:2] 01
SAFEOUT2 output voltage
00: 4.85V
01: 4.90V (default)
10: 4.95V
11: 3.3V
4 R/W ACTDISSAFEO1 1 0: No active discharge
1: Active discharge
5 R/W ACTDISSAFEO2 1 0: No active discharge
1: Active discharge
6 R/W ENSAFEOUT1 1
SAFEOUTLDO1 enable bit
0: Disable SAFEOUT1.
1: Enable SAFEOUT1.
7 R/W ENSAFEOUT2 0
SAFEOUTLDO2 enable bit
0: Disable SAFEOUT2.
1: Enable SAFEOUT2.
Determine the following register bit settings by consider-
ing the characteristics of the system:
Low Battery Prequalification Enable PQEN
Minimum System Regulation Voltage MINVSYS
Junction Temperature Thermal Regulation
Loop Setpoint REGTEMP
Interrupt, Mask, OK, and Detail Registers
The battery charger section of the MAX77818 provides
detailed interrupt generation and status for the following
subblocks:
Charger Input
Charger State Machine
Battery
Bypass Node
State changes on any subblock report interrupts through
the CHG_INT register. Interrupt sources are masked from
affecting the hardware interrupt pin when bits in the CHG_
INT_MASK register are set. The CHG_INT_OK register
provides a single-bit status indication of whether the inter-
rupt generating sub-block is okay or not. The full status
of interrupt generating subblock is provided in the CHG_
DETAILS_00, CHG_DETAILS_01, CHG_DETAILS_02,
and CHG_DETAILS_03 registers.
Note that CHG_INT, CHG_INT_MASK and CHG_INT_OK
use the same bit position for each interrupt generating
block to simplify software development.
Interrupt bits are automatically cleared upon reading a
given interrupt register. When all pending CHG_INT inter-
rupts are cleared, the top level interrupt bit deasserts.
CHG_INT Register Bit Description (0xB0)
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NAME FUNCTION ADDR TYPE RESET
CHG_INT Charger interrupt 0xB0 O 0x00
BIT MODE NAME RESET DESCRIPTION
0 R/C BYP_I 0
Bypass Node Interrupt
0 = The BYP_OK bit has not changed since the last time this bit was read.
1 = The BYP_OK bit has changed since the last time this bit was read.
1 R/C RSVD 0 Reserved
2 R/C BATP_I 0
Battery Presence Interrupt.
0 = The BATP_OK bit has not changed since the last time this bit was read.
1 = The BATP_OK bit has changed since the last time this bit was read.s
3 R/C BAT_I 0
Battery Interrupt
0 = The BAT_OK bit has not changed since the last time this bit was read.
1 = The BAT_OK bit has changed since the last time this bit was read.
4 R/C CHG_I 0
Charger Interrupt
0 = The CHG_OK bit has not changed since the last time this bit was read.
1 = The CHG_OK bit has changed since the last time this bit was read.
5 R/C WCIN_I 0
WCIN Interrupt.
0 = The WCIN_OK bit has not changed since the last time this bit was read.
1 = The WCIN_OK bit has changed since the last time this bit was read.
6 R/C CHGIN_I 0
CHGIN Interrupt.
0 = The CHGIN_OK bit has not changed since the last time this bit was read.
1 = The CHGIN_OK bit has changed since the last time this bit was read.
7 R/C AICL_I 0
AICL interrupt
0=The AICL_OK bit has not changed since the last time this bit was read.
1=The AICL_OK bit has changed since the last time this bit was read.
CHG_INT_MASK Register Bit Description (0xB1)
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NAME FUNCTION ADDR TYPE RESET
CHG_INT_MASK Charger interrupt
mask 0xB1 O 0xFF
BIT MODE NAME RESET DESCRIPTION
0 R/W BYP_M 1
Bypass Interrupt Mask
0 = Unmasked
1 = Masked
1 R/W RSVD 1 Reserved
2 R/W BATP_M 1
Battery Presence Interrupt Mask
0 = Unmasked
1 = Masked
3 R/W BAT_M 1
Battery Interrupt Mask
0 = Unmasked
1 = Masked
4 R/W CHG_M 1
Charger Interrupt Mask
0 = Unmasked
1 = Masked
5 R/W WCIN_M 1
WCIN Interrupt Mask
0 = Unmasked
1 = Masked
6 R/W CHGIN_M 1
CHGIN Interrupt Mask
0 = Unmasked
1 = Masked
7 R/W AICL_M 1
AICL Interrupt Mask
0 = Unmasked
1 = Masked
CHG_INT_OK Register Bit Description (0xB2)
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NAME FUNCTION ADDR TYPE RESET
CHG_INT_OK Charger status 0xB2 O 0x00
BIT MODE NAME RESET DESCRIPTION
0 R BYP_OK 0
Single-Bit Bypass Status Indicator. See BYP_DTLS for more information.
0 = Something powered by the bypass node has hit current limit. i.e., BYP_
DTLS ≠ 0x00.
1 = The bypass node is okay.
i.e., BYP_DTLS = 0x00.
1 R RSVD 0 Reserved
2 R BATP_OK 0
BAT present status indicator.
0 = Main Battery is not present
1 = Main Battery is present.
3 R BAT_OK 0
Single-Bit Battery Status Indicator. See BAT_DTLS for more information.
0 = The battery has an issue or the charger has been suspended, i.e., BAT_
DTLS ≠ 0x03 or 0x04
1 = The battery is okay.
i.e., BAT_DTLS = 0x03 or 0x04
4 R CHG_OK 0
Single-Bit Charger Status Indicator. See CHG_DTLS for more information.
0 = The charger has suspended charging or TREG = 1
i.e., CHG_DTLS ≠ 0x00 or 0x01 or 0x02 or 0x03 or 0x05 or 0x08
1 = The charger is okay or the charger is off
i.e., CHG_DTLS = 0x00 or 0x01 or 0x02 or 0x03 or 0x05 or 0x08
5 R WCIN_OK 0
Single-Bit WCIN Input Status Indicator. See WCIN_DTLS for more
information.
0 = The WCIN input is invalid.
i.e., WCIN_DTLS ≠ 0x03.
1 = The WCIN input is valid.
i.e., WCIN_DTLS = 0x03.
6 R CHGIN_OK 0
Single-Bit CHGIN Input Status Indicator. See CHGIN_DTLS for more
information.
0 = The CHGIN input is invalid.
i.e., CHGIN_DTLS ≠ 0x03.
1 = The CHGIN input is valid.
i.e., CHGIN_DTLS = 0x03.
7 R AICL_OK 0
AICL_OK
0 = AICL mode
1 = Not in AICL mode
CHG_DETAILS_00 Register Bit Description (0xB3)
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NAME FUNCTION ADDR TYPE RESET
CHG_DTLS_00 Charger details
00 0xB3 O 0x00
BIT MODE NAME RESET DESCRIPTION
0 R BATP_DTLS 0
Battery Detection
0 = Battery presence
1 = No battery presence
2:1 R RSVD 00 Reserved
4:3 R WCIN_DTLS 00
WCIN Details
0x00 = VWCIN is invalid. VWCIN < VWCIN_UVLO
0x01 = VWCIN is invalid.
VWCIN < VMBAT + VWCIN2SYS and VWCIN > VWCIN_UVLO
0 x 02 = VWCIN is invalid. VWCIN>VWCIN_OVLO
0 x 03 = VWCIN is valid. VWCIN > VWCIN_UVLO,
VWCIN > VMBAT + VWCIN2SYS, VWCIN < VWCIN_OVLO
6:5 R CHGIN_DTLS 00
CHGIN Details
0x00 = VBUS is invalid. VCHGIN < VCHGIN_UVLO
0x01 = VBUS is invalid. VCHGIN < VMBAT + VCHGIN2SYS and
VCHGIN > VCHGIN_UVLO
0x02 = VBUS is invalid. VCHGIN > VCHGIN_OVLO
0x03 = VBUS is valid. VCHGIN > VCHGIN_UVLO,
VCHGIN > VMBAT + VCHGIN2SYS, VCHGIN < VCHGIN_OVLO
7 R RSVD 0 Reserved
CHG_DETAILS_01 Register Bit Description (0xB4)
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NAME FUNCTION ADDR TYPE RESET
CHG_DTLS_01 Charger details 01 0xB4 O 0x00
BIT MODE NAME RESET DESCRIPTION
3:0 R CHG_DTLS 0000
Charger Details
0x00 = charger is in dead-battery prequalication or low-battery prequalication
mode, CHG_OK = 1, VMBATT < VPQLB, TJ < TJSHDN
0x01 = charger is in fast-charge constant current mode, CHG_OK = 1,
VMBATT < VBATREG, TJ < TJSHDN
0x02 = charger is in fast-charge constant voltage mode, CHG_OK = 1,
VMBATT = VBATREG, TJ < TJSHDN
0x03 = charger is in top-off mode, CHG_OK = 1, VMBATT ≥ VBATREG, TJ < TJSHDN
0x04 = charger is in done mode, CHG_OK=0, VMBATT > VBATREG - VRSTRT,
TJ < TJSHDN
0x06 = charger is in timer fault mode, CHG_OK = 0, VMBATT < VBATOV,
if BAT_DTLS = 0b001 then VMBATT < VBATPQ, TJ < TJSHDN
0x07 = charger is in DETBAT = High suspend mode, CHG_OK = 0,
VMBATT < VBATOV, if BAT_DTLS = 0b001 then VMBATT<VPQLB, TJ < TJSHDN
0x08 = Charger is off, charger input invalid and/or charger is disabled, CHG_OK = 1.
0x09 = Reserved
0x0A = Charger is off and the junction temperature is > TJSHDN, CHG_OK = 0.
0x0B = Charger is off because the watchdog timer expired, CHG_OK = 0.
0x0C-0x0F = Reserved
6:4 R BAT_DTLS 000
Battery Details
0x00 = No battery and the charger is suspended.
0x01 = VMBATT < VPQLB. This condition is also reported in the CHG_DTLS as 0x00
0x02 = the battery is taking longer than expected to charge. This could be due to high
system currents, an old battery, a damaged battery or something else. Charging has
suspended and the charger is in its timer fault mode. This condition is also reported
in the CHG_DTLS as 0x06.
0x03 = the battery is okay and its voltage is greater than the minimum system voltage
(VSYSMIN < VMBATT), QBAT is on and VSYS is approximately equal to VMBATT.
0x04 = the battery is okay but its voltage is low: VPQLB < VMBATT<VSYSMIN.
QBAT is operating like an LDO to regulate VSYS to VSYSMIN.
0x05 = the battery voltage is greater than the battery overvoltage ag threshold
(VBATOVF) or it has been greater than this threshold within the last 37.5ms. VBATOVF
is set to a percentage above the VBATREG target as programmed by CHG_CV_PRM.
Note that this ag is only be generated when there is a valid input or when the DC-
DC is operating as a boost.
0x06 = the battery is overcurrent or it has been overcurrent for at least 6ms since the
last time this register has been read.
0x07 = Reserved
In the event that multiple faults occur within the battery details category, overcurrent
has priority followed by no battery, then overvoltage, then timer fault, then below
prequel.
CHG_DETAILS_01 Register Bit Description (0xB4) (continued)
CHG_DETAILS_02 Register Bit Description (0xB5)
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BIT MODE NAME RESET DESCRIPTION
7 R TREG 0
Temperature Regulation Status
0 = The junction temperature is less than the threshold set by REGTEMP and the full
charge current limit is available.
1 = The junction temperature is greater than the threshold set by REGTEMP and the
charge current limit may be folding back to reduce power dissipation.
NAME FUNCTION ADDR TYPE RESET
CHG_DTLS_02 Charger details 02 0xB5 O 0x00
BIT MODE NAME RESET DESCRIPTION
3:0 R BYP_DTLS 0000
Bypass Node Details. All bits in this family are independent from each other. They are
grouped together only because they all relate to the health of the BYP node and any
change in these bits generates a BYP_I interrupt.
BYP_DTLS0 = OTGILIM = 0bxxx1
BYP_DTLS1 = BSTILIM = 0bxx1x
BYP_DTLS2 = BCKNegILIM = 0bx1xx
********************************
0x00=The bypass node is okay.
0bxxx1=The BYP to CHGIN switch (OTG switch) current limit was reached within the
last 37.5ms.
0bxx1x=The BYP reverse boost converter has hit its current limit -- this condition
persists for 37.5ms.
0bx1xx= The BYP buck converter has hit the max negative demand current limit.
7:4 R RSVD 00 Reserved
CHG_CNFG_00 Register Bit Description (0xB7)
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NAME FUNCTION ADDR TYPE RESET
CHG_CNFG_00 Charger conguration
00 0xB7 O 0x05
BIT MODE NAME RESET DESCRIPTION
3:0 R/W MODE 0101
Smart Power Selector Conguration
0x00 = 0b0000 = charger = off, OTG = off, buck = off, boost = off. The QBAT switch is
on to allow the battery to support the system. BYP may or may not be biased based
on the CHGIN availability.
0x01 = 0b0001 = same as 0b0000
0x02 = 0b0010= same as 0b0000
0x03 = 0b0011= same as 0b0000
0x04 = 0b0100 = charger = off, OTG = off, buck = on, boost = off. When there is a
valid input, the buck converter regulates the system voltage to be VBATREG.
0x05 = 0b0101 = charger = on, OTG = off, buck = on, boost = off. When there is a
valid input, the battery is charging.
VSYS is the larger of VSYSMIN and ~VMBATT + IMBATT x RBAT2SYS.
0x06 = 0b0110 = same as 0b101
0x07 = 0b0111 = same as 0b101
0x08 = 0b1000 = charger = off, OTG = off, buck = off, boost = on. The QBAT switch
is on to allow the battery to support the system and the charger’s DC-DC operates as
a boost converter. The BYP voltage is regulated to VBYPSET. QCHGIN is off. .
0x09 = 0b1001=same as 0b1000
0x0A = 0b1010 = charger = off, OTG = on, buck = off, boost = on. The QBAT switch
is on to allow the battery to support the system, the charger’s DC-DC operates as a
boost converter. QCHGIN is on allowing it to source current up to ICHGIN.OTG.MAX.
The boost target voltage is 5.1V (VBYP.OTG) .
0x0B = reserved
0x0C = 0b1100 = charger = off, OTG = off, buck = on, boost = on. When there is
a valid input, the system is supported from that input: VSYS = 4.2V. When input is
invalid the boost is on with a target voltage that is VBYPSET
0x0D = 0b1101 = charger = on, OTG = off, buck = on, boost = on. When there is
a valid input, the system is supported from that input: VSYS is the larger of VSYSMIN
and ~VMBATT + IMBATT x RBAT2SYS. When input is invalid the boost is on with a
target voltage that is VBYPSET
0x0E = 0b1110=charger=off, OTG = on, buck = on, boost = on. When there is a
valid WCIN input, the system is supported from that input: VSYS = 4.2V and QCHGIN
is on, allowing it to source current up to ICHGIN.OTG.MAX. When WCIN input is
invalid the boost is on with a target voltage of 5.1V (VBYP.OTG).
0x0F = 0b1111 = charger = on, OTG = on, buck = on, boost = on. When there is
a valid WCIN input, the system is supported from that input: VSYS is the larger of
VSYSMIN and ~VMBATT + IMBATT x RBAT2SYS. QCHGIN is on allowing it to source
current up to ICHGIN.OTG.MAX. When WCIN input is invalid the boost is on with a
target voltage of 5.1V (VBYP.OTG)
CHG_CNFG_00 Register Bit Description (0xB7) (continued)
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BIT MODE NAME RESET DESCRIPTION
4 R/W WDTEN 0
Watchdog Timer Enable Bit.
While enabled, the system controller must reset the watchdog timer within the
timer period (tWD) for the charger to operate normally. Reset the watchdog timer by
programming WDTCLR = 0x01.
0 = Watchdog Timer disabled
1 = Watchdog Timer enabled
5 R/W SPREAD 0
Spread Spectrum Feature
Feature is operational both for 9V and 12V CHGIN input voltage.
Feature is not guaranteed to be operational for 5V CHGIN/WCIN input voltage.
When feature is not operational, it can be kept enabled without side effect.
0: Disabled
1: Enabled
6 R/W DISIBS 0
MBATT to SYS FET Disable Control
0 = MBATT to SYS FET is controlled by the power path state machine.
1 = MBATT to SYS FET is forced off.
7 R/W OTG_CTRL 0
OTG FET Control
0 = Forces the CHGIN input switch to be on when in Mode = 0x0E or 0x0F.
1 = The CHGIN turns off anytime power switches between WCIN and BATT.
CHG_CNFG_01 Register Bit Description (0xB8)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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NAME FUNCTION ADDR TYPE RESET
CHG_CNFG_01 Charger details 01 0xB8 O
R/W (protected with CHGPROT) 0x10
BIT MODE NAME RESET DESCRIPTION
2:0 R/W FCHGTIME 001
Fast-Charge Timer Duration (tFC)
0x00 = disable
0x01 = 4hrs
0x02 = 6hrs
0x03 = 8hrs
0x04 = 10hrs
0x05 = 12hrs
0x06 = 14hrs
0x07 = 16hrs
3 R/W FSW 0
Switching Frequency Option
0: 4MHz
1: 2MHz
5:4 R/W CHG_RSTRT 01
Charger Restart Threshold
0x00 = 100mV below the value programmed by CHG_CV_PRM
0x01 = 150mV below the value programmed by CHG_CV_PRM
0x02 = 200mV below the value programmed by CHG_CV_PRM
0x03 = Disabled
6 R/W LSEL 0
Inductor Selection
0:0.47µH (for 4MHz without restriction)
2MHz/0.47µH option can be used only in the charge mode and is
forbidden in following use cases:
Boost mode
Buck mode
1:1µH (for 2MHz and 4MHz option)
7 R/W PQEN 0
Low Battery Prequalication Mode Enable
0 = Low battery prequalication mode is disabled.
1 = Low battery prequalication mode is enabled.
CHG_CNFG_02 Register Bit Description (0xB9)
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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NAME FUNCTION ADDR TYPE RESET
CHG_CNFG_02 Charger
conguration 02 0xB9 O
R/W (protected with CHGPROT) 0x09
BIT MODE NAME RESET DESCRIPTION
5:0 R/W CHG_CC 001001
(450mA)
Fast-Charge Current Selection. When the charger is enabled, the charge
current limit is set by these bits. These bits range from 0.10A (0x00) to 3.0A
(0x3C) in 50mA step. Note that the rst 3 codes are all 100mA
Bits (mA) Bits (mA) Bits (mA) Bits (mA)
0x00 100 0x10 800 0x20 1600 0x30 2400
0x01 100 0x11 850 0x21 1650 0x31 2450
0x02 100 0x12 900 0x22 1700 0x32 2500
0x03 150 0x13 950 0x23 1750 0x33 2550
0x04 200 0x14 1000 0x24 1800 0x34 2600
0x05 250 0x15 1050 0x25 1850 0x35 2650
0x06 300 0x16 1100 0x26 1900 0x36 2700
0x07 350 0x17 1150 0x27 1950 0x37 2750
0x08 400 0x18 1200 0x28 2000 0x38 2800
0x09 450 0x19 1250 0x29 2050 0x39 2850
0x0A 500 0x1A 1300 0x2A 2100 0x3A 2900
0x0B 550 0x1B 1350 0x2B 2150 0x3B 2950
0x0C 600 0x1C 1400 0x2C 2200 0x3C 3000
0x0D 650 0x1D 1450 0x2D 2250 0x3D 3000
0x0E 700 0x1E 1500 0x2E 2300 0x3E 3000
0x0F 750 0x1F 1550 0x2F 2350 0x3F 3000
Note that the thermal foldback loop can reduce the battery charger’s target
current by ATJREG
7:6 R/W OTG_ILIM 00
CHGIN Output Current Limit in OTG Mode (ICHGIN.OTG.LIM)
When MODE = 0x09 or 0x0A the CHGIN current limit is set at the following
current limit:
00 = 500mA
01 = 900mA
10 =1200mA
11 = 1500mA
CHG_CNFG_03 Register Bit Description (0xBA):
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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NAME FUNCTION ADDR TYPE RESET
CHG_CNFG_03 Charger
conguration 03 0xBA O
R/W (protected with CHGPROT) 0xDA
BIT MODE NAME RESET DESCRIPTION
2:0 R/W TO_ITH 010
(150mA)
Top-Off Current Threshold. The charger transitions from its fast-charge
constant voltage mode to its top-off mode when the charger current decays
to the value programmed by this register. This transition generates a CHG_I
interrupt and causes the CHG_DTLS register to report top-off mode. This
transition also starts the top-off time as programmed by TO_TIME.
0x00 = 0.1A
0x01 = 0.125A
0x02 = 0.15A
0x03 = 0.175A
0x04 = 0.2A
0x05 = 0.25A
0x06 = 0.3A
0x07 = 0.35A
5:3 R/W TO_TIME 011
(30min)
Top-Off Timer Setting
0x00 = 0min
0x01 = 10min
0x02 = 20min
0x03 = 30min
0x04 = 40min
0x05 = 50min
0x06 = 60min
0x07 = 70min
7:6 R/W ILIM 11
Program Buck Peak Current Limit
00: support ICHG=3.00A
01: support ICHG=2.75A
10: support ICHG= 2.50A
11: support ICHG=2.25A
CHG_CNFG_04 Register Bit Description (0xBB):
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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NAME FUNCTION ADDR TYPE RESET
CHG_CNFG_04 Charger
conguration 04 0xBB O
R/W (protected with CHGPROT) 0x96
BIT MODE NAME RESET DESCRIPTION
5:0 R/W CHG_CV_PRM 010110
(4.2V)
Primary Charge Termination Voltage Setting
When the charger is enabled and the main-battery temperature is < T3 if
JEITA = 1 or < T4 if JEITA = 0, then, the charger’s battery regulation voltage
(VBATREG) is set by CHG_CV_PRM.
BITS V BITS V BITS V
0x00 3.650 0x10 4.050 0x20 4.425
0x01 3.675 0x11 4.075 0x21 4.450
0x02 3.700 0x12 4.100 0x22 4.475
0x03 3.725 0x13 4.125 0x23 4.500
0x04 3.750 0x14 4.150 0x24 4.525
0x05 3.775 0x15 4.175 0x25 4.550
0x06 3.800 0x16 4.200 0x26 4.575
0x07 3.825 0x17 4.225 0x27 4.600
0x08 3.850 0x18 4.250 0x28 4.625
0x09 3.875 0x19 4.275 0x29 4.650
0x0A 3.900 0x1A 4.300 0x2A 4.675
0x0B 3.925 0x1B 4.325 0x2B 4.700
0x0C 3.950 0x1C 4.340
0x0D 3.975 0x1D 4.350
0x0E 4.000 0x1E 4.375
0x0F 4.025 0x1F 4.400
7:6 R/W MINVSYS 10
(3.6V)
Minimum System Regulation Voltage (VSYSMIN)
0x00 = 3.4V
0x01 = 3.5V
0x02 = 3.6V
0x03 = 3.7V
CHG_CNFG_06 Register Bit Description (0xBD):
CHG_CNFG_07 Register Bit Description (0xBE):
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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NAME FUNCTION ADDR TYPE RESET
CHG_CNFG_06 Charger
conguration 06 0xBD O 0x00
BIT MODE NAME RESET DESCRIPTION
1:0 R/W WDTCLR 00
Watchdog Timer Clear Bits
Writing 01 to these bits clears the watchdog timer when the watchdog timer
is enabled.
0x00 = the watchdog timer is not cleared
0x01 = the watchdog timer is cleared
0x02 = the watchdog timer is not cleared
0x03 = the watchdog timer is not cleared
3:2 R/W CHGPROT 00
Charger Settings Protection Bits
Writing 11 to these bits unlocks the write capability for the registers who
are protected with CHGPROT writing any value besides 11 locks these
registers.
0x00 = write capability is locked
0x01 = write capability is locked
0x02 = write capability is locked
0x03 = write capability is unlocked
7:4 R/W RSVD 0000 Reserved
NAME FUNCTION ADDR TYPE RESET
CHG_CNFG_07 Charger
conguration 07 0xBE O
R/W (protected with CHGPROT) 0x40
BIT MODE NAME RESET DESCRIPTION
4:0 R/W RSVD 00000 Reserved
6:5 R/W REGTEMP 10
Junction Temperature Thermal Regulation Loop Set point.
The charger’s target current limit starts to foldback and the TREG bit is set if
the junction temperature is greater than the REGTEMP setpoint.
0x00 = 85°C
0x01 = 100°C
0x02 = 115°C
0x03 = 130°C
7 R/W RSVD 0 Reserved
CHG_CNFG_09 Register Bit Description (0xC0):
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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NAME FUNCTION ADDR TYPE RESET
CHG_CNFG_09 Charger
conguration 09 0xC0 O 0x0F
BIT MODE NAME RESET DESCRIPTION
6:0 R/W CHGIN_ILIM 0x0F
(0.50A)
Maximum Input Current Limit Selection
7-bit adjustment from 100mA to 4.0A in 33mA steps. Note that the rst 4
codes are all 100mA:
Bits Unit
(mA) Bits Unit
(mA) Bits Unit
(mA) Bits Unit
(mA)
0x00 100 0x20 1067 0x40 2133 0x60 3200
0x01 100 0x21 1100 0x41 2167 0x61 3233
0x02 100 0x22 1133 0x42 2200 0x62 3267
0x03 100 0x23 1167 0x43 2233 0x63 3300
0x04 133 0x24 1200 0x44 2267 0x64 3333
0x05 167 0x25 1233 0x45 2300 0x65 3367
0x06 200 0x26 1267 0x46 2333 0x66 3400
0x07 233 0x27 1300 0x47 2367 0x67 3433
0x08 267 0x28 1333 0x48 2400 0x68 3467
0x09 300 0x29 1367 0x49 2433 0x69 3500
0x0A 333 0x2A 1400 0x4A 2467 0x6A 3533
0x0B 367 0x2B 1433 0x4B 2500 0x6B 3567
0x0C 400 0x2C 1467 0x4C 2533 0x6C 3600
0x0D 433 0x2D 1500 0x4D 2567 0x6D 3633
0x0E 467 0x2E 1533 0x4E 2600 0x6E 3667
0x0F 500 0x2F 1567 0x4F 2633 0x6F 3700
0x10 533 0x30 1600 0x50 2667 0x70 3733
0x11 567 0x31 1633 0x51 2700 0x71 3767
0x12 600 0x32 1667 0x52 2733 0x72 3800
0x13 633 0x33 1700 0x53 2767 0x73 3833
0x14 667 0x34 1733 0x54 2800 0x74 3867
0x15 700 0x35 1767 0x55 2833 0x75 3900
0x16 733 0x36 1800 0x56 2867 0x76 3933
0x17 767 0x37 1833 0x57 2900 0x77 3967
0x18 800 0x38 1867 0x58 2933 0x78 4000
0x19 833 0x39 1900 0x59 2967 0x79 4000
0x1A 867 0x3A 1933 0x5A 3000 0x7A 4000
0x1B 900 0x3B 1967 0x5B 3033 0x7B 4000
0x1C 933 0x3C 2000 0x5C 3067 0x7C 4000
0x1D 967 0x3D 2033 0x5D 3100 0x7D 4000
0x1E 1000 0x3E 2067 0x5E 3133 0x7E 4000
0x1F 1033 0x3F 2100 0x5F 3167 0x7F 4000
7 R/W RSVD 0 Reserved
CHG_CNFG_10 Register Bit Description (0xC1):
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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NAME FUNCTION ADDR TYPE RESET
CHG_CNFG_10 Charger
conguration 09 0xC1 O 0x19
BIT MODE NAME RESET DESCRIPTION
5:0 R/W WCIN_ILIM 0x19
(0.50A)
Maximum Input Current Limit Selection
6bit adjustment from 60mA to 1.260A in 20mA steps. Note that the rst 4
codes are all 60mA:
Bits (mA) Bits (mA)
0x00 60 0x20 640
0x01 60 0x21 660
0x02 60 0x22 680
0x03 60 0x23 700
0x04 80 0x24 720
0x05 100 0x25 740
0x06 120 0x26 760
0x07 140 0x27 780
0x08 160 0x28 800
0x09 180 0x29 820
0x0A 200 0x2A 840
0x0B 220 0x2B 860
0x0C 240 0x2C 880
0x0D 260 0x2D 900
0x0E 280 0x2E 920
0x0F 300 0x2F 940
0x10 320 0x30 960
0x11 340 0x31 980
0x12 360 0x32 1000
0x13 380 0x33 1020
0x14 400 0x34 1040
0x15 420 0x35 1060
0x16 440 0x36 1080
0x17 460 0x37 1100
0x18 480 0x38 1120
0x19 500 0x39 1140
0x1A 520 0x3A 1160
0x1B 540 0x3B 1180
0x1C 560 0x3C 1200
0x1D 580 0x3D 1220
0x1E 600 0x3E 1240
0x1F 620 0x3F 1260
7:6 R/W RSVD 00 Reserved
CHG_CNFG_11 Register Bit Description (0xC2):
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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NAME FUNCTION ADDR TYPE RESET
CHG_CNFG_11 Charger
conguration 11 0xC2 O 0x00
BIT MODE NAME RESET DESCRIPTION
6:0 R/W VBYPSET 0x00
(3V)
Bypass Target Output Voltage in Boost Mode
3V (0x00) to 5.8V (0x70) in 0.025V steps. This setting is valid for the “boost
only” mode (MODE = 0x08).
Bits Unit
(mA) Bits Unit
(mA) Bits Unit
(mA) Bits Unit
(mA)
0x00 3.000 0x20 3.800 0x40 4.600 0x60 5.400
0x01 3.025 0x21 3.825 0x41 4.625 0x61 5.425
0x02 3.050 0x22 3.850 0x42 4.650 0x62 5.450
0x03 3.075 0x23 3.875 0x43 4.675 0x63 5.475
0x04 3.100 0x24 3.900 0x44 4.700 0x64 5.500
0x05 3.125 0x25 3.925 0x45 4.725 0x65 5.525
0x06 3.150 0x26 3.950 0x46 4.750 0x66 5.550
0x07 3.175 0x27 3.975 0x47 4.775 0x67 5.575
0x08 3.200 0x28 4.000 0x48 4.800 0x68 5.600
0x09 3.225 0x29 4.025 0x49 4.825 0x69 5.625
0x0A 3.250 0x2A 4.050 0x4A 4.850 0x6A 5.650
0x0B 3.275 0x2B 4.075 0x4B 4.875 0x6B 5.675
0x0C 3.300 0x2C 4.100 0x4C 4.900 0x6C 5.700
0x0D 3.325 0x2D 4.125 0x4D 4.925 0x6D 5.725
0x0E 3.350 0x2E 4.150 0x4E 4.950 0x6E 5.750
0x0F 3.375 0x2F 4.175 0x4F 4.975
0x10 3.400 0x30 4.200 0x50 5.000
0x11 3.425 0x31 4.225 0x51 5.025
0x12 3.450 0x32 4.250 0x52 5.050
0x13 3.475 0x33 4.275 0x53 5.075
0x14 3.500 0x34 4.300 0x54 5.100
0x15 3.525 0x35 4.325 0x55 5.125
0x16 3.550 0x36 4.350 0x56 5.150
0x17 3.575 0x37 4.375 0x57 5.175
0x18 3.600 0x38 4.400 0x58 5.200
0x19 3.625 0x39 4.425 0x59 5.225
0x1A 3.650 0x3A 4.450 0x5A 5.250
0x1B 3.675 0x3B 4.475 0x5B 5.275
0x1C 3.700 0x3C 4.500 0x5C 5.300
0x1D 3.725 0x3D 4.525 0x5D 5.325
0x1E 3.750 0x3E 4.550 0x5E 5.350
0x1F 3.775 0x3F 4.575 0x5F 5.375
7 R/W RSVD 0 Reserved
CHG_CNFG_12 Register Bit Description (0xC3):
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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NAME FUNCTION ADDR TYPE RESET
CHG_CNFG_12 Charger
conguration 12 0xC3 O 0x67
BIT MODE NAME RESET DESCRIPTION
2:0 R/W B2SOVRC 111
BAT to SYS Overcurrent Threshold
0x00 = Disabled
0x01 = 3.00A
0x02 = 3.25A
0x03 = 3.50A
0x04 = 3.75A
0x05 = 4.00A
0x06 = 4.25A
0x07 = 4.50A
4:3 R/W VCHGIN_REG 00
CHGIN Voltage Regulation Threshold (VCHGIN_REG) Adjustment
The CHGIN to GND Minimum Turn-On Threshold (VCHGIN_UVLO) also
scales with this adjustment.
0x00 = VCHGIN_REG = 4.3V and VCHGIN_UVLO = 4.5V
0x01 = VCHGIN_REG = 4.7V and VCHGIN_UVLO = 4.9V
0x02 = VCHGIN_REG = 4.8V and VCHGIN_UVLO = 5.0V
0x03 = VCHGIN_REG = 4.9V and VCHGIN_UVLO = 5.1V
5 R/W CHGINSEL 1
CHGIN/USB Input Channel Select
0 = Disabled
1 = Enabled
6 R/W WCINSEL 1
WCIN Input Channel Select
0 = Disabled
1 = Enabled
7 R/W Reserved 0 Reserved
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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PCB Layout Guide
GND
CAVL
0402
CVFG
0201
0201
GND
CWCIN
0603
CBYP
0603
CSL2
0402
CSL1
0402
CPVL
0603
CCHGIN
0603
CBYP
0603
CSYS
0603
CSYS
0603
CBATT
0603
2016
INDUCTOR
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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65
Typical Application Circuit
10uF
16V
(0603)
B8
C7
OVP IC
(OPTIONAL)
200K
200K
200K
200K
BATT
VIO
SYS
2.2uF
16V
(0603)
0.47uH
10uF
10V
(0603)
ID
PK+
10uF
10V
(0603)
MICRO-B USB
VBUS
GND
2.2uF
10V
(0402)
10uF
16V
(0603)
10uF
10V
(0603)
RINT
RB
10uF
10V
(0603)
0.1uF
16V
(0402)
0.1uF
6.3V
(0402)
1.8V to 5.5V
1uF
10V
(0402)
4.9V to AP USB PHY
1uF
10V
(0402)
0.1uF
16V
(0402)
10K, 1%
4.9V to CP USB PHY
4.7uF
10V
(0603)
WIRELESS
CHARGER
10K
PK-
VIO (FROM PMIC)
SYS AP
200K
D7
E8
E9
F7
F8
F9
G8
G9
E5
F5
G5
H5
H6
E1
F2
H7
H8
H9
G7
G3
G4
H3
H4
B6
F1
G1
H2
G6
F6
D5
D4
D3
D2
D1
E3
A6
B1
B4
B3
A2
B2
C2
C1
E7
D6
B7
B9
C5
A5
C3
A3
A4
B5
A8
A7
D9
D8
C9
C8 CHGIN
CHGIN
CHGIN
CHGIN
WCIN
WCIN
VIO
SCL
SDA
INTB
WCINOKB
INOKB
SAFEOUT1
SAFEOUT2
AVL
PVL
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
VCCTEST
GND_Q
GND_D
GND_A
GND_A
GND_A
GND_A
GND_A
BYP
BYP
BYP
BYP
BYP
BST
CHGLX
CHGLX
CHGLX
CHGLX
SYS
SYS
SYS
SYS
SYS
SYSA
SYSA
CHGPG
CHGPG
CHGPG
GSUBCG
BATT
BATT
BATT
BATT
DETBATB
VBFG
THMB
THM
BAT_SP
BAT_SN
MAX77818
+Denotes lead(Pb)-free/RoHS-compliant package.
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
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Ordering Information
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART TEMP RANGE PIN-PACKAGE
MAX77818EWZ+ -40°C to +85°C
72-pin WLP
0.4mm pitch,
3.867mm x 3.608mm
(±0.015mm X and Y)
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
72 WLP W723B3+1 21-0477
Refer to
Application
Note 1891
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX77818 Dual Input, Power Path,
3A Switching Mode Charger with FG
© 2015 Maxim Integrated Products, Inc.
│
67
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 6/15 Initial release —
1 10/15 Corrected Figure 5 and minor errors 19, 22, 27, 36
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
