Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 1 1Publication Order Number:
MC74HC4051A/D
MC74HC4051A,
MC74HC4052A,
MC74HC4053A
Analog Multiplexers /
Demultiplexers
High–Performance Silicon–Gate CMOS
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize
silicon–gate CMOS technology to achieve fast propagation delays,
low ON resistances, and low OFF leakage currents. These analog
multiplexers/demultiplexers control analog voltages that may vary
across the complete power supply range (from VCC to VEE).
The HC4051A, HC4052A and HC4053A are identical in pinout to
the metal–gate MC14051AB, MC14052AB and MC14053AB. The
Channel–Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to the
Common Output/Input. When the Enable pin is HIGH, all analog
switches are turned off.
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal–gate CMOS analog
switches.
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HC4852A.
•Fast Switching and Propagation Speeds
•Low Crosstalk Between Switches
•Diode Protection on All Inputs/Outputs
•Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V
•Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
•Improved Linearity and Lower ON Resistance Than Metal–Gate
Counterparts
•Low Noise
•In Compliance With the Requirements of JEDEC Standard No. 7A
•Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates
HC4052A — 168 FETs or 42 Equivalent Gates
HC4053A — 156 FETs or 39 Equivalent Gates
SO–16
D SUFFIX
CASE 751B
http://onsemi.com
TSSOP–16
DT SUFFIX
CASE 948F
1
16
1
16
PDIP–16
N SUFFIX
CASE 648
SO–16 WIDE
DW SUFFIX
CASE 751G
1
16
1
16
MARKING
DIAGRAMS
1
16
HC405xAN
AWLYYWW
1
16
HC405xAD
AWLYYWW
A = Assembly Location
WL = W afer Lot
YY = Year
WW = Work Week
HC40
5xA
ALYW
1
16
1
16
HC405xA
AWLYWW
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
ORDERING INFORMATION
SOEIAJ–16
F SUFFIX
CASE 966
1
16
74HC405xA
ALYW
1
16
MC74HC4051A, MC74HC4052A, MC74HC4053A
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2
LOGIC DIAGRAM
MC74HC4051A
Single–Pole, 8–Position Plus Common Off
X0 13
X1 14
X2 15
X3 12
X4 1
X5 5
X6 2
X7 4
A11
B10
C9
ENABLE 6
MULTIPLEXER/
DEMULTIPLEXER
X
3
ANALOG
INPUTS/
CHANNEL
INPUTS
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUT/
INPUT
1516 14 13 12 11 10
21 34567
VCC 9
8
X2 X1 X0 X3 A B C
X4 X6 X X7 X5 Enable V
EE
GND
Pinout: MC74HC4051A (Top View)
OUTPUTS
SELECT
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
FUNCTION TABLE – MC74HC4051A
Control Inputs
ON Channels
Enable Select
CBA
X0
X1
X2
X3
X4
X5
X6
X7
NONE
L
L
L
L
L
L
L
L
HX = Don’t Care
LOGIC DIAGRAM
MC74HC4052A
Double–Pole, 4–Position Plus Common Off
X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
A10
B9
ENABLE 6
X SWITCH
Y SWITCH
X
13
ANALOG
INPUTS/OUTPUTS
CHANNEL-SELECT
INPUTS PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
L
L
H
H
X
L
H
L
H
X
FUNCTION TABLE – MC74HC4052A
Control Inputs
ON Channels
Enable Select
BA
X0
X1
X2
X3
L
L
L
L
H
X = Don’t Care
Pinout: MC74HC4052A (Top View)
1516 14 13 12 11 10
21 34567
VCC 9
8
X2 X1 X X0 X3 A B
Y0 Y2 Y Y3 Y1 Enable VEE GND
Y
3
Y0
Y1
Y2
Y3 NONE
MC74HC4051A, MC74HC4052A, MC74HC4053A
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3
LOGIC DIAGRAM
MC74HC4053A
Triple Single–Pole, Double–Position Plus Common Off
X0 12
X1 13
A11
B10
C9
ENABLE 6
X SWITCH
Y SWITCH
X
14
ANALOG
INPUTS/OUTPUTS
CHANNEL-SELECT
INPUTS PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
FUNCTION TABLE – MC74HC4053A
Control Inputs
ON Channels
Enable Select
CBA
L
L
L
L
L
L
L
L
H
X = Don’t Care
Pinout: MC74HC4053A (Top View)
1516 14 13 12 11 10
21 34567
VCC 9
8
Y X X1 X0 A B C
Y1 Y0 Z1 Z Z0 Enable VEE GND
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
X0
X1
X0
X1
NONE
Y0 2
Y1 1Y
15
Z0 5
Z1 3Z
4
Z SWITCH
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎ
ÎÎÎÎÎ
Value
ÎÎÎ
ÎÎÎ
Unit
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)
ÎÎÎÎÎ
Î
ÎÎÎ
Î
ÎÎÎÎÎ
– 0.5 to + 7.0
– 0.5 to + 14.0
ÎÎÎ
Î
Î
Î
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Negative DC Supply Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
– 7.0 to + 5.0
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
VIS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Analog Input Voltage
ÎÎÎÎÎ
Î
ÎÎÎ
Î
ÎÎÎÎÎ
VEE – 0.5 to
VCC + 0.5
ÎÎÎ
Î
Î
Î
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
Vin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Digital Input Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
– 0.5 to VCC + 0.5
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
I
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Current, Into or Out of Any Pin
ÎÎÎÎÎ
ÎÎÎÎÎ
±25
ÎÎÎ
ÎÎÎ
mA
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
PD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Power Dissipation in Still Air, Plastic DIP†
EIAJ/SOIC Package†
TSSOP Package†
ÎÎÎÎÎ
Î
ÎÎÎ
Î
ÎÎÎÎÎ
750
500
450
ÎÎÎ
Î
Î
Î
ÎÎÎ
mW
ÎÎÎÎ
ÎÎÎÎ
Tstg
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Storage Temperature Range
ÎÎÎÎÎ
ÎÎÎÎÎ
– 65 to + 150
ÎÎÎ
ÎÎÎ
_
C
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
TL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
ÎÎÎÎÎ
Î
ÎÎÎ
Î
ÎÎÎÎÎ
260
ÎÎÎ
Î
Î
Î
ÎÎÎ
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/
_
C from 65
_
to 125
_
C
EIAJ/SOIC Package: – 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: – 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or V out)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC4051A, MC74HC4052A, MC74HC4053A
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4
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parameter
Min
Max
ÎÎÎ
ÎÎÎ
Unit
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)
Î
2.0
2.0
6.0
12.0
ÎÎÎ
Î
Î
Î
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Negative DC Supply Voltage, Output (Referenced to
GND)
– 6.0
GND
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Analog Input Voltage
VEE
VCC
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
Vin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Digital Input Voltage (Referenced to GND)
GND
VCC
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
VIO*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Static or Dynamic Voltage Across Switch
1.2
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
TA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature Range, All Package Types
– 55
+ 125
ÎÎÎ
ÎÎÎ
_
C
ÎÎÎÎ
Î
ÎÎ
Î
Î
ÎÎ
Î
ÎÎÎÎ
tr, tf
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Rise/Fall T ime VCC = 2.0 V
(Channel Select or Enable Inputs) VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Î
Î
0
0
0
0
1000
600
500
400
ÎÎÎ
Î
Î
Î
Î
Î
Î
ÎÎÎ
ns
*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
V
CC
Guaranteed Limit
Symbol Parameter Condition
VCC
V–55 to 25°C≤85°C≤125°CUnit
VIH Minimum High–Level Input
V oltage, Channel–Select or
Enable Inputs
Ron = Per Spec 2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL Maximum Low–Level Input
V oltage, Channel–Select or
Enable Inputs
Ron = Per Spec 2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
Iin Maximum Input Leakage Current,
Channel–Select or Enable Inputs Vin = VCC or GND,
VEE = – 6.0 V 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent Supply
Current (per Package) Channel Select, Enable and
VIS = VCC or GND; VEE = GND
VIO = 0 V VEE = – 6.0 6.0
6.0 1
410
40 20
80
µA
NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
MC74HC4051A, MC74HC4052A, MC74HC4053A
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5
DC CHARACTERISTICS — Analog Section
Guaranteed Limit
Symbol Parameter Condition VCC VEE –55 to 25°C≤85°C≤125°CUnit
Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to
VEE; IS ≤ 2.0 mA
(Figures 1, 2)
4.5
4.5
6.0
0.0
– 4.5
– 6.0
190
120
100
240
150
125
280
170
140
Ω
Vin = VIL or VIH; VIS = VCC or
VEE (Endpoints); IS ≤ 2.0 mA
(Figures 1, 2)
4.5
4.5
6.0
0.0
– 4.5
– 6.0
150
100
80
190
125
100
230
140
115
∆Ron Maximum Dif ference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = VIL or VIH;
VIS = 1/2 (VCC – VEE);
IS ≤ 2.0 mA
4.5
4.5
6.0
0.0
– 4.5
– 6.0
30
12
10
35
15
12
40
18
14
Ω
Ioff Maximum Of f–Channel Leakage
Current, Any One Channel Vin = VIL or VIH;
VIO = VCC – VEE;
Switch Off (Figure 3) 6.0 – 6.0 0.1 0.5 1.0 µA
Maximum Off–ChannelHC4051A
Leakage Current, HC4052A
Common Channel HC4053A
Vin = VIL or VIH;
VIO = VCC – VEE;
Switch Off (Figure 4)
6.0
6.0
6.0
– 6.0
– 6.0
– 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
Ion Maximum On–ChannelHC4051A
Leakage Current, HC4052A
Channel–to–Channel HC4053A
Vin = VIL or VIH;
Switch–to–Switch =
VCC – VEE; (Figure 5)
6.0
6.0
6.0
– 6.0
– 6.0
– 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
µA
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
V
CC
Guaranteed Limit
Symbol Parameter
VCC
V–55 to 25°C≤85°C≤125°CUnit
tPLH,
tPHL Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9) 2.0
3.0
4.5
6.0
270
90
59
45
320
110
79
65
350
125
85
75
ns
tPLH,
tPHL Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10) 2.0
3.0
4.5
6.0
40
25
12
10
60
30
15
13
70
32
18
15
ns
tPLZ,
tPHZ Maximum Propagation Delay, Enable to Analog Output
(Figure 11) 2.0
3.0
4.5
6.0
160
70
48
39
200
95
63
55
220
110
76
63
ns
tPZL,
tPZH Maximum Propagation Delay, Enable to Analog Output
(Figure 11) 2.0
3.0
4.5
6.0
245
115
49
39
315
145
69
58
345
155
83
67
ns
Cin Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF
CI/O Maximum Capacitance Analog I/O 35 35 35 pF
(All Switches Off) Common O/I: HC4051A
HC4052A
HC4053A
130
80
50
130
80
50
130
80
50
Feedthrough 1.0 1.0 1.0
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D)
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Figure 13)* HC4051A
HC4052A
HC4053A
45
80
45
pF
*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
MC74HC4051A, MC74HC4052A, MC74HC4053A
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6
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
V
CC
V
EE
Limit*
Symbol Parameter Condition
VCC
V
VEE
V25°CUnit
BW Maximum On–Channel Bandwidth
Mi i F R
fin = 1MHz Sine W ave; Adjust fin Voltage to
Obt i 0dB t V I f
‘51 ‘52 ‘53 MHz
or
Mi
n
i
mum
F
requency
R
esponse
(Figure 6)
Ob
ta
i
n
0dB
m at
V
OS;
I
ncrease
f
in
Frequency Until dB Meter Reads –3dB;
RL = 50Ω, CL = 10pF
2.25
4.50
6.00
–2.25
–4.50
–6.00
80
80
80
95
95
95
120
120
120
—Off–Channel Feedthrough Isolation
(Figure 7) fin = Sine W ave; Adjust f in Voltage to
Obtain 0dBm at VIS
fin = 10kHz, RL = 600Ω, CL = 50pF
2.25
4.50
6.00
–2.25
–4.50
–6.00
–50
–50
–50
dB
fin = 1.0MHz, RL = 50Ω, CL = 10pF
2.25
4.50
6.00
–2.25
–4.50
–6.00
–40
–40
–40
—Feedthrough Noise.
Channel–Select Input to Common
I/O (Figure 8)
Vin ≤ 1MHz Square Wave (tr = tf = 6ns);
Adjust RL at Setup so that IS = 0A;
Enable = GND RL = 600Ω, CL = 50pF
2.25
4.50
6.00
–2.25
–4.50
–6.00
25
105
135
mVPP
RL = 10kΩ, CL = 10pF
2.25
4.50
6.00
–2.25
–4.50
–6.00
35
145
190
—Crosstalk Between Any Two
Switches (Figure 12)
(Test does not apply to HC4051A)
fin = Sine W ave; Adjust f in Voltage to
Obtain 0dBm at VIS
fin = 10kHz, RL = 600Ω, CL = 50pF
2.25
4.50
6.00
–2.25
–4.50
–6.00
–50
–50
–50
dB
fin = 1.0MHz, RL = 50Ω, CL = 10pF
2.25
4.50
6.00
–2.25
–4.50
–6.00
–60
–60
–60
THD Total Harmonic Distortion
(Figure 14) fin = 1kHz, RL = 10kΩ, CL = 50pF
THD = THDmeasured – THDsource
VIS = 4.0VPP sine wave
VIS = 8.0VPP sine wave
VIS = 11.0VPP sine wave
2.25
4.50
6.00
–2.25
–4.50
–6.00
0.10
0.08
0.05
%
*Limits not tested. Determined by design and verified by qualification.
Figure 1a. Typical On Resistance, VCC – VEE = 2.0 V Figure 1b. Typical On Resistance, VCC – VEE = 3.0 V
250
200
150
100
50
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
R
on
,
ON
RESISTANCE
(
OHMS
)
100
80
60
40
20
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.25
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron, ON RESISTANCE (OHMS)
25°C
–55°C
125°C
25°C
–55°C
125°C
2.0
0
300
1
8
0
160
140
120
02.5 2.75 3.0
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Figure 1c. Typical On Resistance, VCC – VEE = 4.5 V Figure 1d. Typical On Resistance, VCC – VEE = 6.0 V
120
100
80
60
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
R
on
,
ON
RESISTANCE
(
OHMS
)
75
60
45
30
15
0 1.0 2.0 3.0 4.0 5.0 6.03.5 4.5 5.5
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron, ON RESISTANCE (OHMS)
20
0
25°C
–55°C
125°C
25°C
–55°C
125°C
90
105
00.5 1.5 2.5
Figure 1e. Typical On Resistance, VCC – VEE = 9.0 V
–4.5 –3.5
70
60
50
40
30
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron, ON RESISTANCE (OHMS)
20
10
–2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5
25°C
–55°C
125°C
8
0
0
Figure 1f. Typical On Resistance, VCC – VEE = 12.0 V
–6.0 –5.0
60
50
40
30
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron, ON RESISTANCE (OHMS)
20
10
–4.0 –3.0 –2.0 2.0 3.0 4.0 5.0 6.0
25°C
–55°C
125°C
0–1.0 1.00
Figure 2. On Resistance Test Set–Up
PLOTTER
MINI COMPUTER
PROGRAMMABLE
POWER
SUPPLY DC ANAL YZER
VCC
DEVICE
UNDER TEST
+–
VEE
ANALOG IN COMMON OUT
GND
MC74HC4051A, MC74HC4052A, MC74HC4053A
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8
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set–Up
Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set–Up Figure 6. Maximum On Channel Bandwidth,
Test Set–Up
Figure 7. Off Channel Feedthrough Isolation,
Test Set–Up Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set–Up
OFF
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIH
NC
A
VCC
VEE
VCC
OFF
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIH
ANALOG I/O
VCC
VEE
VCC
ON
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIL
VCC
VEE
VCC
N/C
A
ANALOG I/O
ON
6
7
8
16
VCC
VEE
0.1µF
CL*
fin RL
dB
METER
*Includes all probe and jig capacitance
OFF
6
7
8
16
VCC
VEE
0.1µF
CL*
fin RL
dB
METER
*Includes all probe and jig capacitance
VOS
VOS
RL
VIS
VIL or VIH CHANNEL SELECT
ON/OFF
6
7
8
16
VCC
VEE
CL*
RL
*Includes all probe and jig capacitance
CHANNEL SELECT
TEST
POINT
COMMON O/I
11 VCC
OFF/ON
ANALOG I/O
RL
RL
VCC
GND
Vin ≤1 MHz
tr = tf = 6 ns
MC74HC4051A, MC74HC4052A, MC74HC4053A
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9
Figure 9a. Propagation Delays, Channel Select
to Analog Out Figure 9b. Propagation Delay, Test Set–Up Channel
Select to Analog Out
Figure 10a. Propagation Delays, Analog In
to Analog Out Figure 10b. Propagation Delay, Test Set–Up
Analog In to Analog Out
Figure 11a. Propagation Delays, Enable to
Analog Out Figure 11b. Propagation Delay, Test Set–Up
Enable to Analog Out
VCC
GND
CHANNEL
SELECT
ANALOG
OUT 50%
tPLH tPHL
50% ON/OFF
6
7
8
16
VCC
CL*
*Includes all probe and jig capacitance
CHANNEL SELECT
TEST
POINT
COMMON O/I
OFF/ON
ANALOG I/O
VCC
VCC
GND
ANALOG
IN
ANALOG
OUT 50%
tPLH tPHL
50% ON
6
7
8
16
VCC
CL*
*Includes all probe and jig capacitance
TEST
POINT
COMMON O/I
ANALOG I/O
ON/OFF
6
7
8
ENABLE
VCC
ENABLE 90%
50%
10%
tftrVCC
GND
ANALOG
OUT
tPZL
ANALOG
OUT
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
ANALOG I/O
CL*
TEST
POINT
16
VCC 1kΩ
1
2
1
2
POSITION 1 WHEN TESTING tPHZ AND tPZH
POSITION 2 WHEN TESTING tPLZ AND tPZL
MC74HC4051A, MC74HC4052A, MC74HC4053A
http://onsemi.com
10
RL
Figure 12. Crosstalk Between Any Two
Switches, Test Set–Up Figure 13. Power Dissipation Capacitance,
Test Set–Up
Figure 14a. Total Harmonic Distortion, Test Set–Up Figure 14b. Plot, Harmonic Distortion
0
–10
–20
–30
–40
–50
–100 1.0 2.0 3.125
FREQUENCY (kHz)
dB
–60
–70
–80
–90
FUNDAMENTAL FREQUENCY
DEVICE
SOURCE
ON
6
7
8
16
VEE CL*
*Includes all probe and jig capacitance
OFF
RL
RL
VIS
RLCL*
VOS
fin 0.1µF
ON/OFF
6
7
8
16
VCC
CHANNEL SELECT
NC
COMMON O/I
OFF/ON
ANALOG I/O
VCC A
11
VCC
VEE
ON
6
7
8
16
VCC
VEE
0.1µF
CL*
fin RL
TO
DISTORTION
METER
*Includes all probe and jig capacitance
VOS
VIS
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
VCC or GND logic levels. VCC being recognized as a logic
high and GND being recognized as a logic low. In this
example: VCC = +5V = logic high
GND = 0V = logic low
The maximum analog voltage swings are determined by
the supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In this example,
the difference between VCC and VEE is ten volts. Therefore,
using the configuration of Figure 15, a maximum analog
signal of ten volts peak–to–peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that: VCC – GND = 2 to 6 volts
VEE – GND = 0 to –6 volts
VCC – VEE = 2 to 12 volts
and VEE ≤ GND
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in Figure
16. These diodes should be able to absorb the maximum
anticipated current sur ges during clipping.
MC74HC4051A, MC74HC4052A, MC74HC4053A
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11
ANALOG
SIGNAL
Figure 15. Application Example Figure 16. External Germanium or
Schottky Clipping Diodes
a. Using Pull–Up Resistors b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
ON
6
7
8
16
+5V
–5V
ANALOG
SIGNAL
+5V
–5V
+5V
–5V
11
10
9
TO EXTERNAL CMOS
CIRCUITR Y 0 to 5V
DIGITAL SIGNALS
ON/OFF
7
8
16
VCC
VEE
VEE
Dx
VCC
Dx
VEE
Dx
VCC
Dx
ANALOG
SIGNAL
ON/OFF
6
7
8
16
+5V
VEE
ANALOG
SIGNAL
+5V
VEE
+5V
VEE
11
10
9
R
*R R
LSTTL/NMOS
CIRCUITRY
+5V
* 2K ≤ R ≤ 10K
ANALOG
SIGNAL
ON/OFF
6
7
8
16
+5V
VEE
ANALOG
SIGNAL
+5V
VEE
+5V
VEE
11
10
9LSTTL/NMOS
CIRCUITRY
+5V
HCT
BUFFER
Figure 18. Function Diagram, HC4051A
13 X0
14 X1
15 X2
12 X3
1X4
5X5
2X6
4X7
3X
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
11
A
10
B
9
C
6
ENABLE
MC74HC4051A, MC74HC4052A, MC74HC4053A
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12
Figure 20. Function Diagram, HC4053A
Figure 19. Function Diagram, HC4052A
13 X1
12 X0
1Y1
2Y0
3Z1
5Z0
14 X
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
11
A
10
B
9
C
6
ENABLE
12 X0
14 X1
15 X2
11 X3
1Y0
5Y1
2Y2
4Y3
3Y
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
10
A
9
B
6
ENABLE
13 X
15 Y
4Z
MC74HC4051A, MC74HC4052A, MC74HC4053A
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13
ORDERING & SHIPPING INFORMATION
Device Package Shipping
MC74HC4051AN PDIP–16 500 Units / Unit Pak
MC74HC4051AD SOIC–16 48 Units / Rail
MC74HC4051ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4051ADT TSSOP–16 96 Units / Rail
MC74HC4051ADTR2 TSSOP–16 2500 Units / Tape & Reel
MC74HC4051ADW SOIC WIDE 48 Units / Rail
MC74HC4051ADWR2 SOIC WIDE 1000 Units / Tape & Reel
MC74HC4051AF SOEIAJ–16 See Note 1.
MC74HC4051AFEL SOEIAJ–16 See Note 1.
MC74HC4052AN PDIP–16 500 Units / Unit Pak
MC74HC4052AD SOIC–16 48 Units / Rail
MC74HC4052ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4052ADT TSSOP–16 96 Units / Rail
MC74HC4052ADTR2 TSSOP–16 2500 Units / Tape & Reel
MC74HC4052ADW SOIC WIDE 48 Units / Rail
MC74HC4052ADWR2 SOIC WIDE 1000 Units / Tape & Reel
MC74HC4052AF SOEIAJ–16 See Note 1.
MC74HC4052AFEL SOEIAJ–16 See Note 1.
MC74HC4053AN PDIP–16 500 Units / Unit Pak
MC74HC4053AD SOIC–16 48 Units / Rail
MC74HC4053ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4053ADT TSSOP–16 96 Units / Rail
MC74HC4053ADTR2 TSSOP–16 2500 Units / Tape & Reel
MC74HC4053ADW SOIC WIDE 48 Units / Rail
MC74HC4053ADWR2 SOIC WIDE 1000 Units / Tape & Reel
MC74HC4053AF SOEIAJ–16 See Note 1.
MC74HC4053AFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
MC74HC4051A, MC74HC4052A, MC74HC4053A
http://onsemi.com
14
PACKAGE DIMENSIONS
PDIP–16
N SUFFIX
CASE 648–08
ISSUE R
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
M
S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50
0°
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74
10°
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295
0°
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305
10°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
–A
–
B
18
916
F
HGD 16 PL
S
C
–T
–SEATING
PLANE
KJM
L
TA0.25 (0.010) M M
0.25 (0.010) T B A
MS S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
916
–A
–
–B
–
D16 PL
K
C
G
–T
–
SEATING
PLANE
R X 45°
MJ
F
P 8 PL 0.25 (0.010) B
M M
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
MC74HC4051A, MC74HC4052A, MC74HC4053A
http://onsemi.com
15
PACKAGE DIMENSIONS
SOIC–16 WIDE
DW SUFFIX
CASE 751G–03
ISSUE B
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45
_
M
B
M
0.25
H8X
E
B
A
eT
A1
A
L
C
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q
0 7
__
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
ÇÇÇ
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C––– 1.20 ––– 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION A T MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
____
SECTION N–N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
–U–
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
–T–
–V–
–W–
0.25 (0.010)
16X REFK
N
N
MC74HC4051A, MC74HC4052A, MC74HC4053A
http://onsemi.com
16
PACKAGE DIMENSIONS
HE
A1
DIM MIN MAX MIN MAX
INCHES
––– 2.05 ––– 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
––– 0.78 ––– 0.031
A1
HE
Q1
LE
_
10
_
0
_
10
_
LEQ1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION A T MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
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attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Af firmative Action Employer.
PUBLICATION ORDERING INFORMATION
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Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: ONlit–spanish@hibbertco.com
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Phone: 303–675–2121 (T ue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
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Email: ONlit–asia@hibbertco.com
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4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549
Phone: 81–3–5740–2745
Email: r14525@onsemi.com
ON Semiconductor Website : http://onsemi.com
For additional information, please contact your local
Sales Representative.
MC74HC4051A/D
NORTH AMERICA Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver , Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
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German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich T ime)
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Email: ONlit–french@hibbertco.com
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Email: ONlit@hibbertco.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
*Available from Germany, France, Italy, England, Ireland