2010 Microchip Technology Inc. DS80496C-page 1
PIC18F2480/2580/4480/4580
The PIC18F2480/2580/4480/4580 devices that you
have received conform functionally to the current Device
Data Sheet (DS39637D), except for the anomalies
described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will be
addressed in future revisions of the PIC18F2480/2580/
4480/4580 silicon.
Data Sheet clarifications and corrections start on
page 11, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1. Using the appropriate interface, connect the
device to the MPLAB ICD 2 programmer/
debugger or PICkit™ 3.
2. From the main menu in MPLAB IDE, select Con-
figure>Select Device, and then select the target
part number in the dialog box.
3. Select the MPLAB hardware tool
(Debugger>Select Tool).
4. Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number and Device
Revision ID value appear in the Output window.
The DEVREV values for the various PIC18F2480/2580/
4480/4580 silicon revisions are shown in Table 1.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon revision
(B2).
Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES
Part Number Device ID(1) Revision ID for Silicon Revision(2)
A1 B0 B2
PIC18F2480 1AEh
1h 2h 4h
PIC18F2580 1ACh
PIC18F4480 1AAh
PIC18F4580 1A8h
Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
2: Refer to the “PIC18F2XXX/4XXXX Family Flash Microcontroller Programming Specification” (DS39622)
for detailed information on Device and Revision IDs for your specific device.
PIC18F2480/2580/4480/4580
Silicon Errata and Data Sheet Clarification
PIC18F2480/2580/4480/4580
DS80496C-page 2 2010 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item
Number Issue Summary
Affected Revisions(1)
A1 B0 B2
MSSP I2C™ 1. Slave reception receives incorrect data if not
read at the correct time. XXX
BOR Trip Level 2. Trip levels are off at high frequencies. X
ECCP Special Event
Trigger 3. The Special Event Trigger Reset does not occur
on the next rollover of the prescaler counter. X
EUSART Transmission 4. Nine-bit timing can be corrupted if the TX9D bit
is not written immediately after TXIF is set. X
Timer1/3 16-Bit Mode 5.
The TMR1H/TMR3H Buffer registers may
lengthen the duration of the period between the
increments of the timer.
X
Interrupts Two-Cycle
Instruction 6.
If an interrupt occurs during a two-cycle
instruction modifying the STATUS, BSR or
WREG register, the previous value is saved to
the Fast Return register.
X
ECAN™
Technology
Transmit
Buffer ID 7. The first five bits of a transmitted identifier may
not match the transmit buffer ID. X
ECAN
Technology
Error
Interruption
Flag
8.
The error interrupt flag may not be able to be
cleared in software if the TXERRCNT or
RXERRCNT counters exceed 127.
X
ECAN
Technology
Configuration
Mode 9.
After an error on the bus, the module is unable
to switch directly from Listen Only mode to
Configuration mode.
X
ECAN
Technology
TXBnSIDH
Register 10. May become corrupted. X
ECAN
Technology
Listen Only
Mode 11.
IRXIF, RXB0IF and RXFUL flags are
consistently set after 129 or more consistent
error frames.
X
10-Bit ADC EIL and EDL 12. EIL and EDL may exceed data sheet
specifications at codes, 511 and 512. X
MSSP SPI 13. SDO output may change after inactive lock
edge of Bit 0. X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
2010 Microchip Technology Inc. DS80496C-page 3
PIC18F2480/2580/4480/4580
Silicon Errata Issues
1. Module: Master Synchronous Serial Port
(MSSP)
When configured for I2C slave reception, the
MSSP module may not receive the correct data,
in extremely rare cases. This occurs only if the
Serial Receive/Transmit Buffer register
(SSPBUF) is not read within a window after the
SSPIF interrupt (PIR1<3>) has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I2C slave reception, enable the
clock stretching feature.
This is done by setting the SEN bit
(SSPCON2<0>).
• Each time the SSPIF is set, read the SSPBUF
before the first rising clock edge of the next
byte being received.
Affected Silicon Revisions
2. Module: Brown-out Reset (BOR)
The BOR module may reset above the
parameter D005 value specified in Section 28.1
“DC Characteristics: Supply Voltage” when:
•BORV<1:0> = 01 or 00
•FOSC is above 26 MHz
The updated BOR voltage specifications are
shown in the Section 28.1 table.
Work around
To address this situation:
• Reduce FOSC to 25 MHz
• Use the lower of the two affected BOR
voltage thresholds, BORV<1:0>
(CONFIG2L<4:3>) = 01
This will ensure detection of VDD below 5.0V.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B2).
A1 B0 B2
XXX
28.1 DC Characteristics: Supply Voltage
PIC18F2480/2580/4480/4580 (Industrial, Extended)
PIC18LF2480/2580/4480/4580 (Industrial)
Param
No. Symbol Characteristic Min Typ Max Units Conditions
D005 VBOR Brown-out Reset Voltage
BORV<1:0> = 01 4.47 4.69 4.91 V FOSC > 26 MHz
BORV<1:0> = 00 4.72 4.95 5.18 V FOSC > 26 MHz
A1 B0 B2
X
PIC18F2480/2580/4480/4580
DS80496C-page 4 2010 Microchip Technology Inc.
3. Module: ECCP
When operating either Timer1 or Timer3 as a
counter, with a prescale value other than 1:1 and
operating the ECCP in Compare mode with the
Special Event Trigger (CCP1CON bits,
CCP1M<3:0> = 1011), the Special Event
Trigger Reset of the timer occurs as soon as
there is a match between TMRxH:TMRxL and
CCPR1H:CCPR1L.
This differs from the PIC18F458, where the
Special Event Trigger Reset of the timer occurs
on the next rollover of the prescale counter, after
the match between TMRxH:TMRxL and
CCPR1H:CCPR1L.
Work around
To achieve the same timer Reset period as the
PIC18F458 devices, for a given clock source,
add 1 to the value in CCPR1H:CCPR1L. If
CCPR1H:CCPR1L = x for the PIC18F458,
achieve the same Reset period on a
PIC18F2480/2580/4480/4580 device by using
CCPR1H:CCPR1L = x + 1, where the prescale is
1, 2, 4 or 8 (depending on the T1CKPS<1:0> bit
values).
Affected Silicon Revisions
4. Module: EUSART
When performing back-to-back transmission in
9-bit mode (TX9D bit in the TXSTA register is
set), an ongoing transmission’s timing can be
corrupted if the TX9D bit (for the next transmis-
sion) is not written immediately following the
setting of TXIF. This is because any write to the
TXSTA register results in a Reset of the Baud
Rate Generator which will effect any ongoing
transmission.
Work around
Load TX9D just after TXIF is set, either by poll-
ing TXIF or by writing TX9D at the beginning of
the Interrupt Service Routine. Alternately, only
write to TX9D when a transmission is not in
progress (TRMT = 1).
Affected Silicon Revisions
5. Module: Timer1/3
When Timer1/Timer3 is operating in 16-bit mode
and the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen
the duration of the period between the incre-
ments of the timer for the period in which
TMR1H/TMR3H were written. It does not
change the actual prescale value.
Work around
Do not write to TMR1H/TMR3H while Timer1/
Timer3 is running, or else write to TMR1L/
TMR3L immediately following a write to
TMR1H/TMR3H.
Do not write to TMR1H/TMR3H and then wait
for another event before also updating
TMR1L/TMR3L.
Affected Silicon Revisions
A1 B0 B2
X
A1 B0 B2
X
A1 B0 B2
X
2010 Microchip Technology Inc. DS80496C-page 5
PIC18F2480/2580/4480/4580
6. Module: Interrupts
If an interrupt occurs during a two-cycle instruc-
tion that modifies the STATUS, BSR or WREG
register, the unmodified value of the register will
be saved to the corresponding Fast Return
(Shadow) register. Upon a fast return from the
interrupt, the unmodified value will be restored
to the STATUS, BSR or WREG register.
For example, if a high-priority interrupt occurs
during the instruction, MOVFF TEMP, WREG, the
MOVFF instruction will be completed and WREG
will be loaded with the value of TEMP before
branching to the ISR. However, the previous
value of WREG will be saved to the Fast Return
register during ISR branching. Upon return from
the interrupt with a fast return, the previous
value of WREG in the Fast Return register will
be written to WREG.
This results in WREG containing the value it had
before execution of MOVFF TEMP, WREG.
Affected instructions are:
Work around
1. Assembly Language Programming:
If any two-cycle instruction is used to modify
the WREG, BSR or STATUS register, do not
use the RETFIE FAST instruction to return
from the interrupt. Instead, save and then
restore WREG, BSR and STATUS via soft-
ware, as shown in Example 8-1 in the Device
Data Sheet.
Alternatively, in the case of MOVFF, use the
MOVF instruction to write to WREG instead. For
example:
As another alternative, the work around in
Example 1 can be used. This example over-
writes the Fast Return register by making a
dummy call to Foo with the fast option in the
high-priority service routine.
EXAMPLE 1: ASSEMBLY LANGUAGE INTERRUPT SERVICE
MOVFF Fs, Fd
Where Fd is WREG, BSR or STATUS
MOVSF Zs, Fd
Where Fd is WREG, BSR or STATUS
MOVSS [Zs], [Zd]
Where the destination is WREG, BSR or STATUS
Use
MOVF TEMP, W
MOVWF BSR
Instead of
MOVFF TEMP, BSR
ISR @ 0x0008
CALL Foo, FAST ; store current value of WREG, BSR, STATUS for a second time
Foo:POP ; clears return address of Foo call
: ; insert high priority ISR code here
:
RETFIE FAST
PIC18F2480/2580/4480/4580
DS80496C-page 6 2010 Microchip Technology Inc.
2. C Language Programming:
The exact work around depends on the
compiler in use. Consult the C compiler’s
documentation for details.
If using the Microchip MPLAB® C18 C
Compiler, define both high and low-priority
interrupt handler functions as “low priority” by
using the pragma interruptlow directive.
This directive instructs the compiler to not use
the RETFIE FAST instruction. If the proper
high-priority interrupt bit is set in the IPRx
register, the interrupt is treated as high priority
in spite of the pragma interruptlow
directive.
The code segment, shown in Example 2,
demonstrates the work around using the C18
compiler.
EXAMPLE 2: INTERRUPT SERVICE ROUTINE IN C
#pragma interruptlow MyLowISR
void MyLowISR(void)
{// Handle low priority interrupts.
}
// Although MyHighISR is a high priority interrupt, use interruptlow pragma so that
// the compiler will not use retfie FAST.
#pragma interruptlow MyHighISR
void MyHighISR(void)
{// Handle high priority interrupts.
}
#pragma code highVector=0x08
void HighVector (void)
{_asm goto MyHighISR _endasm
}
#pragma code /* return to default code section */
#pragma code lowVector=0x18
void LowVector (void)
{_asm goto MyLowISR _endasm
}
#pragma code /* return to default code section */
2010 Microchip Technology Inc. DS80496C-page 7
PIC18F2480/2580/4480/4580
An optimized C18 version, illustrating how to
reduce the instruction cycle count to three, is
provided in Example 3.
Affected Silicon Revisions
EXAMPLE 3: OPTIMIZED INTERRUPT SERVICE ROUTINE
A1 B0 B2
X
#pragma code high_vector_section=0x8
void high_vector (void)
{
_asm
CALL high_vector_branch, 1
_endasm
}
void high_vector_branch (void)
{
_asm
POP
GOTO high_isr
_endasm
}
#pragma interrupt high_isr
void high_isr (void)
{
...
}
PIC18F2480/2580/4480/4580
DS80496C-page 8 2010 Microchip Technology Inc.
7. Module: ECAN™ Technology
Under specific conditions, the first five bits of a
transmitted identifier may not match the value in
the Transmit Buffer ID register, TXBnSIDH. The
following conditions must exist for the corruption
to occur:
• A transmit message must be pending
• The ECAN module must detect a
Start-of-Frame (SOF) in the third bit of the
interframe space.
Work around
None.
Affected Silicon Revisions
8. Module: ECAN Technology
The Error Interrupt Flag, ERRIF (PIR3<5>), may
not be able to be cleared in software after either
of the following counter registers exceeds 127:
• Transmit Error Counter Register (TXERRCNT)
• Receive Error Counter Register (RXERRCNT)
Work around
Monitor the EWARN (COMSTAT<0>) bit to
determine if either the TXERRCNT or the
RXERRCNT exceeds 95 and clear the ERRIF
flag before either counter reaches 127.
Affected Silicon Revisions
9. Module: ECAN Technology
Following an error on the bus, the ECAN module
is unable to switch from Listen Only mode
directly to Configuration mode.
Work around
Use the REQOP (CANCON<7:5>) bits to select
Normal mode as an intermediate step when
switching from Listen Only mode to Configuration
mode.
Affected Silicon Revisions
A1 B0 B2
X
A1 B0 B2
X
A1 B0 B2
X
2010 Microchip Technology Inc. DS80496C-page 9
PIC18F2480/2580/4480/4580
10. Module: ECAN Technology
Under specific conditions, the TXBnSIDH register
of the pending message for transmission may be
corrupted. This occurs when the following
conditions exist:
• A transmit message is pending.
• All of the receive buffers are full and a received
message is in the Message Assembly Buffer
(MAB).
• A receive buffer is made available (RXFUL
(RXBxCON<7>) set to ‘0’) at either of the
following times:
- When a Start-of-Frame (SOF) is recognized
on the CAN bus
- On the instruction cycle prior to the SOF
The timing of this event is crucial.
Work around
Ensure that a receive buffer overflow condition
does not occur and/or ensure that a transmit
request is not pending if a receive buffer
overflow condition does exist.
The pseudo code segment in Example 4 is an
example of how to disable a pending transmission.
This code is for illustration purposes only.
Affected Silicon Revisions
EXAMPLE 4: DISABLING A PENDING TRANSMISSION
A1 B0 B2
X
If (RXBnOVFL == 1) // Has an overflow occurred?
{ If (TXREQ == 1) // Is a transmission pending?
{ TXREQ = 0; // Clear transmit request
If (TXABT == 1) // Store transmission aborted status value
MyFlag = 1;
}
}
Temp_RXREG = RXBx; // Read receive buffer
If (MyFlag) // Was previous transmission aborted?
{ TXREQ = 1; // Set transmit request
MyFlag = 0; // Reset stored transmission aborted status
}
PIC18F2480/2580/4480/4580
DS80496C-page 10 2010 Microchip Technology Inc.
11. Module: ECAN Technology
In Listen Only mode, the module may
persistently set the IRXIF and RXB0IF interrupt
flags, and the RXFUL status flag, after receiving
129 or more consecutive error frames. In this
case, the flags can be cleared, but then will
become set again immediately and continuously
without receiving a bus message.
Work around
Place the ECAN module in Configuration mode
before receiving 129 consecutive error frames
and then place it back into Listen Only mode.
Affected Silicon Revisions
12. Module: 10-Bit Analog-to-Digital
Converter
When the AD clock source is selected as 2 TOSC
or RC (when ADCS<2:0> = 000 or x11), in
extremely rare cases, the EIL (Integral Linearity
Error) and EDL (Differential Linearity Error) may
exceed the data sheet specifications at codes,
511 and 512 only.
Work around
Select the AD clock source as 4 TOSC, 8 TOSC,
16 T
OSC, 32 TOSC or 64 TOSC and avoid selecting
2T
OSC or RC.
Affected Silicon Revisions
13. Module: MSSP
In SPI mode, the SDO output may change after
the inactive clock edge of the Bit 0 output. This
may affect some SPI components that read data
over 300 ns after the inactive edge of SCK.
Work around
None.
Affected Silicon Revisions
A1 B0 B2
X
A1 B0 B2
X
A1 B0 B2
X
2010 Microchip Technology Inc. DS80496C-page 11
PIC18F2480/2580/4480/4580
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS39637D):
None.
APPENDIX A: DOCUMENT
REVISION HISTORY
Rev A Document (2/2010)
Original release of this errata, combining previous
errata for silicon revisions, A1 and B0, and superseding
the data sheet errata. Added the B2 silicon revision,
which had no issues. No data sheet issues were
included as they had been resolved with a data sheet
revision.
This document replaces these errata documents:
• DS80419B, “PIC18F2480/2580/4480/4580
Rev. B0 Silicon Errata”
• DS80219E, “PIC18F2480/2580/4480/4580
Rev. A1 Silicon Errata”
• DS80267C, “PIC18F2480/2580/4480/4580 Data
Sheet Errata”
Rev B Document (3/2010)
Corrected an erroneous silicon revision reference in
the revision history.
Rev C Document (3/2010)
Removed issue #1 from the document and renumbered
the previous issues 2-14. Added B2 silicon as being
affected by issue 1 (formerly 2) and removed A1 silicon
from issue 2 (formerly 3).
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
PIC18F2480/2580/4480/4580
DS80496C-page 12 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS80496C-page 13
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-067-6
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS80496C-page 14 2010 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
01/05/10
