PIC18F2480/2580/4480/4580 PIC18F2480/2580/4480/4580 Silicon Errata and Data Sheet Clarification The PIC18F2480/2580/4480/4580 devices that you have received conform functionally to the current Device Data Sheet (DS39637D), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC18F2480/2580/ 4480/4580 silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (B2). Data Sheet clarifications and corrections start on page 11, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: Device ID(1) PIC18F2480 1AEh PIC18F2580 1ACh PIC18F4480 1AAh PIC18F4580 1A8h 2: 1. Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/ debugger or PICkitTM 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. 2. 3. 4. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC18F2480/2580/ 4480/4580 silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number Note 1: For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkitTM 3: Revision ID for Silicon Revision(2) A1 B0 B2 1h 2h 4h The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration memory space. They are shown in hexadecimal in the format "DEVID DEVREV". Refer to the "PIC18F2XXX/4XXXX Family Flash Microcontroller Programming Specification" (DS39622) for detailed information on Device and Revision IDs for your specific device. 2010 Microchip Technology Inc. DS80496C-page 1 PIC18F2480/2580/4480/4580 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Issue Summary Affected Revisions(1) A1 B0 B2 X X X MSSP I2CTM 1. Slave reception receives incorrect data if not read at the correct time. BOR Trip Level 2. Trip levels are off at high frequencies. ECCP Special Event Trigger 3. The Special Event Trigger Reset does not occur on the next rollover of the prescaler counter. X EUSART Transmission 4. Nine-bit timing can be corrupted if the TX9D bit is not written immediately after TXIF is set. X Timer1/3 16-Bit Mode 5. The TMR1H/TMR3H Buffer registers may lengthen the duration of the period between the increments of the timer. X Interrupts Two-Cycle Instruction 6. If an interrupt occurs during a two-cycle instruction modifying the STATUS, BSR or WREG register, the previous value is saved to the Fast Return register. X ECANTM Transmit Technology Buffer ID 7. The first five bits of a transmitted identifier may not match the transmit buffer ID. X Error ECAN Interruption Technology Flag 8. The error interrupt flag may not be able to be cleared in software if the TXERRCNT or RXERRCNT counters exceed 127. X ECAN Configuration Technology Mode 9. After an error on the bus, the module is unable to switch directly from Listen Only mode to Configuration mode. X ECAN TXBnSIDH Technology Register 10. May become corrupted. X ECAN Listen Only Technology Mode 11. IRXIF, RXB0IF and RXFUL flags are consistently set after 129 or more consistent error frames. X 10-Bit ADC EIL and EDL 12. EIL and EDL may exceed data sheet specifications at codes, 511 and 512. X MSSP 13. SDO output may change after inactive lock edge of Bit 0. X Note 1: SPI X Only those issues indicated in the last column apply to the current silicon revision. DS80496C-page 2 2010 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Silicon Errata Issues Note: Work around The issue can be resolved in either of these ways: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B2). * Prior to the I2C slave reception, enable the clock stretching feature. This is done by (SSPCON2<0>). setting the SEN bit * Each time the SSPIF is set, read the SSPBUF before the first rising clock edge of the next byte being received. 1. Module: Master Synchronous Serial Port (MSSP) Affected Silicon Revisions When configured for I2C slave reception, the MSSP module may not receive the correct data, in extremely rare cases. This occurs only if the Serial Receive/Transmit Buffer register (SSPBUF) is not read within a window after the SSPIF interrupt (PIR1<3>) has occurred. A1 B0 B2 X X X 2. Module: Brown-out Reset (BOR) The BOR module may reset above the parameter D005 value specified in Section 28.1 "DC Characteristics: Supply Voltage" when: * BORV<1:0> = 01 or 00 * FOSC is above 26 MHz The updated BOR voltage specifications are shown in the Section 28.1 table. 28.1 DC Characteristics: Param No. D005 Symbol VBOR Supply Voltage PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial) Characteristic Min Typ Max Units Conditions BORV<1:0> = 01 4.47 4.69 4.91 V FOSC > 26 MHz BORV<1:0> = 00 4.72 4.95 5.18 V FOSC > 26 MHz Brown-out Reset Voltage Work around To address this situation: * Reduce FOSC to 25 MHz * Use the lower of the two affected BOR voltage thresholds, BORV<1:0> (CONFIG2L<4:3>) = 01 This will ensure detection of VDD below 5.0V. Affected Silicon Revisions A1 B0 B2 X 2010 Microchip Technology Inc. DS80496C-page 3 PIC18F2480/2580/4480/4580 3. Module: ECCP When operating either Timer1 or Timer3 as a counter, with a prescale value other than 1:1 and operating the ECCP in Compare mode with the Special Event Trigger (CCP1CON bits, CCP1M<3:0> = 1011), the Special Event Trigger Reset of the timer occurs as soon as there is a match between TMRxH:TMRxL and CCPR1H:CCPR1L. This differs from the PIC18F458, where the Special Event Trigger Reset of the timer occurs on the next rollover of the prescale counter, after the match between TMRxH:TMRxL and CCPR1H:CCPR1L. Work around To achieve the same timer Reset period as the PIC18F458 devices, for a given clock source, add 1 to the value in CCPR1H:CCPR1L. If CCPR1H:CCPR1L = x for the PIC18F458, achieve the same Reset period on a PIC18F2480/2580/4480/4580 device by using CCPR1H:CCPR1L = x + 1, where the prescale is 1, 2, 4 or 8 (depending on the T1CKPS<1:0> bit values). 5. Module: Timer1/3 When Timer1/Timer3 is operating in 16-bit mode and the prescale setting is not 1:1, a write to the TMR1H/TMR3H Buffer registers may lengthen the duration of the period between the increments of the timer for the period in which TMR1H/TMR3H were written. It does not change the actual prescale value. Work around Do not write to TMR1H/TMR3H while Timer1/ Timer3 is running, or else write to TMR1L/ TMR3L immediately following a write to TMR1H/TMR3H. Do not write to TMR1H/TMR3H and then wait for another event before also updating TMR1L/TMR3L. Affected Silicon Revisions A1 B0 B2 X Affected Silicon Revisions A1 B0 B2 X 4. Module: EUSART When performing back-to-back transmission in 9-bit mode (TX9D bit in the TXSTA register is set), an ongoing transmission's timing can be corrupted if the TX9D bit (for the next transmission) is not written immediately following the setting of TXIF. This is because any write to the TXSTA register results in a Reset of the Baud Rate Generator which will effect any ongoing transmission. Work around Load TX9D just after TXIF is set, either by polling TXIF or by writing TX9D at the beginning of the Interrupt Service Routine. Alternately, only write to TX9D when a transmission is not in progress (TRMT = 1). Affected Silicon Revisions A1 B0 B2 X DS80496C-page 4 2010 Microchip Technology Inc. PIC18F2480/2580/4480/4580 6. Module: Interrupts Work around If an interrupt occurs during a two-cycle instruction that modifies the STATUS, BSR or WREG register, the unmodified value of the register will be saved to the corresponding Fast Return (Shadow) register. Upon a fast return from the interrupt, the unmodified value will be restored to the STATUS, BSR or WREG register. For example, if a high-priority interrupt occurs during the instruction, MOVFF TEMP, WREG, the MOVFF instruction will be completed and WREG will be loaded with the value of TEMP before branching to the ISR. However, the previous value of WREG will be saved to the Fast Return register during ISR branching. Upon return from the interrupt with a fast return, the previous value of WREG in the Fast Return register will be written to WREG. This results in WREG containing the value it had before execution of MOVFF TEMP, WREG. Affected instructions are: MOVFF Fs, Fd Where Fd is WREG, BSR or STATUS MOVSF 1. Assembly Language Programming: If any two-cycle instruction is used to modify the WREG, BSR or STATUS register, do not use the RETFIE FAST instruction to return from the interrupt. Instead, save and then restore WREG, BSR and STATUS via software, as shown in Example 8-1 in the Device Data Sheet. Alternatively, in the case of MOVFF, use the MOVF instruction to write to WREG instead. For example: Use MOVF MOVWF TEMP, W BSR Instead of MOVFF TEMP, BSR As another alternative, the work around in Example 1 can be used. This example overwrites the Fast Return register by making a dummy call to Foo with the fast option in the high-priority service routine. Zs, Fd Where Fd is WREG, BSR or STATUS MOVSS [Zs], [Zd] Where the destination is WREG, BSR or STATUS EXAMPLE 1: ISR @ 0x0008 CALL Foo: POP : : RETFIE ASSEMBLY LANGUAGE INTERRUPT SERVICE Foo, FAST ; store current value of WREG, BSR, STATUS for a second time ; clears return address of Foo call ; insert high priority ISR code here FAST 2010 Microchip Technology Inc. DS80496C-page 5 PIC18F2480/2580/4480/4580 2. C Language Programming: The exact work around depends on the compiler in use. Consult the C compiler's documentation for details. If using the Microchip MPLAB(R) C18 C Compiler, define both high and low-priority interrupt handler functions as "low priority" by using the pragma interruptlow directive. This directive instructs the compiler to not use EXAMPLE 2: the RETFIE FAST instruction. If the proper high-priority interrupt bit is set in the IPRx register, the interrupt is treated as high priority in spite of the pragma interruptlow directive. The code segment, shown in Example 2, demonstrates the work around using the C18 compiler. INTERRUPT SERVICE ROUTINE IN C #pragma interruptlow MyLowISR void MyLowISR(void) { // Handle low priority interrupts. } // Although MyHighISR is a high priority interrupt, use interruptlow pragma so that // the compiler will not use retfie FAST. #pragma interruptlow MyHighISR void MyHighISR(void) { // Handle high priority interrupts. } #pragma code highVector=0x08 void HighVector (void) { _asm goto MyHighISR _endasm } #pragma code /* return to default code section */ #pragma code lowVector=0x18 void LowVector (void) { _asm goto MyLowISR _endasm } #pragma code /* return to default code section */ DS80496C-page 6 2010 Microchip Technology Inc. PIC18F2480/2580/4480/4580 An optimized C18 version, illustrating how to reduce the instruction cycle count to three, is provided in Example 3. Affected Silicon Revisions A1 B0 B2 X EXAMPLE 3: OPTIMIZED INTERRUPT SERVICE ROUTINE #pragma code high_vector_section=0x8 void high_vector (void) { _asm CALL high_vector_branch, 1 _endasm } void high_vector_branch (void) { _asm POP GOTO high_isr _endasm } #pragma interrupt high_isr void high_isr (void) { ... } 2010 Microchip Technology Inc. DS80496C-page 7 PIC18F2480/2580/4480/4580 7. Module: ECANTM Technology Under specific conditions, the first five bits of a transmitted identifier may not match the value in the Transmit Buffer ID register, TXBnSIDH. The following conditions must exist for the corruption to occur: * A transmit message must be pending * The ECAN module must detect a Start-of-Frame (SOF) in the third bit of the interframe space. Work around Affected Silicon Revisions B0 Following an error on the bus, the ECAN module is unable to switch from Listen Only mode directly to Configuration mode. Work around Use the REQOP (CANCON<7:5>) bits to select Normal mode as an intermediate step when switching from Listen Only mode to Configuration mode. Affected Silicon Revisions A1 None. A1 9. Module: ECAN Technology B0 B2 X B2 X 8. Module: ECAN Technology The Error Interrupt Flag, ERRIF (PIR3<5>), may not be able to be cleared in software after either of the following counter registers exceeds 127: * Transmit Error Counter Register (TXERRCNT) * Receive Error Counter Register (RXERRCNT) Work around Monitor the EWARN (COMSTAT<0>) bit to determine if either the TXERRCNT or the RXERRCNT exceeds 95 and clear the ERRIF flag before either counter reaches 127. Affected Silicon Revisions A1 B0 B2 X DS80496C-page 8 2010 Microchip Technology Inc. PIC18F2480/2580/4480/4580 10. Module: ECAN Technology Work around Under specific conditions, the TXBnSIDH register of the pending message for transmission may be corrupted. This occurs when the following conditions exist: Ensure that a receive buffer overflow condition does not occur and/or ensure that a transmit request is not pending if a receive buffer overflow condition does exist. * A transmit message is pending. * All of the receive buffers are full and a received message is in the Message Assembly Buffer (MAB). * A receive buffer is made available (RXFUL (RXBxCON<7>) set to `0') at either of the following times: - When a Start-of-Frame (SOF) is recognized on the CAN bus - On the instruction cycle prior to the SOF The pseudo code segment in Example 4 is an example of how to disable a pending transmission. This code is for illustration purposes only. Affected Silicon Revisions A1 B0 B2 X The timing of this event is crucial. EXAMPLE 4: DISABLING A PENDING TRANSMISSION If (RXBnOVFL == 1) { If (TXREQ == 1) { TXREQ = 0; If (TXABT == 1) MyFlag = 1; } } Temp_RXREG = RXBx; If (MyFlag) { TXREQ = 1; MyFlag = 0; } 2010 Microchip Technology Inc. // // // // Has an overflow occurred? Is a transmission pending? Clear transmit request Store transmission aborted status value // // // // Read receive Was previous Set transmit Reset stored buffer transmission aborted? request transmission aborted status DS80496C-page 9 PIC18F2480/2580/4480/4580 11. Module: ECAN Technology 13. Module: MSSP In Listen Only mode, the module may persistently set the IRXIF and RXB0IF interrupt flags, and the RXFUL status flag, after receiving 129 or more consecutive error frames. In this case, the flags can be cleared, but then will become set again immediately and continuously without receiving a bus message. In SPI mode, the SDO output may change after the inactive clock edge of the Bit 0 output. This may affect some SPI components that read data over 300 ns after the inactive edge of SCK. Work around Affected Silicon Revisions Place the ECAN module in Configuration mode before receiving 129 consecutive error frames and then place it back into Listen Only mode. Work around None. A1 B0 B2 X Affected Silicon Revisions A1 B0 B2 X 12. Module: 10-Bit Analog-to-Digital Converter When the AD clock source is selected as 2 TOSC or RC (when ADCS<2:0> = 000 or x11), in extremely rare cases, the EIL (Integral Linearity Error) and EDL (Differential Linearity Error) may exceed the data sheet specifications at codes, 511 and 512 only. Work around Select the AD clock source as 4 TOSC, 8 TOSC, 16 TOSC, 32 TOSC or 64 TOSC and avoid selecting 2 TOSC or RC. Affected Silicon Revisions A1 B0 B2 X DS80496C-page 10 2010 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Data Sheet Clarifications APPENDIX A: The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39637D): Rev A Document (2/2010) Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. None. DOCUMENT REVISION HISTORY Original release of this errata, combining previous errata for silicon revisions, A1 and B0, and superseding the data sheet errata. Added the B2 silicon revision, which had no issues. No data sheet issues were included as they had been resolved with a data sheet revision. This document replaces these errata documents: * DS80419B, "PIC18F2480/2580/4480/4580 Rev. B0 Silicon Errata" * DS80219E, "PIC18F2480/2580/4480/4580 Rev. A1 Silicon Errata" * DS80267C, "PIC18F2480/2580/4480/4580 Data Sheet Errata" Rev B Document (3/2010) Corrected an erroneous silicon revision reference in the revision history. Rev C Document (3/2010) Removed issue #1 from the document and renumbered the previous issues 2-14. Added B2 silicon as being affected by issue 1 (formerly 2) and removed A1 silicon from issue 2 (formerly 3). 2010 Microchip Technology Inc. DS80496C-page 11 PIC18F2480/2580/4480/4580 NOTES: DS80496C-page 12 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-067-6 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. 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