©2002 Fairchild Semiconductor Corporation
January 2002
Rev .B, January 2002
IRFP250N
IRFP250N
N-Channel Power MOSFET
200V, 30A, 0.075
Ω
Features
• Ultra Low On-Resistance
-r
DS(ON)
= 0.052
Ω
(Typ)
,
V
GS
=
10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER
©
Electrical Models
- Spice and SABER
©
Thermal Impedance Models
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
MOSFET Maximum Ratings
T
A
= 25°C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
V
DSS
Drain to Source Voltage 200 V
V
GS
Gate to Source Voltage
±
20 V
I
D
Drain Current
30 A
Continuous (T
C
= 25
o
C, V
GS
= 10V)
Continuous (T
C
= 100
o
C, V
GS
= 10V) 21 A
Pulsed Figure 4 A
E
AS
Single Pulse Avalanche Energy (Note 1) 315 mJ
P
D
Power dissipation
Derate above 25
o
C
214
1.4
W
W/
o
C
T
J
, T
STG
Operating and Storage Temperature -55 to 175
o
C
R
θ
JC
Thermal Resistance Junction to Case TO-247 0.70
o
C/W
R
θ
JA
Thermal Resistance Junction to Ambient TO-247 40
o
C/W
Device Marking Device Package Reel Size Tape Width Quantity
IRFP250N IRFP250N TO-247 Tube N/A 30
D
G
S
SOURCE
DRAIN
GATE
DRAIN
(TAB)
TO-247
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
IRFP250N
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
(V
GS
= 10V)
Drain-Source Diode Characteristics
Notes:
1:
Starting T
J
= 25°C, L = 1.9mH, I
AS
= 18A.
2:
Pulse width
≤
300
µ
s; duty cycle
≤
2%.
Symbol Parameter Test Conditions Min Typ Max Units
B
VDSS
Drain to Source Breakdown Voltage I
D
= 250
µ
A, V
GS
= 0V 200 - - V
I
DSS
Zero Gate Voltage Drain Current V
DS
= 200V V
GS
= 0V - - 25
µ
A
V
DS
= 160V T
C
= 150
o
- - 250
I
GSS
Gate to Source Leakage Current V
GS
=
±
20V - -
±
100 nA
V
GS(TH)
Gate to Source Threshold Voltage V
GS
= V
DS
, I
D
= 250
µ
A2-4V
r
DS(ON)
Drain to Source On Resistance I
D
= 18A, V
GS
= 10V - 0.052 0.075
Ω
g
fs
Forward Transconductance V
DS
= 50V, I
D
= 18A (Note 2) 17 - - S
C
ISS
Input Capacitance
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
- 4023 - pF
C
OSS
Output Capacitance - 880 - pF
C
RSS
Reverse Transfer Capacitance - 240 - pF
Q
g(TOT)
Total Gate Charge at 20V V
GS
= 0V to
20V
V
DD
= 160V
I
D
= 18A
I
g
= 2.0mA
215 280 nC
Q
g(10)
Total Gate Charge at 10V V
GS
= 0V to
10V - 114 140 nC
Q
g(TH)
Threshold Gate Charge V
GS
= 0V to 2V - 8 10 nC
Q
gs
Gate to Source Gate Charge - 14 - nC
Q
gd
Gate to Drain “Miller” Charge - 44 - nC
t
ON
Turn-On Time
V
DD
= 100V, I
D
= 18A
V
GS
= 10V, R
GS
= 3.9
Ω
- - 69 ns
t
d(ON)
Turn-On Delay Time - 16 - ns
t
r
Rise Time - 30 - ns
t
d(OFF)
Turn-Off Delay Time - 78 - ns
t
f
Fall Time - 40 - ns
t
OFF
Turn-Off Time - - 177 ns
V
SD
Source to Drain Diode Voltage I
SD
= 18A - - 1.3 V
t
rr
Reverse Recovery Time I
SD
= 18A, dI
SD
/dt = 100A/
µ
s - - 279 ns
Q
RR
Reverse Recovered Charge I
SD
= 18A, dI
SD
/dt = 100A/
µ
s - - 2000 nC
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
IRFP250N
Typical Characteristic
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150 0
10
20
30
40
25 50 75 100 125 150 175
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
VGS = 10V
0.1
1
10-5 10-4 10-3 10-2 10-1 100101
0.01
2
t, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
THERMAL IMPEDANCE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DESCENDING ORDER
SINGLE PULSE
10
100
1000
10-4 10-3 10-2 10-1 100101
10-5
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
IRFP250N
Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching
Capability
Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
Typical Characteristic (Continued)
1
10
100
1 10 100
500
500
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
SINGLE PULSE
100µs
10ms
1ms
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
1
10
100
0.001 0.01 0.1 1
200
10
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
STARTING TJ = 150oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0
25
50
75
234 5
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = 175oC
TJ = 25oC
TJ = -55oC
0
25
50
75
0123456
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS =4.5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
VGS = 10V
VGS = 5V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-80 -40 0 40 80 120 200
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 30A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
160
0.4
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 160 200
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
THRESHOLD VOLTAGE
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
IRFP250N
Figure 11. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 12. Capacitance vs Drain to Source
Voltage
Figure 13. Gate Charge Waveforms for Constant Gate Currents
Typical Characteristic (Continued)
0.9
1.0
1.1
1.2
1.3
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
100
1000
10000
0.1 1.0 10 100 200
30
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≅ CDS + CGD
0
2
4
6
8
10
0 20406080100120
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 160V
Qg, GATE CHARGE (nC)
ID = 18A
ID = 10A
WAVEFORMS IN
DESCENDING ORDER:
Test Circuits and Waveforms
Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
IRFP250N
Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms
Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
IRFP250N
PSPICE Electrical Model
.SUBCKT IRFP250N 2 1 3 ; rev May 2001
CA 12 8 6.6e-9
CB 15 14 6.5e-9
CIN 6 8 3.80e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 221
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 8.05e-9
LSOURCE 3 7 5.8e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5.0e-2
RGATE 9 20 0.77
RLDRAIN 2 5 10
RLGATE 1 9 80.5
RLSOURCE 3 7 58
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.8e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),2.5))}
.MODEL DBODYMOD D (IS = 2.8e-12 RS = 3.0e-3 XTI = 5.5 TRS1 = 3.5e-3 TRS2 = 1e-5 CJO = 2.55e-9 TT = 1.52e-7 M = 0.42)
.MODEL DBREAKMOD D (RS = 1.2e-0 TRS1 = 1e-3 TRS2 = 1e-6)
.MODEL DPLCAPMOD D (CJO = 4.6e-9 IS = 1e-30 N = 10 M = 0.9)
.MODEL MMEDMOD NMOS (VTO = 3.05 KP = 2.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.77)
.MODEL MSTROMOD NMOS (VTO = 3.55 KP = 100 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.69 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 7.70 )
.MODEL RBREAKMOD RES (TC1 =1.27e-3 TC2 = 1.0e-6)
.MODEL RDRAINMOD RES (TC1 = 9.90e-3 TC2 = 3.60e-5)
.MODEL RSLCMOD RES (TC1 = 3.0e-3 TC2 = 1.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.90e-3 TC2 = -1.10e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.80e-3 TC2 = 1.70e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.5 VOFF= -4.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.5 VOFF= -5.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.3 VOFF= 0.4)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.4 VOFF= -0.3)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
IRFP250N
SABER Electrical Model
REV May 2001
template IRFP250N n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 2.8e-12, rs = 3.0e-3, xti = 5.5, trs1 = 3.5e-3, trs2 = 1.0e-5, cjo = 2.55e-9, tt = 1.52e-7, m = 0.42)
dp..model dbreakmod = (rs = 1.2, trs1 = 1.0e-3, trs2 = 1.0e-6)
dp..model dplcapmod = (cjo = 4.6e-9, isl = 10e-30, nl=10, m = 0.9)
m..model mmedmod = (type=_n, vto = 3.05, kp = 2.5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.55, kp = 100, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.69, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -4.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -4.5, voff = -5.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.4)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.4, voff = -0.3)
c.ca n12 n8 = 6.6e-9
c.cb n15 n14 = 6.5e-9
c.cin n6 n8 = 3.8e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 8.05e-9
l.lsource n3 n7 = 5.80e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.27e-3, tc2 = 1.00e-6
res.rdrain n50 n16 = 5.0e-2, tc1 = 9.9e-3, tc2 =3.6e-5
res.rgate n9 n20 = 0.77
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 80.5
res.rlsource n3 n7 = 58
res.rslc1 n5 n51= 1e-6, tc1 = 3e-3, tc2 = -1.0e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.8e-3, tc1 = 1.0e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.8e-3, tc2 = 1.70e-6
res.rvthres n22 n8 = 1, tc1 = -2.9e-3, tc2 = 1.1e-5
spe.ebreak n11 n7 n17 n18 = 221
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6*100))** 2.5))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
IRFP250N
SPICE Thermal Model
REV May 2001
IRFP250N
CTHERM1 th 6 6.45e-3
CTHERM2 6 5 3.00e-2
CTHERM3 5 4 1.40e-2
CTHERM4 4 3 1.65e-2
CTHERM5 3 2 4.85e-2
CTHERM6 2 tl 1.00e-1
RTHERM1 th 6 3.24e-3
RTHERM2 6 5 8.08e-3
RTHERM3 5 4 2.28e-2
RTHERM4 4 3 1.00e-1
RTHERM5 3 2 1.10e-1
RTHERM6 2 tl 1.40e-1
SABER Thermal Model
SABER thermal model IRFP250N
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 6.45e-3
ctherm.ctherm2 6 5 = 3.00e-2
ctherm.ctherm3 5 4 = 1.40e-2
ctherm.ctherm4 4 3 = 1.65e-2
ctherm.ctherm5 3 2 = 4.85e-2
ctherm.ctherm6 2 tl = 1.00e-1
rtherm.rtherm1 th 6 = 3.24e-3
rtherm.rtherm2 6 5 = 8.08e-3
rtherm.rtherm3 5 4 = 2.28e-2
rtherm.rtherm4 4 3 = 1.00e-1
rtherm.rtherm5 3 2 = 1.10e-1
rtherm.rtherm6 2 tl = 1.40e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
Rev. H4
ACEx™
Bottomless™
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CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
STAR*POWER is used under license
VCX™
