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3/2/06
IRFB4019PbF
Notes through are on page 2
PD - 97075
DIGITAL AUDIO MOSFET
Features
Key Parameters Optimized for Class-D Audio
Amplifier Applications
Low RDSON for Improved Efficiency
Low QG and QSW for Better THD and Improved
Efficiency
Low QRR for Better THD and Lower EMI
175°C Operating Junction Temperature for
Ruggedness
Can Deliver up to 200W per Channel into 8 Load in
Half-Bridge Configuration Amplifier
Description
This Digital Audio MOSFET is specifically designed for Class-D audio amplifier applications. This MOSFET utilizes
the latest processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode
reverse recovery and internal Gate resistance are optimized to improve key Class-D audio amplifier performance
factors such as efficiency, THD and EMI. Additional features of this MOSFET are 175°C operating junction
temperature and repetitive avalanche capability. These features combine to make this MOSFET a highly efficient,
robust and reliable device for ClassD audio amplifier applications.
S
D
G
TO-220AB
D
S
D
G
GDS
Gate Drain Source
Absolute Maximum Ratings
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
IDM Pulsed Drain Current c
PD @TC = 25°C Power Dissipation fW
PD @TC = 100°C Power Dissipation f
Linear Derating Factor W/°C
TJ Operating Junction and °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case f––– 1.88
RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient f––– 62
Max.
12
51
±20
150
17
80
40
0.5
10lbxin (1.1Nxm)
-55 to + 175
300
VDS 150 V
RDS(ON) typ. @ 10V 80 m:
Qg typ. 13 nC
Qsw typ. 5.1 nC
RG(int) typ. 2.4
TJ max 175 °C
Key Parameters
IRFB4019PbF
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S
D
G
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 1.46mH, RG = 25, IAS = 10A.
Pulse width 400µs; duty cycle 2%.
Notes:
Rθ is measured at TJ of approximately 90°C.
Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive
avalanche information
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BVDSS Drain-to-Source Breakdown Voltage 150 ––– ––– V
∆ΒVDSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.19 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 80 95 m
VGS(th) Gate Threshold Voltage 3.0 ––– 4.9 V
VGS(th)/TJGate Threshold Voltage Coefficient ––– -13 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
gfs Forward Transconductance 14 ––– ––– S
QgTotal Gate Charge ––– 13 20
Qgs1 Pre-Vth Gate-to-Source Charge ––– 3.3 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 0.95 ––– nC
Qgd Gate-to-Drain Charge ––– 4.1 –––
Qgodr Gate Charge Overdrive ––– 4.7 ––– See Fig. 6 and 19
Qsw Switch Charge (Qgs2 + Qgd)––– 5.1 –––
RG(int) Internal Gate Resistance ––– 2.4 –––
td(on) Turn-On Delay Time ––– 7.0 –––
trRise Time ––– 13 –––
td(off) Turn-Off Delay Time ––– 12 ––– ns
tfFall Time ––– 7.8 –––
Ciss Input Capacitance ––– 800 –––
Coss Output Capacitance ––– 74 ––– pF
Crss Reverse Transfer Capacitance ––– 19 –––
Coss Effective Output Capacitance ––– 99 –––
LDInternal Drain Inductance ––– 4.5 ––– Between lead,
nH 6mm (0.25in.)
LSInternal Source Inductance ––– 7.5 ––– from package
Avalanche Characteristics
Parameter Units
EAS Single Pulse Avalanche Energy
d
mJ
IAR Avalanche Current
g
A
EAR Repetitive Avalanche Energy
g
mJ
Diode Characteristics
Parameter Min. Typ. Max. Units
IS @ TC = 25°C Continuous Source Current ––– ––– 17
(Body Diode) A
ISM Pulsed Source Current ––– ––– 51
(Body Diode)
c
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time ––– 64 96 ns
Qrr Reverse Recovery Charge ––– 160 240 nC
––– 73
See Fig. 14, 15, 17a, 17b
ID = 10A
Typ. Max.
ƒ = 1.0MHz, See Fig.5
TJ = 25°C, IF = 10A
di/dt = 100A/µs
e
TJ = 25°C, IS = 10A, VGS = 0V
e
showing the
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 10A
e
VDS = VGS, ID = 50µA
VDS = 150V, VGS = 0V
VGS = 0V, VDS = 0V to 120V
VDS = 150V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
VGS = 10V
ID = 10A
VGS = 0V
MOSFET symbol
RG = 2.4
VDS = 10V, ID = 10A
Conditions
and center of die contact
VDD = 75V, VGS = 10V
e
VDS = 75V
VDS = 50V
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Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
ID, Drain-to-Source Current (A)
60µs PULSE WIDTH
Tj = 25°C
5.0V
VGS
TOP 15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
ID, Drain-to-Source Current (A)
60µs PULSE WIDTH
Tj = 175°C
5.0V
VGS
TOP 15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
2 4 6 8 10
VGS, Gate-to-Source Voltage (V)
0.1
1.0
10.0
100.0
ID, Drain-to-Source Current
(Α)
VDS = 25V
60µs PULSE WIDTH
TJ = 25°C
TJ = 175°C
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ, Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 10A
VGS = 10V
110 100 1000
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 5 10 15 20
QG Total Gate Charge (nC)
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
VDS= 120V
VDS= 75V
VDS= 30V
ID= 10A
IRFB4019PbF
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1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
Thermal Response ( Z
thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area
Fig 10. Threshold Voltage vs. Temperature
0.0 0.5 1.0 1.5
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
25 50 75 100 125 150 175
TJ , Junction Temperature (°C)
0
4
8
12
16
20
ID , Drain Current (A)
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
1.0
2.0
3.0
4.0
5.0
VGS(th) Gate threshold Voltage (V)
ID = 50µA
Ri (°C/W)
τι
(sec)
0.535592 0.000222
0.913763 0.001027
0.432454 0.006058
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
τ
τ
C
Ci= τi/Ri
Ci= τi/Ri
1 10 100 1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
DC
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Fig 13. Maximum Avalanche Energy Vs. Drain Current
Fig 12. On-Resistance Vs. Gate Voltage
Fig 14. Typical Avalanche Current Vs.Pulsewidth
Fig 15. Maximum Avalanche Energy Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long as neither
Tjmax nor Iav (max) is exceeded
3. Equation below based on circuit and waveforms shown in
Figures 17a, 17b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
4 6 8 10 12 14 16
VGS, Gate-to-Source Voltage (V)
0.0
0.1
0.2
0.3
0.4
0.5
RDS(on), Drain-to -Source On Resistance (
)
TJ = 25°C
TJ = 125°C
ID = 10A
25 50 75 100 125 150 175
Starting TJ, Junction Temperature (°C)
0
50
100
150
200
250
300
EAS, Single Pulse Avalanche Energy (mJ)
I D
TOP 1.3A
2.3A
BOTTOM 10A
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 10A
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
IRFB4019PbF
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Fig 18a. Switching Time Test Circuit Fig 18b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
Fig 17b. Unclamped Inductive Waveforms
Fig 17a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 19a. Gate Charge Test Circuit Fig 19b Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 16. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
*** VGS = 5V for Logic Level Devices
***
+
-
+
+
+
-
-
-
RGVDD
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
**
*
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50K
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
IRFB4019PbF
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/06
TO-220AB packages are not recommended for Surface Mount Application.
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
LOT CODE 1789
EXAMPLE: THIS IS AN IRF1010
Note: "P" in assembly line position
indicates "L ead - F r ee"
IN THE ASSEMBLY LINE "C"
AS S EMBLED ON WW 19, 2000
INTERNATIONAL PART NUMBER
RECTIFIER
LOT CODE
AS S E MB L Y
LOGO
YEAR 0 = 2000
DAT E CODE
WE E K 19
LINE C
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/