LTC2934ITS8-1#TRPBF - Linear Technology

LTC2934

2934f

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Ultra-Low Power

Adjustable Supervisor with

Power-Fail Output

The LTC

2934 ultra-low power voltage monitor provides

system initialization, power-fail warning and reset gen-

eration functions. Low quiescent current (500nA typical)

makes the LTC2934 an ideal choice for battery-operated

applications.

Precision power-fail and reset voltages can be conﬁ gured

independently. Early warning of an impending low volt-

age condition is provided at the power-fail output (PFO)

when the PFI input falls below 0.4V. Supervisory circuits

monitor the ADJ input and pull RST low when ADJ falls

below 0.4V. When ADJ is rising from an under-threshold

condition, an internal reset timer is started after exceeding

the ADJ threshold by 5%. The reset timeout delays the

return of the RST output to a high state. A pushbutton

switch connected to the MR input is typically used to

force a manual reset. Outputs RST and PFO are available

with open-drain (LTC2934-1) or active pull-up circuits

(LTC2934-2). Operating temperature range is from –40ºC

to 85ºC.

Conﬁ gurable Low Power Voltage Supervisor

n 500nA Quiescent Current

n ±1.5% (Max) Accuracy over Temperature

n Operates Down to 1.6V Supply

n Adjustable Reset Threshold

n Adjustable Power-Fail Threshold

n Early Warning Power-Fail Output

n Selectable 15ms or 200ms Reset Timeout

n Manual Reset Input

n Compact 8-Lead, 2mm × 2mm DFN and TSOT-23

(ThinSOT™) Packages

n Portable Equipment

n Battery-Powered Equipment

n Security Systems

n Point-of-Sale Devices

n Wireless Systems

, LT, LTC, LTM are registered trademarks of Linear Technology Corporation. ThinSOT is

a trademark of Linear Technology Corporation. All other trademarks are the property of

their respective owners.

Selectable Reset Timeout Period

VCC

VIN

BATTERY

POWERED

SYSTEM

LOGIC

2934 TA01a

0.1μF PFO

RST

LTC2934-2

GNDRT

ADJ

PFI

750k

11.8k

237k

POWER FAIL FALLING THRESHOLD = 1.686V

RESET FALLING THRESHOLD = 1.606V

RST, RT = GND

RST, RT = VCC

VCC

15ms

200ms

2934 TA01b

LTC2934

2934f

ABSOLUTE MAXIMUM RATINGS

Input Voltages

CC ........................................................... –0.3V to 6V

ADJ, PFI ................................................... –0.3V to 6V

RT, MR ......................................–0.3V to (VCC + 0.3V)

Output Voltages

PFO, RST (LTC2934-1)............................. –0.3V to 6V

PFO, RST (LTC2934-2)..............–0.3V to (VCC + 0.3V)

(Note 1)

TOP VIEW

VCC

RST

PFO

ADJ

PFI

GND

DC PACKAGE

8-LEAD (2mm × 2mm) PLASTIC DFN

TJMAX = 125°C, θJA = 102°C/W

EXPOSED PAD (PIN 9) PCB GND CONNECTION OPTIONAL

VCC

RST

PFO

ADJ 1

PFI 2

RT 3

GND 4

TOP VIEW

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

TJMAX = 125°C, θJA = 195°C/W

PIN CONFIGURATION

ORDER INFORMATION

RMS Currents

PFO, RST ..........................................................±5mA

Operating Ambient Temperature Range

LTC2934C ................................................ 0°C to 70°C

LTC2934I.............................................. –40°C to 85°C

Storage Temperature Range ................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

TSOT-23 Package .............................................. 300°C

Lead Free Finish

TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2934CTS8-1#TRMPBF LTC2934CTS8-1#TRPBF LTDKR 8-Lead Plastic TSOT-23 0°C to 70°C

LTC2934ITS8-1#TRMPBF LTC2934ITS8-1#TRPBF LTDKR 8-Lead Plastic TSOT-23 –40°C to 85°C

LTC2934CTS8-2#TRMPBF LTC2934CTS8-2#TRPBF LTDKS 8-Lead Plastic TSOT-23 0°C to 70°C

LTC2934ITS8-2#TRMPBF LTC2934ITS8-2#TRPBF LTDKS 8-Lead Plastic TSOT-23 –40°C to 85°C

LTC2934CDC-1#TRMPBF LTC2934CDC-1#TRPBF LDKT 8-Lead (2mm × 2mm) Plastic DFN 0°C to 70°C

LTC2934IDC-1#TRMPBF LTC2934IDC-1#TRPBF LDKT 8-Lead (2mm × 2mm) Plastic DFN –40°C to 85°C

LTC2934CDC-2#TRMPBF LTC2934CDC-2#TRPBF LDKV 8-Lead (2mm × 2mm) Plastic DFN 0°C to 70°C

LTC2934IDC-2#TRMPBF LTC2934IDC-2#TRPBF LDKV 8-Lead (2mm × 2mm) Plastic DFN –40°C to 85°C

TRM = 500 pieces. *Temperature grades are identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

Consult LTC Marketing for information on lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

LTC2934

2934f

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC VCC Input Supply Voltage l1.6 5.5 V

ICC VCC Input Supply Current l225 500 1000 nA

Threshold Adjustment Inputs: ADJ, PFI

VTH Input Threshold (Monitored Voltage Falling) l394 400 406 mV

VTHM ADJ to PFI Threshold Matching l ±2 ±8 mV

VADJ(HYST) Reset Threshold Hysteresis

(Monitored Voltage Rising)

l18 20 25 mV

VPFI(HYST) Power-Fail Threshold Hysteresis

(Monitored Voltage Rising)

l81015 mV

tUV Undervoltage Detect to RST or PFO Falling VADJ or VPFI = VTH – 4mV (Note 3) 1 ms

ITH(LKG) Threshold Adjustment Input Leakage Current VADJ or VPFI = 420mV l 0.1 ±1 nA

Control Inputs: MR, RT

VIN(TH) Control Input Threshold RT

0.3 • VCC

0.4

0.7 • VCC

1.4

tPW Input Pulse Width MR l20 μs

tPD Propagation Delay to RST Falling Manual Reset Falling l2520 μs

RPU Internal Pull-Up Resistance MR l600 900 1200 kΩ

ILK Input Leakage Current (RT Input) RT = VCC or GND l±1 ±10 nA

Reset and Power Fail Outputs: RST, PFO

VOL Voltage Output Low VCC = 1V, 200μA Pull-Up Current

VCC = 3V, 3mA Pull-Up Current

100

150

VOH Voltage Output High (LTC2934-2) –200μA Pull-Down Current l0.7 • VCC V

IOH Leakage Current, Output High (LTC2934-1) VRST, VPFO = 3.6V l ±1 ±10 nA

tRST Reset Timeout Period RT Input High

RT Input Low

140

200

260

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C, VCC = 3.6V, unless otherwise noted. (Note 2)

Note 2. All currents into pins are positive, all voltages are referenced to

GND unless otherwise noted.

Note 3. Guaranteed by design. Characterized, but not production tested.

LTC2934

2934f

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current vs Supply Voltage ADJ, PFI Threshold vs Temperature

Comparator Undervoltage

Glitch Immunity

Reset Timeout Period

vs Temperature

Voltage Output Low vs Pull-Up

Current (RST, PFO)

Voltage Output High vs Pull-Down

Current (RST, PFO)

VCC (V)

ICC (nA)

200

400

600

800

1000

1234

2934 G01

–40°C

25°C

85°C

EXTERNALLY CONFIGURED

FOR 3V FALLING THRESHOLDS

PULL-UP CURRENT (mA)

VOL (mV)

100

1234

2934 G05

–40°C

25°C

85°C

VCC = 3V

PULL-DOWN CURRENT (mA)

3.2

VOH (mV)

3.3

3.4

3.5

3.6

–0.2 –0.4 –0.6 –0.8

2934 G06

–1

–40°C

25°C

85°C

LTC2934-2

VCC = 3.6V

TEMPERATURE (°C)

–50

394

VTH (mV)

396

398

400

402

406

–25 02550

2934 G02

75 100

404

TEMPERATURE (°C)

–50

140

tRST (ms)

160

180

200

220

260

–25 02550

2934 G04

75 100

240

VCC = RT = 3.6V

COMPARATOR OVERDRIVE (%)

0.1

2.0

GLITCH DURATION, tUV (ms)

2.5

1 10 100

1.5

1.0

0.5

3.0

2934 G03

VCC = 3.6V

COMPARATORS PULL DOWN

ABOVE CURVE

TA = 25°C, unless otherwise noted.

LTC2934

2934f

Supply Current vs RT

Input Voltage Supply Current vs MR Input Voltage

PIN FUNCTIONS

ADJ: Reset Threshold Adjustment Input. Tie to resistive

divider between monitored voltage and GND to conﬁ gure

desired reset threshold. See the Applications Information

section for details. Tie to VCC if unused.

Exposed Pad (DFN Only): Exposed Pad may be left ﬂ oating

or connected to device ground.

GND: Device Ground.

MR: Manual Reset Input. Attach a push-button switch

between this input and ground. A logic low on this input

pulls RST low. When the MR input returns to logic high,

RST returns high after the reset timer has expired. Tie to

VCC if unused.

PFI: Power-Fail Threshold Adjustment Input. Tie to

resistive divider between monitored voltage and GND

to configure desired power-fail threshold. See the

Applications Information section for details. Tie to VCC or

GND if unused.

PFO: Power-Fail Output. PFO pulls low when monitored

voltage falls below the power-fail (PFI) threshold. PFO

is released when the PFI voltage rises above the power-

fail threshold by 2.5%. PFO is available with open-drain

(LTC2934-1) or active pull-up (LTC2934-2) outputs. Leave

open if unused.

RST: Reset Output. RST pulls low when monitored volt-

age falls below the reset threshold. RST is released after

monitored voltage exceeds the reset threshold plus 5%

hysteresis and after reset timer has expired. RST is available

with open-drain (LTC2934-1) or active pull-up (LTC2934-2)

outputs. Leave open if unused.

RT: Reset Timeout Selection Input. Tie to GND or VCC for

desired reset timeout. Tie low for 15ms delay or high for

200ms delay.

VCC: Power Supply Input. Bypass VCC with 0.1μF to

GND.

TYPICAL PERFORMANCE CHARACTERISTICS

RT INPUT VOLTAGE (V)

ICC (μA)

200

3.5

150

100

0.5 1.5 2.5 3 4

250

2934 G07

VCC = 3.6V

MR INPUT VOLTAGE (V)

ICC (μA)

3.5

0.5 1.5 2.5 3 4

2934 G08

VCC = 3.6V

TA = 25°C, unless otherwise noted.

LTC2934

2934f

BLOCK DIAGRAM

TIMING DIAGRAM

900k

LTC2934-2 OPTION

VCC

2934 BD

VCC

RST

PFO

–

ADJ

0.4V

PFI

RESET

DELAY

LTC2934-2 OPTION

VCC

GND

MR RT

VTH

VTH+HYST

VPFI

PFO

2935 TD01

VTH

VTH+HYST

tRST

2935 TD02

VADJ

RST

tRST

tPD

PFI/ PFO Timing

ADJ/ RST Timing

LTC2934

2934f

APPLICATIONS INFORMATION

VOLTAGE MONITORING

Unmanaged power can cause various system problems.

At power-up, voltage ﬂ uctuation around critical thresholds

can cause improper system or processor initialization.

The LTC2934 provides power management capabilities

for the system power-up phase. The supervisory device

issues a system reset after the monitored voltage has

stabilized. Built-in hysteresis and ﬁ ltering ensures that

ﬂ uctuations due to load transients or supply noise do

not cause chattering of the status outputs. Comparator

undervoltage glitch immunity is shown in the Typical

Performance Characteristics section. The curve dem-

onstrates the transient amplitude and width required to

switch the comparators.

Because many batteries exhibit large series resistance,

load currents can cause signiﬁ cant voltage drops. The

low DC current draw of the LTC2934 (at any input volt-

age) does not add to the loading problem. When voltage

is initially applied to VCC, RST and PFO pull low once there

is enough voltage to turn on the pull-down devices (1V

maximum).

If the monitored supply voltage falls to the power-fail

threshold, the built-in power-fail comparator pulls PFO low.

PFO remains low until the PFI input rises above 0.4V plus

2.5% hysteresis. PFO is typically used to signal preparation

for controlled shutdown. For example, the PFO output may

be connected to a processor nonmaskable interrupt. Upon

interrupt, the processor begins shutdown procedures such

as supply sequencing and/or storage/erasure of system

state in nonvolatile memory.

If the monitored voltage drops below the reset threshold,

RST pulls low until the ADJ input rises above 0.4V plus

5% hysteresis. This may occur through battery charging

or replacement. An internal reset timer delays the return

of the RST output to a high state to provide settling and

initialization time. The RST output is typically connected

to processor reset input.

Few, if any external components are necessary for reliable

operation. However, a decoupling capacitor between VCC

and ground is recommended (0.01μF minimum).

Threshold Conﬁ guration

The LTC2934 monitors voltage applied to its inputs PFI and

ADJ. A resistive divider connected between a monitored

voltage and ground is used to bias the inputs. Figure 1

demonstrates how the monitor inputs can be made de-

pendent upon a single voltage (V1). Only three resistors

are required. To calculate their values, specify desired

falling power fail (VPF) and reset voltages (VR) with VPF

> VR. For example:

PF = 1.72V, VR = 1.62V

Figure 1. Conﬁ guration for Single Voltage Monitoring

2934 F01

ADJ

PFI

LTC2934

The solution for R1, R2, and R3 provides three equations

and three unknowns. Maximum resistor size is governed

by maximum input leakage current. For the LTC2934, the

maximum input leakage current over temperature is 1nA.

For a maximum error of 1% due to both input currents,

the resistor divider current should be 100 times the sum

of the leakage currents, or 0.2μA. At the reset threshold,

V1 = 1.62V, so RSUM = V1/0.2μA = 8.1M where:

SUM = R1 + R2 + R3

The falling monitor thresholds (VTH) are 0.4 volts, so:

RVR

TH SUM

104 81

172 188===

•.•.

The closest 1% value is 1.87M. R2 can be determined

from:

RVR

VRVM

TH SUM

04 81

162 187

2 130

==−

•–.•.

LTC2934

2934f

APPLICATIONS INFORMATION

Figure 3. RST vs VCC with 10k Pull-Up

R3 is easily obtained from:

R3 = RSUM – R1 – R2 = 8.1M – 1.87M – 130k = 6.1M

The closest 1% value is 6.04M. Plugging the standard

values back into the equations yields the design values

for the falling power-fail and reset voltages:

PF = 1.720V, VR = 1.608V

Figure 2 demonstrates how the inputs can be biased

to monitor two voltages (V1, V2). In this example, four

resistors are required. Calculate each divider ratio for the

desired falling threshold (VFT) using:

RnB

RnA

=−=−104 1

In Figure 2, PFO is tied back to the MR input, making the

state of the RST output dependent upon both V1 and V2. If

V1 and V2 are both above the conﬁ gured falling threshold

plus hysteresis, RST is allowed to pull high. If independent

operation of the status outputs is desired, simply omit the

PFO to MR connection.

Selecting Output Logic Style

The LTC2934 status outputs are available in two options:

open-drain (LTC2934-1) or active pull-up (LTC2934-2).

The open-drain option (LTC2934-1) allows the outputs

to be pulled up to a user deﬁ ned voltage with a resistor.

The open-drain pull-up voltage may be greater than VCC

(5.5V maximum), which is not always possible with

inferior battery supervisors, due to internal diode clamps.

When the status outputs are low, power is dissipated in

the pull-up resistors. Recommended resistor values lie in

the range between 10k and 470k. Figure 3 demonstrates

typical LTC2934-1 RST output behavior.

The active pull-up option (LTC2934-2) eliminates the

need for external pull-up resistors on the status outputs.

Integrated pull-up devices pull the outputs up to VCC.

Actively pulled up outputs may not be driven above VCC.

Some applications require the RST and/or PFO outputs to

be valid with VCC down to ground. Active pull-up handles

this requirement with the addition of an external resistor

from the output to ground. The resistor provides a path

for leakage currents, preventing the output from ﬂ oating to

undetermined voltages when connected to high impedance

(such as CMOS logic inputs). The resistor value should

be small enough to provide effective pull-down without

excessively loading the pull-up circuitry. A 100k resistor

from output to ground is satisfactory for most applications.

When the status outputs are high, power is dissipated in

the pull-down resistors. Figure 4 demonstrates typical

LTC2934-2 RST output behavior.

Figure 4. RST vs VCC

2934 F02

ADJ

PFI

LTC2934

R1B

R2B

R2A R1A

RST

PFO

Figure 2. Dual Voltage Monitoring

VCC (V)

RST (V)

2.0

2.5

3.0

1.5

1.0

0.5 1.5 2.5 3 3.5

0.5

3.5

2934 F03

EXTERNALLY CONFIGURED

FOR 3V FALLING THRESHOLD

LTC2934-1

VCC (V)

RST (V)

2.0

2.5

3.0

1.5

1.0

0.5 1.5 2.5 3 3.5

0.5

3.5

2934 F04

EXTERNALLY CONFIGURED

FOR 3V FALLING THRESHOLD

LTC2934-2

LTC2934

2934f

TYPICAL APPLICATIONS

Battery Monitor with Interface to Low Voltage Logic

Alkaline Cell Stack Voltage Monitor Coin Cell Voltage Monitor

1.18M

1μF

590k 100k

324k

100k

VCC VDD

μP

POWER FAIL FALLING THRESHOLD = 3.192V

RESET FALLING THRESHOLD = 1.696V

*OPTIONAL RESISTOR FOR ADDED ESD PROTECTION

2934 TA02

698k

100k

NMI

RST

ADJ

Li-Ion

0.1μF

SHDN

IN OUT

3μA LDO 1.8V

ADJ

PFO

PB1

RST

PFI

LTC2934-1

LT3009

RESD*

10k

GND

VCC

2934 TA03

ADJ

1.5V

0.1μF

PFI

LTC2934-2

GND

1.5V

RST

PFO

POWER FAIL THRESHOLD = 2.628V

RESET THRESHOLD = 2.428V

845k

12.7k

LOW BATTERY

SYSTEM RESET

154k

APPLICATIONS INFORMATION

Manual Reset Input

When VCC is above its reset threshold, and the manual

reset input (MR) is pulled low, the RST output is forced

low. RST remains low for the selected reset timeout

period after the manual reset input is released and pulled

high. The manual reset input is pulled up internally through

900k to VCC. If external leakage currents have the ability

to pull down the manual reset input below its logic thresh-

old, a lower value pull-up resistor, placed between VCC and

MR will ﬁ x the problem.

Input MR is often pulled down through a pushbutton

switch requiring human contact. If extended ESD toler-

ance is required, series resistance between the switch and

the input is recommended. For most applications a 10k

resistor provides sufﬁ cient current limiting.

Selecting the Reset Timeout Period

Use the RT input to select between two ﬁ xed reset timeout

periods. Connect RT to ground for a 15ms timeout. Connect

RT to VCC for a 200ms timeout. The reset timeout period

occurs after the ADJ input is driven above threshold. After

the reset timeout period, the RST output is allowed to pull

up to a high state.

VCC

2934 TA04

ADJ

0.1μF

PFI

LTC2934-2

GND

CR2032

RST

PFO

POWER FAIL THRESHOLD = 2.727V

RESET THRESHOLD = 2.553V

845k

10k

147k

LOW BATTERY

SYSTEM RESET

LTC2934

2934f

2.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

0.64 ± 0.10

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

R = 0.05

TYP

1.37 ±0.10

(2 SIDES)

PIN 1 BAR

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DC8) DFN 0106 REVØ

0.23 ± 0.05

0.45 BSC

0.25 ± 0.05

1.37 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.64 ±0.05

(2 SIDES)

1.15 ±0.05

0.70 ±0.05

2.55 ±0.05

PACKAGE

OUTLINE

0.45 BSC

PIN 1 NOTCH

R = 0.20 OR

0.25 × 45°

CHAMFER

PACKAGE DESCRIPTION

DC Package

8-Lead Plastic DFN (2mm × 2mm)

(Reference LTC DWG # 05-08-1719 Rev Ø)

LTC2934

2934f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

1.50 – 1.75

(NOTE 4)

2.80 BSC

0.22 – 0.36

8 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20

(NOTE 3) TS8 TSOT-23 0802

2.90 BSC

(NOTE 4)

0.65 BSC

1.95 BSC

0.80 – 0.90

1.00 MAX 0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.52

MAX

0.65

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.4 MIN

2.62 REF

1.22 REF

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637)

LTC2934

2934f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0508 • PRINTED IN USA

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590k 100k

100k

VCC

LOW BATTERY

EARLY WARNING

2934 TA05

ADJ

Li-Ion

SHDN

IN OUT

3μA LDO

1.8V

ADJ

PFO

PFI

LTC2934-1

LT3009

GND

RST

POWER FAIL FALLING THRESHOLD = 3.148V

RESET FALLING THRESHOLD = 2.998V

0.1μF

866k

6.34k

127k