LTC1871EMS-1#PBF - LINEAR TECHNOLOGY

LTC1871-1

18711fb

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Wide Input Range, No RSENSE™

Current Mode Boost,

Flyback and SEPIC Controller

The LTC

1871-1 is a wide input range, current mode, boost,

ﬂ yback or SEPIC controller that drives an N-channel power

MOSFET and requires very few external components. It

eliminates the need for a current sense resistor by utilizing

the power MOSFET’s on-resistance, thereby maximizing

efﬁ ciency. Higher output voltage applications are possible

with the LTC1871-1 by connecting the SENSE pin to a

resistor in the source of the power MOSFET.

The IC’s operating frequency can be set with an external

resistor over a 50kHz to 1MHz range, and can be synchro-

nized to an external clock using the MODE/SYNC pin.

The LTC1871-1 differs from the LTC1871 by having a

lower pulse skip threshold, making it ideal for applica-

tions requiring constant frequency operation at light

loads. The lower pulse skip threshold also helps maintain

constant frequency operation in applications with a wide

input voltage range. For applications requiring primary-

to-secondary side isolation, please refer to the LTC1871

datasheet.

The LTC1871-1 is available in the 10-lead MSOP package.

Efﬁ ciency of Figure 1

n High Efﬁ ciency (No Sense Resistor Required)

Wide Input Voltage Range: 2.5V to 36V

Current Mode Control Provides Excellent

Transient Response

High Maximum Duty Cycle (92% Typ)

±2% RUN Pin Threshold with 100mV Hysteresis

±1% Internal Voltage Reference

n Ultra Low Pulse Skip Threshold for Wide Input

Range Applications

n Micropower Shutdown: IQ = 10µA

Programmable Operating Frequency

(50kHz to 1MHz) with One External Resistor

Synchronizable to an External Clock Up to 1.3 × fOSC

User-Controlled Pulse Skip or Burst Mode

Operation

Internal 5.2V Low Dropout Voltage Regulator

Output Overvoltage Protection

Capable of Operating with a Sense Resistor for High

Output Voltage Applications

n Small 10-Lead MSOP Package

n Telecom Power Supplies

n Portable Electronic Equipment

L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation.

No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Figure 1. High Efﬁ ciency 3.3V Input, 5V Output Boost Converter (Bootstrapped)

RUN

ITH

FREQ

MODE/SYNC

SENSE

VIN

INTVCC

GATE

GND

LTC1871-1

80.6k

37.4k

12.1k

1% CVCC

4.7µF

X5R

CIN

22µF

6.3V

×2

1µH

22k

CC1

6.8nF

CC2

47pF

COUT1

150µF

6.3V

×4

VIN

3.3V

VOUT

(10A PEAK)

GND

18711 F01a

COUT2

22µF

6.3V

X5R

×2

CIN: TAIYO YUDEN JMK325BJ226MM

COUT1: PANASONIC EEFUEOJ151R

COUT2: TAIYO YUDEN JMK325BJ226MM

D1: MBRB2515L

L1: SUMIDA CEP125-H 1R0MH

M1: FAIRCHILD FDS7760A OUTPUT CURRENT (A)

EFFICIENCY (%)

100

0.001 0.1 1 10

18711 F01b

0.01

Burst Mode

OPERATION

PULSE-SKIP

MODE

LTC1871-1

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PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

VIN Voltage ............................................... – 0.3V to 36V

INTVCC Voltage ............................................ –0.3V to 7V

INTVCC Output Current .......................................... 50mA

GATE Voltage ............................ –0.3V to VINTVCC + 0.3V

ITH, FB Voltages ....................................... –0.3V to 2.7V

RUN, MODE/SYNC Voltages ....................... –0.3V to 7V

FREQ Voltage ............................................ –0.3V to 1.5V

SENSE Pin Voltage .................................... –0.3V to 36V

Operating Junction Temperature Range (Note 2)

LTC1871E-1 ......................................... –40°C to 85°C

LTC1871I-1 ........................................ –40°C to 125°C

Junction Temperature (Note 3) ............................ 125°C

Storage Temperature Range ................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

(Note 1)

RUN

ITH

FREQ

MODE/

SYNC

SENSE

VIN

INTVCC

GATE

GND

TOP VIEW

MS PACKAGE

10-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 120°C/W

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC1871EMS-1#PBF LTC1871EMS-1#TRPBF LTCTV 10-Lead Plastic MSOP –40°C to 85°C

LTC1871IMS-1#PBF LTC1871IMS-1#TRPBF LTCTV 10-Lead Plastic MSOP –40°C to 125°C

LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC1871EMS-1 LTC1871EMS-1#TR LTCTV 10-Lead Plastic MSOP –40°C to 85°C

LTC1871IMS-1 LTC1871IMS-1#TR LTCTV 10-Lead Plastic MSOP –40°C to 125°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loop

VIN(MIN) Minimum Input Voltage 2.5 V

I-Grade (Note 2) ●2.5 V

IQInput Voltage Supply Current (Note 4)

Continuous Mode VMODE/SYNC = 5V, VFB = 1.4V, VITH = 0.75V 550 1000 µA

VMODE/SYNC = 5V, VFB = 1.4V, VITH = 0.75V,

I-Grade (Note 2)

●550 1000 µA

Burst Mode Operation, No Load VMODE/SYNC = 0V, VITH = 0V (Note 5) 250 500 µA

VMODE/SYNC = 0V, VITH = 0V (Note 5),

I-Grade (Note 2)

●250 500 µA

Shutdown Mode VRUN = 0V 10 20 µA

VRUN = 0V, I-Grade (Note 2) ●10 20 µA

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise speciﬁ ed.

LTC1871-1

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ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise speciﬁ ed.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VRUN+Rising RUN Input Threshold Voltage 1.348 V

VRUN–Falling RUN Input Threshold Voltage

●

1.223

1.198

1.248 1.273

1.298

VRUN(HYST) RUN Pin Input Threshold Hysteresis 50 100 150 mV

I-Grade (Note 2) ●35 100 175 mV

IRUN RUN Input Current 160 nA

VFB Feedback Voltage VITH = 0.4V (Note 5)

●

1.218

1.212

1.230 1.242

1.248

VITH = 0.4V (Note 5), I-Grade (Note 2) ●1.205 1.255 V

IFB FB Pin Input Current VITH = 0.4V (Note 5) 18 60 nA

ΔVFB

ΔVIN

Line Regulation 2.5V ≤ VIN ≤ 30V 0.002 0.02 %/V

2.5V ≤ VIN ≤ 30V, I-Grade (Note 2) ●0.002 0.03 %/V

ΔVFB

ΔVITH

Load Regulation VMODE/SYNC = 0V, VITH = 0.5V to 0.9V (Note 5) ●–1 –0.1 %

VMODE/SYNC = 0V, VITH = 0.5V to 0.9V (Note 5)

I-Grade (Note 2)

●–1 –0.1 %

ΔVFB(OV) ΔFB Pin, Overvoltage Lockout VFB(OV) – VFB(NOM) in Percent 2.5 6 10 %

gmError Ampliﬁ er Transconductance ITH Pin Load = ±5µA (Note 5) 650 µmho

VITH(BURST) Burst Mode Operation ITH Pin Voltage Falling ITH Voltage (Note 5) 195 mV

VSENSE(MAX) Maximum Current Sense Input Threshold Duty Cycle < 20% 120 150 180 mV

Duty Cycle < 20%, I-Grade (Note 2) ●100 200 mV

ISENSE(ON) SENSE Pin Current (GATE High) VSENSE = 0V 35 50 µA

ISENSE(OFF) SENSE Pin Current (GATE Low) VSENSE = 30V 0.1 5 µA

Oscillator

fOSC Oscillator Frequency RFREQ = 80k 250 300 350 kHz

RFREQ = 80k, I-Grade (Note 2) ●250 300 350 kHz

Oscillator Frequency Range 50 1000 kHz

I-Grade (Note 2) ●50 1000 kHz

DMAX Maximum Duty Cycle 87 92 97 %

I-Grade (Note 2) ●87 92 97 %

fSYNC/fOSC Recommended Maximum Synchronized

Frequency Ratio

fOSC = 300kHz (Note 6) 1.25 1.30

fOSC = 300kHz (Note 6), I-Grade (Note 2) ●1.25 1.30

tSYNC(MIN) MODE/SYNC Minimum Input Pulse Width VSYNC = 0V to 5V 25 ns

tSYNC(MAX) MODE/SYNC Maximum Input Pulse Width VSYNC = 0V to 5V 0.8/fOSC ns

VIL(MODE) Low Level MODE/SYNC Input Voltage 0.3 V

I-Grade (Note 2) ●0.3 V

VIH(MODE) High Level MODE/SYNC Input Voltage 1.2 V

I-Grade (Note 2) ●1.2 V

RMODE/SYNC MODE/SYNC Input Pull-Down Resistance 50 k

VFREQ Nominal FREQ Pin Voltage 0.62 V

LTC1871-1

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ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC1871E-1 is guaranteed to meet performance speciﬁ cations

from 0°C to 85°C junction temperature. Speciﬁ cations over the – 40°C

to 85°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC1871I-1 is guaranteed over the full –40°C to 125°C operating junction

temperature range.

Note 3: TJ is calculated from the ambient temperature TA and power

dissipation PD according to the following formula:

J = TA + (PD • 110°C/W)

Note 4: The dynamic input supply current is higher due to power MOSFET

gate charging (QG • fOSC). See Applications Information.

Note 5: The LTC1871-1 is tested in a feedback loop which servos VFB to

the reference voltage with the ITH pin forced to the midpoint of its voltage

range (0.3V ≤ VITH ≤ 1.2V, midpoint = 0.75V).

Note 6: In a synchronized application, the internal slope compensation

gain is increased by 25%. Synchronizing to a signiﬁ cantly higher ratio will

reduce the effective amount of slope compensation, which could result in

subharmonic oscillation for duty cycles greater than 50%.

Note 7: Rise and fall times are measured at 10% and 90% levels.

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise speciﬁ ed.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Low Dropout Regulator

VINTVCC INTVCC Regulator Output Voltage VIN = 7.5V 5.0 5.2 5.4 V

VIN = 7.5V, I-Grade (Note 2) ●5.0 5.2 5.4 V

ΔVINTVCC

ΔVIN1

INTVCC Regulator Line Regulation 7.5V ≤ VIN ≤ 15V 8 25 mV

ΔVINTVCC

ΔVIN2

INTVCC Regulator Line Regulation 15V ≤ VIN ≤ 30V 70 200 mV

VLDO(LOAD) INTVCC Load Regulation 0 ≤ IINTVCC ≤ 20mA, VIN = 7.5V –2 –0.2 %

VDROPOUT INTVCC Regulator Dropout Voltage INTVCC Load = 20mA 280 mV

IINTVCC Bootstrap Mode INTVCC Supply RUN = 0V, SENSE = 5V 10 20 µA

I-Grade (Note 2) ●30 µA

GATE Driver

trGATE Driver Output Rise Time CL = 3300pF (Note 7) 17 100 ns

tfGATE Driver Output Fall Time CL = 3300pF (Note 7) 8 100 ns

TYPICAL PERFORMANCE CHARACTERISTICS

FB Voltage vs Temp FB Voltage Line Regulation FB Pin Current vs Temperature

TEMPERATURE (°C)

–50

FB VOLTAGE (V)

1.23

1.24

150

18711 G01

1.22

1.21 050 100

–25 25 75 125

1.25

VIN (V)

1.229

FB VOLTAGE (V)

1.230

1.231

5101520

18711 G02

25 30 35

TEMPERATURE (°C)

–50

FB PIN CURRENT (nA)

–25 250 50 10075

18711 G03

125 150

LTC1871-1

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TYPICAL PERFORMANCE CHARACTERISTICS

Shutdown Mode IQ vs VIN Shutdown Mode IQ vs Temperature Burst Mode IQ vs VIN

Burst Mode IQ vs Temperature Dynamic IQ vs Frequency

Gate Drive Rise and

Fall Time vs CL

VIN (V)

SHUTDOWN MODE IQ (µA)

10 20 30 40

18711 G04

TEMPERATURE (°C)

–50

SHUTDOWN MODE IQ (µA)

–25 0 25 50

18711 G05

75 100 125 150

VIN = 5V

VIN (V)

Burst Mode IQ (µA)

100

200

300

400

600

10 20

18711 G06

30 40

500

TEMPERATURE (°C)

–50

Burst Mode IQ (µA)

200

500

050 75

18711 G07

100

400

300

–25 25 100 125 150

FREQUENCY (kHz)

IQ (mA)

800

18711 G08

400 1200

600

200 1000

CL = 3300pF

IQ(TOT) = 550µA + Qg • f

CL (pF)

TIME (ns)

2000 4000 6000 8000

18711 G09

10000 12000

RISE TIME

FALL TIME

RUN Thresholds vs VIN RUN Thresholds vs Temperature RT vs Frequency

VIN (V)

1.2

RUN THRESHOLDS (V)

1.3

1.4

10 20 30 40

18711 G10

1.5

TEMPERATURE (°C)

–50

RUN THRESHOLDS (V)

1.30

1.35

150

18711 G11

1.25

1.20 050 100

–25 25 75 125

1.40

FREQUENCY (kHz)

100

RT (kΩ)

300

1000

18711 G12

100

200 1000

900

800700600

500

400

LTC1871-1

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TYPICAL PERFORMANCE CHARACTERISTICS

Frequency vs Temperature

Maximum Sense Threshold

vs Temperature

SENSE Pin Current

vs Temperature

INTVCC Load Regulation INTVCC Line Regulation

INTVCC Dropout Voltage

vs Current, Temperature

RUN (Pin 1): The RUN pin provides the user with an

accurate means for sensing the input voltage and pro-

gramming the start-up threshold for the converter. The

falling RUN pin threshold is nominally 1.248V and the

comparator has 100mV of hysteresis for noise immunity.

When the RUN pin is below this input threshold, the IC

is shut down and the VIN supply current is kept to a low

value (typ 10µA). The Absolute Maximum Rating for the

voltage on this pin is 7V.

ITH (Pin 2): Error Ampliﬁ er Compensation Pin. The

current comparator input threshold increases with this

control voltage. Nominal voltage range for this pin is 0V

to 1.40V.

FB (Pin 3): Receives the feedback voltage from the external

resistor divider across the output. Nominal voltage for

this pin in regulation is 1.230V.

FREQ (Pin 4): A resistor from the FREQ pin to ground

programs the operating frequency of the chip. The nominal

voltage at the FREQ pin is 0.6V.

TEMPERATURE (°C)

–50

275

GATE FREQUENCY (kHz)

280

290

295

300

325

310

050 75

18711 G13

285

315

320

305

–25 25 100 125 150

TEMPERATURE (°C)

–50

140

MAX SENSE THRESHOLD (mV)

145

150

155

160

–25 0 25 50

18711 G14

75 100 125 150

TEMPERATURE (°C)

–50

SENSE PIN CURRENT (µA)

050 75

18711 G15

–25 25 100 125 150

GATE HIGH

VSENSE = 0V

INTVCC LOAD (mA)

INTVCC VOLTAGE (V)

5.2

30 50 80

18711 G16

5.1

5.0

10 20 40 60 70

VIN = 7.5V

VIN (V)

5.1

INTVCC VOLTAGE (V)

5.2

5.3

10 20 30 40

18711 G17

5.4

51525 35

INTVCC LOAD (mA)

DROPOUT VOLTAGE (mV)

150

200

250

500

350

510

18711 G18

100

400

450

300

15 20

150°C

75°C

125°C

25°C

–50°C

0°C

PIN FUNCTIONS

LTC1871-1

18711fb

PIN FUNCTIONS

MODE/SYNC (Pin 5): This input controls the operating

mode of the converter and allows for synchronizing the

operating frequency to an external clock. If the MODE/

SYNC pin is connected to ground, Burst Mode operation

is enabled. If the MODE/SYNC pin is connected to INTVCC,

or if an external logic-level synchronization signal is ap-

plied to this input, Burst Mode operation is disabled and

the IC operates in a continuous mode.

GND (Pin 6): Ground Pin.

GATE (Pin 7): Gate Driver Output.

NTVCC (Pin 8): The Internal 5.20V Regulator Output.

The gate driver and control circuits are powered from

this voltage. Decouple this pin locally to the IC ground

with a minimum of 4.7µF low ESR tantalum or ceramic

capacitor.

VIN (Pin 9): Main Supply Pin. Must be closely decoupled

to ground.

SENSE (Pin 10): The Current Sense Input for the Control

Loop. Connect this pin to the drain of the power MOSFET

for VDS sensing and highest efﬁ ciency. Alternatively, the

SENSE pin may be connected to a resistor in the source

of the power MOSFET. Internal leading edge blanking is

provided for both sensing methods.

BLOCK DIAGRAM

–

1.230V

85mV OV

50k

START-UP

CONTROL

BURST

COMPARATOR

LOGIC

PWM LATCH

CURRENT

COMPARATOR

0.175V

1.230V

5.2V

–

2.00V

1.230V

SLOPE

1.230V

ILOOP

ITH

–

MODE/SYNC

FREQ

INTVCC

8LDO

V-TO-I

OSCV-TO-I

SLOPE

COMPENSATION

BIAS AND

START-UP

CONTROL

VIN

BIAS VREF

IOSC

RLOOP

–

SENSE

GND

18711 BD

GATE

INTVCC

GND

VIN

1.248V

RUN

0.6V

LTC1871-1

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OPERATION

Figure 2. Using the SENSE Pin On the LTC1871-1

Main Control Loop

The LTC1871-1 is a constant frequency, current mode

controller for DC/DC boost, SEPIC and ﬂ yback converter

applications. The LTC1871-1 is distinguished from con-

ventional current mode controllers because the current

control loop can be closed by sensing the voltage drop

across the power MOSFET switch instead of across a

discrete sense resistor, as shown in Figure 2. This sensing

technique improves efﬁ ciency, increases power density,

and reduces the cost of the overall solution.

which causes the current comparator C1 to trip at a higher

peak inductor current value. The average inductor current

will therefore rise until it equals the load current, thereby

maintaining output regulation.

The nominal operating frequency of the LTC1871-1 is

programmed using a resistor from the FREQ pin to ground

and can be controlled over a 50kHz to 1000kHz range. In

addition, the internal oscillator can be synchronized to

an external clock applied to the MODE/SYNC pin and can

be locked to a frequency between 100% and 130% of its

nominal value. When the MODE/SYNC pin is left open, it

is pulled low by an internal 50k resistor and Burst Mode

operation is enabled. If this pin is taken above 2V or an

external clock is applied, Burst Mode operation is disabled

and the IC operates in continuous mode. With no load (or

an extremely light load), the controller will skip pulses in

order to maintain regulation and prevent excessive output

ripple.

The RUN pin controls whether the IC is enabled or is in a low

current shutdown state. A micropower 1.248V reference

and comparator C2 allow the user to program the supply

voltage at which the IC turns on and off (comparator C2

has 100mV of hysteresis for noise immunity). With the

RUN pin below 1.248V, the chip is off and the input supply

current is typically only 10µA.

An overvoltage comparator OV senses when the FB pin

exceeds the reference voltage by 6.5% and provides a

reset pulse to the main RS latch. Because this RS latch is

reset-dominant, the power MOSFET is actively held off for

the duration of an output overvoltage condition.

The LTC1871-1 can be used either by sensing the voltage

drop across the power MOSFET or by connecting the

SENSE pin to a conventional shunt resistor in the source

of the power MOSFET, as shown in Figure 2. Sensing the

voltage across the power MOSFET maximizes converter

efﬁ ciency and minimizes the component count, but limits

the output voltage to the maximum rating for this pin (36V).

By connecting the SENSE pin to a resistor in the source

of the power MOSFET, the user is able to program output

voltages signiﬁ cantly greater than 36V.

COUT

VSW

2a. SENSE Pin Connection for

Maximum Efﬁciency (VSW < 36V)

VOUT

VIN

GND

COUT

18711 F02

2b. SENSE Pin Connection for Precise

Control of Peak Current or for VSW > 36V

VOUT

VIN

GND

GATE

GND

VIN

SENSE

GATE

GND

VIN

SENSE

For circuit operation, please refer to the Block Diagram of

the IC and Figure 1. In normal operation, the power MOSFET

is turned on when the oscillator sets the PWM latch and

is turned off when the current comparator C1 resets the

latch. The divided-down output voltage is compared to an

internal 1.230V reference by the error ampliﬁ er EA, which

outputs an error signal at the ITH pin. The voltage on the

ITH pin sets the current comparator C1 input threshold.

When the load current increases, a fall in the FB voltage

relative to the reference voltage causes the ITH pin to rise,

LTC1871-1

18711fb

OPERATION

MOSFET RDS(ON). If the ITH pin drops below 0.175V, the

Burst Mode comparator B1 will turn off the power MOSFET

and scale back the quiescent current of the IC to 250µA

(sleep mode). In this condition, the load current will be

supplied by the output capacitor until the ITH voltage rises

above the 50mV hysteresis of the burst comparator. At

light loads, short bursts of switching (where the average

inductor current is 20% of its maximum value) followed

by long periods of sleep will be observed, thereby greatly

improving converter efﬁ ciency. Oscilloscope waveforms

illustrating Burst Mode operation are shown in Figure 3.

Pulse-Skip Mode Operation

With the MODE/SYNC pin tied to a DC voltage above 2V,

Burst Mode operation is disabled. The internal, 0.525V

buffered ITH burst clamp is removed, allowing the ITH

pin to directly control the current comparator from no

load to full load. With no load, the ITH pin is driven below

0.175V, the power MOSFET is turned off and sleep mode

is invoked. Oscilloscope waveforms illustrating this mode

of operation are shown in Figure 4.

When an external clock signal drives the MODE/SYNC

pin at a rate faster than the chip’s internal oscillator, the

oscillator will synchronize to it. In this synchronized mode,

Burst Mode operation is disabled. The constant frequency

associated with synchronized operation provides a more

controlled noise spectrum from the converter, at the ex-

pense of overall system efﬁ ciency of light loads.

Programming the Operating Mode

For applications where maximizing the efﬁ ciency at very

light loads (e.g., <100µA) is a high priority, the current

in the output divider could be decreased to a few micro-

amps and Burst Mode operation should be applied (i.e.,

the MODE/SYNC pin should be connected to ground).

In applications where ﬁ xed frequency operation is more

critical than low current efﬁ ciency, or where the lowest

output ripple is desired, pulse-skip mode operation should

be used and the MODE/SYNC pin should be connected

to the INTVCC pin. This allows discontinuous conduction

mode (DCM) operation down to near the limit deﬁ ned

by the chip’s minimum on-time (about 175ns). Below

this output current level, the converter will begin to skip

cycles in order to maintain output regulation. Figures 3

and 4 show the light load switching waveforms for Burst

Mode and pulse-skip mode operation for the converter

in Figure 1.

Burst Mode Operation

Burst Mode operation is selected by leaving the MODE/

SYNC pin unconnected or by connecting it to ground. In

normal operation, the range on the ITH pin corresponding to

no load to full load is 0.30V to 1.2V. In Burst Mode opera-

tion, if the error ampliﬁ er EA drives the ITH voltage below

0.525V, the buffered ITH input to the current comparator

C1 will be clamped at 0.525V (which corresponds to 25%

of maximum load current). The inductor current peak is

then held at approximately 30mV divided by the power

Figure 3. LTC1871-1 Burst Mode Operation

(MODE/SYNC = 0V) at Low Output Current

Figure 4. LTC1871-1 Low Output Current Operation with

Burst Mode Operation Disabled (MODE/SYNC = INTVCC)

VOUT

50mV/DIV

5A/DIV

10µs/DIV 18711 F03

VIN = 3.3V

VOUT = 5V

IOUT = 500mA

MODE/SYNC = 0V

(Burst Mode OPERATION)

VOUT

50mV/DIV

5A/DIV

2µs/DIV 18711 F04

VIN = 3.3V

VOUT = 5V

IOUT = 500mA

MODE/SYNC = INTVCC

(PULSE-SKIP MODE)

LTC1871-1

18711fb

When the oscillator’s internal logic circuitry detects a

synchronizing signal on the MODE/SYNC pin, the in-

ternal oscillator ramp is terminated early and the slope

compensation is increased by approximately 30%. As

a result, in applications requiring synchronization, it is

recommended that the nominal operating frequency of

the IC be programmed to be about 75% of the external

clock frequency. Attempting to synchronize to too high an

external frequency (above 1.3fO) can result in inadequate

slope compensation and possible subharmonic oscillation

(or jitter).

The external clock signal must exceed 2V for at least 25ns,

and should have a maximum duty cycle of 80%, as shown

in Figure 5. The MOSFET turn on will synchronize to the

rising edge of the external clock signal.

0.6V, and the current that ﬂ ows into the FREQ pin is used

to charge and discharge an internal oscillator capacitor. A

graph for selecting the value of RT for a given operating

frequency is shown in Figure 6.

APPLICATIONS INFORMATION

Figure 5. MODE/SYNC Clock Input and Switching

Waveforms for Synchronized Operation

Figure 6. Timing Resistor (RT) Value

18711 F05

2V TO 7V

MODE/

SYNC

GATE

tMIN = 25ns

0.8T

D = 40%

T T = 1/fO

Programming the Operating Frequency

The choice of operating frequency and inductor value is

a tradeoff between efﬁ ciency and component size. Low

frequency operation improves efﬁ ciency by reducing

MOSFET and diode switching losses. However, lower

frequency operation requires more inductance for a given

amount of load current.

The LTC1871-1 uses a constant frequency architecture that

can be programmed over a 50kHz to 1000kHz range with

a single external resistor from the FREQ pin to ground, as

shown in Figure 1. The nominal voltage on the FREQ pin is

FREQUENCY (kHz)

100

RT (kΩ)

300

1000

18711 F06

100

200 1000

900

800700600

500

400

INTVCC Regulator Bypassing and Operation

An internal, P-channel low dropout voltage regulator pro-

duces the 5.2V supply which powers the gate driver and

logic circuitry within the LTC1871-1, as shown in Figure 7.

The INTVCC regulator can supply up to 50mA and must be

bypassed to ground immediately adjacent to the IC pins

with a minimum of 4.7µF tantalum or ceramic capacitor.

Good bypassing is necessary to supply the high transient

currents required by the MOSFET gate driver.

For input voltages that don’t exceed 7V (the absolute

maximum rating for this pin), the internal low dropout

regulator in the LTC1871-1 is redundant and the INTVCC

pin can be shorted directly to the VIN pin. With the INTVCC

pin shorted to VIN, however, the divider that programs the

regulated INTVCC voltage will draw 10µA of current from

the input supply, even in shutdown mode. For applications

that require the lowest shutdown mode input supply cur-

rent, do not connect the INTVCC pin to VIN. Regardless of

whether the INTVCC pin is shorted to VIN or not, it is always

necessary to have the driver circuitry bypassed with a

4.7μF tantalum or low ESR ceramic capacitor to ground

immediately adjacent to the INTVCC and GND pins.

In an actual application, most of the IC supply current is

used to drive the gate capacitance of the power MOSFET.

LTC1871-1

18711fb

APPLICATIONS INFORMATION

Figure 7. Bypassing the LDO Regulator and Gate Driver Supply

–

1.230V

R2 R1

P-CH

5.2V

DRIVER GATE

CVCC

4.7µF

CIN

INPUT

SUPPLY

2.5V TO 30V

GND

PLACE AS CLOSE AS

POSSIBLE TO DEVICE PINS

18711 F07

INTVCC

VIN

GND

LOGIC

As a result, high input voltage applications in which a

large power MOSFET is being driven at high frequencies

can cause the LTC1871-1 to exceed its maximum junc-

tion temperature rating. The junction temperature can be

estimated using the following equations:

Q(TOT) ≈ IQ + f • QG

IC = VIN • (IQ + f • QG)

J = TA + PIC • RTH(JA)

The total quiescent current IQ(TOT) consists of the static

supply current (IQ) and the current required to charge and

discharge the gate of the power MOSFET. The 10-pin MSOP

package has a thermal resistance of RTH(JA) = 120°C/W.

As an example, consider a power supply with VIN = 5V and

VO = 12V at IO = 1A. The switching frequency is 500kHz,

and the maximum ambient temperature is 70°C. The power

MOSFET chosen is the IRF7805, which has a maximum

RDS(ON) of 11m (at room temperature) and a maximum

total gate charge of 37nC (the temperature coefﬁ cient of

the gate charge is low).

Q(TOT) = 600µA + 37nC • 500kHz = 19.1mA

IC = 5V • 19.1mA = 95mW

J = 70°C + 120°C/W • 95mW = 81.4°C

This demonstrates how signiﬁ cant the gate charge current

can be when compared to the static quiescent current in

the IC.

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked when

operating in a continuous mode at high VIN. A tradeoff

between the operating frequency and the size of the power

MOSFET may need to be made in order to maintain a reliable

IC junction temperature. Prior to lowering the operating

frequency, however, be sure to check with power MOSFET

manufacturers for their latest-and-greatest low QG, low

RDS(ON) devices. Power MOSFET manufacturing tech-

nologies are continually improving, with newer and better

performance devices being introduced almost yearly.

Output Voltage Programming

The output voltage is set by a resistor divider according

to the following formula:

VO=1.230V • 1+R2











The external resistor divider is connected to the output

as shown in Figure 1, allowing remote voltage sensing.

The resistors R1 and R2 are typically chosen so that the

LTC1871-1

18711fb

APPLICATIONS INFORMATION

error caused by the current ﬂ owing into the FB pin dur-

ing normal operation is less than 1% (this translates to a

maximum value of R1 of about 250k).

Programming Turn-On and Turn-Off Thresholds

with the RUN Pin

The LTC1871-1 contains an independent, micropower volt-

age reference and comparator detection circuit that remains

active even when the device is shut down, as shown in

Figure 8. This allows users to accurately program an input

voltage at which the converter will turn on and off. The

falling threshold voltage on the RUN pin is equal to the

internal reference voltage of 1.248V. The comparator has

100mV of hysteresis to increase noise immunity.

The turn-on and turn-off input voltage thresholds are

programmed using a resistor divider according to the

following formulas:

VIN(OFF) =1.248V • 1+R2











VIN(ON) =1.348V • 1+R2











The resistor R1 is typically chosen to be less than 1M.

For applications where the RUN pin is only to be used as

a logic input, the user should be aware of the 7V Absolute

Maximum Rating for this pin! The RUN pin can be con-

nected to the input voltage through an external 1M resistor,

as shown in Figure 8c, for “always on” operation.

Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin

Figure 8c. External Pull-Up Resistor On

RUN Pin for “Always On” Operation

Figure 8b. On/Off Control Using External Logic

–

RUN

COMPARATOR

VIN

RUN

INPUT

SUPPLY OPTIONAL

FILTER

CAPACITOR

–GND

18711 F8a

BIAS AND

START-UP

CONTROL

1.248V

µPOWER

REFERENCE

–

RUN

COMPARATOR

1.248V

18711 F08b

RUN

EXTERNAL

LOGIC CONTROL

–

RUN

COMPARATOR

VIN

RUN

INPUT

SUPPLY

–GND 1.248V

18711 F08c

LTC1871-1

18711fb

APPLICATIONS INFORMATION

Application Circuits

A basic LTC1871-1 application circuit is shown in

Figure 1. External component selection is driven by the

characteristics of the load and the input supply. The

ﬁ rst topology to be analyzed will be the boost converter,

followed by SEPIC (single ended primary inductance

converter).

Boost Converter: Duty Cycle Considerations

For a boost converter operating in a continuous conduction

mode (CCM), the duty cycle of the main switch is:

D=VO+VD–V

VO+VD











where VD is the forward voltage of the boost diode. For

converters where the input voltage is close to the output

voltage, the duty cycle is low and for converters that develop

a high output voltage from a low voltage input supply,

the duty cycle is high. The maximum output voltage for a

boost converter operating in CCM is:

VO(MAX) =VIN(MIN)

1–DMAX

( )

–V

The maximum duty cycle capability of the LTC1871-1 is

typically 92%. This allows the user to obtain high output

voltages from low input supply voltages.

Boost Converter: The Peak and Average Input Currents

The control circuit in the LTC1871-1 is measuring the input

current (either by using the RDS(ON) of the power MOSFET

or by using a sense resistor in the MOSFET source), so

the output current needs to be reﬂ ected back to the input

in order to dimension the power MOSFET properly. Based

on the fact that, ideally, the output power is equal to the

input power, the maximum average input current is:

IIN(MAX) =IO(MAX)

1–DMAX

The peak input current is:

IIN(PEAK) =1+









•IO(MAX)

1–DMAX

The maximum duty cycle, DMAX, should be calculated at

minimum VIN.

Boost Converter: Ripple Current ΔIL and the ‘χ’ Factor

The constant ‘χ’ in the equation above represents the

percentage peak-to-peak ripple current in the inductor,

relative to its maximum value. For example, if 30% ripple

current is chosen, then χ = 0.30, and the peak current is

15% greater than the average.

For a current mode boost regulator operating in CCM,

slope compensation must be added for duty cycles above

50% in order to avoid subharmonic oscillation. For the

LTC1871-1, this ramp compensation is internal. Having an

internally ﬁ xed ramp compensation waveform, however,

does place some constraints on the value of the inductor

and the operating frequency. If too large an inductor is

used, the resulting current ramp (ΔIL) will be small relative

to the internal ramp compensation (at duty cycles above

50%), and the converter operation will approach voltage

mode (ramp compensation reduces the gain of the current

loop). If too small an inductor is used, but the converter

is still operating in CCM (near critical conduction mode),

the internal ramp compensation may be inadequate to

prevent subharmonic oscillation. To ensure good current

mode gain and avoid subharmonic oscillation, it is recom-

mended that the ripple current in the inductor fall in the

range of 20% to 40% of the maximum average current.

For example, if the maximum average input current is

1A, choose a ΔIL between 0.2A and 0.4A, and a value ‘χ’

between 0.2 and 0.4.

Boost Converter: Inductor Selection

Given an operating input voltage range, and having chosen

the operating frequency and ripple current in the inductor,

the inductor value can be determined using the following

equation:

L=VIN(MIN)

IL• f •D

MAX

where:

IL=•IO(MAX)

1–DMAX

LTC1871-1

18711fb

APPLICATIONS INFORMATION

Figure 9. Discontinuous Mode Waveforms

Remember that boost converters are not short-circuit

protected. Under a shorted output condition, the inductor

current is limited only by the input supply capability. For

applications requiring a step-up converter that is short-

circuit protected, please refer to the applications section

covering SEPIC converters.

The minimum required saturation current of the inductor

can be expressed as a function of the duty cycle and the

load current, as follows:

IL(SAT) 1+









•IO(MAX)

1–DMAX

The saturation current rating for the inductor should be

checked at the minimum input voltage (which results

in the highest inductor current) and maximum output

current.

Boost Converter: Operating in Discontinuous Mode

Discontinuous mode operation occurs when the load cur-

rent is low enough to allow the inductor current to run out

during the off-time of the switch, as shown in Figure 9.

Once the inductor current is near zero, the switch and diode

capacitances resonate with the inductance to form damped

ringing at 1MHz to 10MHz. If the off-time is long enough,

the drain voltage will settle to the input voltage.

Depending on the input voltage and the residual energy

in the inductor, this ringing can cause the drain of the

power MOSFET to go below ground where it is clamped

by the body diode. This ringing is not harmful to the IC

and it has not been shown to contribute signiﬁ cantly to

EMI. Any attempt to damp it with a snubber will degrade

the efﬁ ciency.

MOSFET DRAIN

VOLTAGE

2V/DIV

INDUCTOR

CURRENT

2A/DIV

2µs/DIV 18711 F09

VIN = 3.3V IOUT = 200mA

VOUT = 5V

Boost Converter: Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. High efﬁ ciency converters generally cannot

afford the core loss found in low cost powdered iron cores,

forcing the use of more expensive ferrite, molypermalloy

or Kool Mµ

cores. Actual core loss is independent of core

size for a ﬁ xed inductor value, but is very dependent on

the inductance selected. As inductance increases, core

losses go down. Unfortunately, increased inductance

requires more turns of wire and therefore, copper losses

will increase. Generally, there is a tradeoff between core

losses and copper losses that needs to be balanced.

Ferrite designs have very low core losses and are pre-

ferred at high switching frequencies, so design goals can

concentrate on copper losses and preventing saturation.

Ferrite core material saturates “hard,” meaning that the

inductance collapses rapidly when the peak design current

is exceeded. This results in an abrupt increase in inductor

ripple current and consequently, output voltage ripple. Do

not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good,

low cost core material for toroids, but is more expensive

than ferrite. A reasonable compromise from the same

manufacturer is Kool Mµ.

Boost Converter: Power MOSFET Selection

The power MOSFET serves two purposes in the LTC1871-1:

it represents the main switching element in the power path,

and its RDS(ON) represents the current sensing element

for the control loop. Important parameters for the power

MOSFET include the drain-to-source breakdown voltage

(BVDSS), the threshold voltage (VGS(TH)), the on-resistance

(RDS(ON)) versus gate-to-source voltage, the gate-to-source

and gate-to-drain charges (QGS and QGD, respectively),

the maximum drain current (ID(MAX)) and the MOSFET’s

thermal resistances (RTH(JC) and RTH(JA)).

The gate drive voltage is set by the 5.2V INTVCC low drop

regulator. Consequently, logic-level threshold MOSFETs

should be used in most LTC1871-1 applications. If low

input voltage operation is expected (e.g., supplying power

LTC1871-1

18711fb

APPLICATIONS INFORMATION

DUTY CYCLE

MAXIMUM CURRENT SENSE VOLTAGE (mV)

100

150

0.8

18711 F10

00.2 0.4 0.5 1.0

200

Figure 10. Maximum SENSE Threshold Voltage vs Duty Cycle

from a lithium-ion battery or a 3.3V logic supply), then

sublogic-level threshold MOSFETs should be used.

Pay close attention to the BVDSS speciﬁ cations for the

MOSFETs relative to the maximum actual switch voltage in

the application. Many logic-level devices are limited to 30V

or less, and the switch node can ring during the turn-off of

the MOSFET due to layout parasitics. Check the switching

waveforms of the MOSFET directly across the drain and

source terminals using the actual PC board layout (not

just on a lab breadboard!) for excessive ringing.

During the switch on-time, the control circuit limits the

maximum voltage drop across the power MOSFET to about

150mV (at low duty cycle). The peak inductor current

is therefore limited to 150mV/RDS(ON). The relationship

between the maximum load current, duty cycle and the

RDS(ON) of the power MOSFET is:

RDS(ON) VSENSE(MAX) •1–DMAX

1+









•I

O(MAX) •T

The VSENSE(MAX) term is typically 150mV at low duty

cycle, and is reduced to about 100mV at a duty cycle of

92% due to slope compensation, as shown in Figure 10.

The ρT term accounts for the temperature coefﬁ cient of

the RDS(ON) of the MOSFET, which is typically 0.4%/°C.

Figure 11 illustrates the variation of normalized RDS(ON)

over tempera

ture for a typical power MOSFET.

Another method of choosing which power MOSFET to

use is to check what the maximum output current is for a

given RDS(ON), since MOSFET on-resistances are available

in discrete values.

IO(MAX) =VSENSE(MAX) •1–DMAX

1+









•RDS(ON) •T

It is worth noting that the 1 – DMAX relationship between

IO(MAX) and RDS(ON) can cause boost converters with a

wide input range to experience a dramatic range of maxi-

mum input and output current. This should be taken into

consideration in applications where it is important to limit

the maximum current drawn from the input supply.

Calculating Power MOSFET Switching and Conduction

Losses and Junction Temperatures

In order to calculate the junction temperature of the

power MOSFET, the power dissipated by the device must

be known. This power dissipation is a function of the

duty cycle, the load current and the junction temperature

itself (due to the positive temperature coefﬁ cient of its

RDS(ON)). As a result, some iterative calculation is normally

required to determine a reasonably accurate value. Since

the con

troller is using the MOSFET as both a switching

and a sensing element, care should be taken to ensure

that the converter is capable of delivering the required

load current over all operating conditions (line voltage

and temperature), and for the worst-case speciﬁ cations

JUNCTION TEMPERATURE (°C)

–50

ρT NORMALIZED ON RESISTANCE

1.0

1.5

150

18711 F11

0.5

0050 100

2.0

Figure 11. Normalized RDS(ON) vs Temperature

LTC1871-1

18711fb

APPLICATIONS INFORMATION

for VSENSE(MAX) and the RDS(ON) of the MOSFET listed in

the manufacturer’s data sheet.

The power dissipated by the MOSFET in a boost converter

is:

FET

O(MAX)

1–D

MAX











•R

DS(ON)

•D

MAX

•

+k•V

O1.85

•I

O(MAX)

1–D

MAX

( )

•C

RSS

•f

The ﬁ rst term in the equation above represents the I2R

losses in the device, and the second term, the switching

losses. The constant, k = 1.7, is an empirical factor inversely

related to the gate drive current and has the dimension

of 1/current.

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

J = TA + PFET • RTH(JA)

The RTH(JA) to be used in this equation normally includes

the RTH(JC) for the device plus the thermal resistance from

the case to the ambient temperature (RTH(CA)). This value

of TJ can then be compared to the original, assumed value

used in the iterative calculation process.

Boost Converter: Output Diode Selection

To maximize efﬁ ciency, a fast switching diode with low

forward drop and low reverse leakage is desired. The output

diode in a boost converter conducts current during the

switch off-time. The peak reverse voltage that the diode

must withstand is equal to the regulator output voltage.

The average forward current in normal operation is equal

to the output current, and the peak current is equal to the

peak inductor current.

ID(PEAK) =IL(PEAK) =1+









•IO(MAX)

1–DMAX

The power dissipated by the diode is:

D = IO(MAX) • VD

and the diode junction temperature is:

J = TA + PD • RTH(JA)

The RTH(JA) to be used in this equation normally includes

the RTH(JC) for the device plus the thermal resistance from

the board to the ambient temperature in the enclosure.

Remember to keep the diode lead lengths short and to

observe proper switch-node layout (see Board Layout

Checklist) to avoid excessive ringing and increased

dissipation.

Boost Converter: Output Capacitor Selection

Contributions of ESR (equivalent series resistance), ESL

(equivalent series inductance) and the bulk capacitance

must be considered when choosing the correct component

for a given output ripple voltage. The effects of these three

parameters (ESR, ESL and bulk C) on the output voltage

ripple waveform are illustrated in Figure 12e for a typical

boost converter.

The choice of component(s) begins with the maximum

acceptable ripple voltage (expressed as a percentage of

the output voltage), and how this ripple should be divided

between the ESR step and the charging/discharging

For the purpose of simplicity we will choose 2% for the

maximum output ripple, to be divided equally between the

ESR step and the charging/discharging

V. This percent-

age ripple will change, depending on the requirements

of the application, and the equations provided below can

easily be modiﬁ ed.

For a 1% contribution to the total ripple voltage, the ESR

of the output capacitor can be determined using the fol-

lowing equation:

ESRCOUT 0.01• VO

IIN(PEAK)

where:

IIN(PEAK)=1+









•IO(MAX)

1–DMAX

For the bulk C component, which also contributes 1% to

the total ripple:

COUT IO(MAX)

0.01• VO• f

LTC1871-1

18711fb

APPLICATIONS INFORMATION

For many designs it is possible to choose a single capacitor

type that satisﬁ es both the ESR and bulk C requirements

for the design. In certain demanding applications, however,

the ripple voltage can be improved signiﬁ cantly by con-

necting two or more types of capacitors in parallel. For

example, using a low ESR ceramic capacitor can minimize

the ESR step, while an electrolytic capacitor can be used

to supply the required bulk C.

Once the output capacitor ESR and bulk capacitance have

been determined, the overall ripple voltage waveform

should be veriﬁ ed on a dedicated PC board (see Board

Layout section for more information on component place-

ment). Lab breadboards generally suffer from excessive

series inductance (due to inter-component wiring), and

these parasitics can make the switching waveforms look

signiﬁ cantly worse than they would be on a properly

designed PC board.

The output capacitor in a boost regulator experiences high

RMS ripple currents, as shown in Figure 12. The RMS

output capacitor ripple current is:

IRMS(COUT) IO(MAX) •VO–V

IN(MIN)

VIN(MIN)

Note that the ripple current ratings from capacitor manu-

facturers are often based on only 2000 hours of life. This

makes it advisable to further derate the capacitor or to

choose a capacitor rated at a higher temperature than

required. Several capacitors may also be placed in parallel

to meet size or height requirements in the design.

Manufacturers such as Nichicon, United Chemicon and

Sanyo should be considered for high performance through-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest product of

ESR and size of any aluminum electrolytic, at a somewhat

higher price.

In surface mount applications, multiple capacitors may

have to be placed in parallel in order to meet the ESR or

RMS current handling requirements of the application.

Aluminum electrolytic and dry tantalum capacitors are

both available in surface mount packages. In the case of

tantalum, it is critical that the capacitors have been surge

tested for use in switching power supplies. An excellent

choice is AVX TPS series of surface mount tantalum. Also,

ceramic capacitors are now available with extremely low

ESR, ESL and high ripple current ratings.

Boost Converter: Input Capacitor Selection

The input capacitor of a boost converter is less critical

than the output capacitor, due to the fact that the inductor

is in series with the input and the input current waveform

is continuous (see Figure 12b). The input voltage source

impedance determines the size of the input capacitor,

VIN

12a. Circuit Diagram

12b. Inductor and Input Currents

COUT

VOUT

IIN

12c. Switch Current

ISW

tON

12d. Diode and Output Currents

12e. Output Voltage Ripple Waveform

VOUT

(AC)

tOFF

ΔVESR

RINGING DUE TO

TOTAL INDUCTANCE

(BOARD + CAP)

ΔVCOUT

Figure 12. Switching Waveforms for a Boost Converter

LTC1871-1

18711fb

APPLICATIONS INFORMATION

Table 1. Recommended Component Manufacturers

VENDOR COMPONENTS TELEPHONE WEB ADDRESS

AVX Capacitors (207) 282-5111 avxcorp.com

BH Electronics Inductors, Transformers (952) 894-9590 bhelectronics.com

Coilcraft Inductors (847) 639-6400 coilcraft.com

Coiltronics Inductors (407) 241-7876 coiltronics.com

Diodes, Inc Diodes (805) 446-4800 diodes.com

Fairchild MOSFETs (408) 822-2126 fairchildsemi.com

General Semiconductor Diodes (516) 847-3000 generalsemiconductor.com

International Rectiﬁ er MOSFETs, Diodes (310) 322-3331 irf.com

IRC Sense Resistors (361) 992-7900 irctt.com

Kemet Tantalum Capacitors (408) 986-0424 kemet.com

Magnetics Inc Toroid Cores (800) 245-3984 mag-inc.com

Microsemi Diodes (617) 926-0404 microsemi.com

Murata-Erie Inductors, Capacitors (770) 436-1300 murata.co.jp

Nichicon Capacitors (847) 843-7500 nichicon.com

On Semiconductor Diodes (602) 244-6600 onsemi.com

Panasonic Capacitors (714) 373-7334 panasonic.com

Sanyo Capacitors (619) 661-6835 sanyo.co.jp

Sumida Inductors (847) 956-0667 sumida.com

Taiyo Yuden Capacitors (408) 573-4150 t-yuden.com

TDK Capacitors, Inductors (562) 596-1212 component.tdk.com

Thermalloy Heat Sinks (972) 243-4321 aavidthermalloy.com

Tokin Capacitors (408) 432-8020 nec-tokinamerica.com

Toko Inductors (847) 699-3430 tokoam.com

United Chemicon Capacitors (847) 696-2000 chemi-com.com

Vishay/Dale Resistors (605) 665-9301 vishay.com

Vishay/Siliconix MOSFETs (800) 554-5565 vishay.com

Vishay/Sprague Capacitors (207) 324-4140 vishay.com

Zetex Small-Signal Discretes (631) 543-7100 zetex.com

which is typically in the range of 10µF to 100µF. A low ESR

capacitor is recommended, although it is not as critical as

for the output capacitor.

The RMS input capacitor ripple current for a boost con-

verter is:

IRMS(CIN) =0.3 • VIN(MIN)

L•f•D

MAX

Please note that the input capacitor can see a very high

surge current when a battery is suddenly connected to

the input of the converter and solid tantalum capacitors

can fail catastrophically under these conditions. Be sure

to specify surge-tested capacitors!

Burst Mode Operation and Considerations

The choice of MOSFET RDS(ON) and inductor value also

determines the load current at which the LTC1871-1 en-

ters Burst Mode operation. When bursting, the controller

clamps the peak inductor current to approximately:

IBURST(PEAK) =30mV

RDS(ON)

which represents about 20% of the maximum 150mV

SENSE pin voltage. The corresponding average current

depends upon the amount of ripple current. Lower inductor

values (higher ΔIL) will reduce the load current at which

LTC1871-1

18711fb

APPLICATIONS INFORMATION

Burst Mode operations begins, since it is the peak current

that is being clamped.

The output voltage ripple can increase during Burst Mode

operation if ΔIL is substantially less than IBURST

. This can

occur if the input voltage is very low or if a very large

inductor is chosen. At high duty cycles, a skipped cycle

causes the inductor current to quickly decay to zero.

However, because ΔIL is small, it takes multiple cycles

for the current to ramp back up to IBURST(PEAK). Dur-

ing this inductor charging interval, the output capacitor

must supply the load current and a signiﬁ cant droop in

the output voltage can occur. Generally, it is a good idea

to choose a value of inductor ΔIL between 25% and 40%

of IIN(MAX). The alternative is to either increase the value

of the output capacitor or disable Burst Mode operation

using the MODE/SYNC pin.

Burst Mode operation can be defeated by connecting the

MODE/SYNC pin to a high logic-level voltage (either with

a control input or by connecting this pin to INTVCC). In

this mode, the burst clamp is removed, and the chip can

operate at constant frequency from continuous conduction

mode (CCM) at full load, down into deep discontinuous

conduction mode (DCM) at light load. Prior to skipping

pulses at very light load (i.e., < 5% of full load), the

controller will operate with a minimum switch on-time

in DCM. Pulse skipping prevents a loss of control of

the output at very light loads and reduces output volt-

age ripple.

Efﬁ ciency Considerations: How Much Does VDS

Sensing Help?

The efﬁ ciency of a switching regulator is equal to the

output power divided by the input power (×100%).

Percent efﬁ ciency can be expressed as:

% Efﬁ ciency = 100% – (L1 + L2 + L3 + …),

where L1, L2, etc. are the individual loss components

as a percentage of the input power. It is often useful to

analyze individual losses to determine what is limiting

the efﬁ ciency and which change would produce the most

improvement. Although all dissipative elements in the

circuit produce losses, four main sources usually account

for the majority of the losses in LTC1871-1 applica-

tion circuits:

1. The supply current into VIN. The VIN current is the

sum of the DC supply current IQ (given in the Electrical

Characteristics) and the MOSFET driver and control

currents. The DC supply current into the VIN pin is typi-

cally about 550µA and represents a small power loss

(much less than 1%) that increases with VIN. The driver

current results from switching the gate capacitance

of the power MOSFET; this current is typically much

larger than the DC current. Each time the MOSFET is

switched on and then off, a packet of gate charge QG

is transferred from INTVCC to ground. The resulting

dQ/dt is a current that must be supplied to the INTVCC

capacitor through the VIN pin by an external supply. If

the IC is operating in CCM:

Q(TOT) ≈ IQ = f • QG

IC = VIN • (IQ + f • QG)

2. Power MOSFET switching and conduction losses. The

technique of using the voltage drop across the power

MOSFET to close the current feedback loop was chosen

because of the increased efﬁ ciency that results from

not having a sense resistor. The losses in the power

MOSFET are equal to:

FET

O(MAX)

1–D

MAX











•R

DS(ON)

•D

MAX

•

+k•V

O1.85

•I

O(MAX)

1–D

MAX

( )

•C

RSS

•f

The I2R power savings that result from not having a

discrete sense resistor can be calculated almost by

inspection.

R(SENSE) =IO(MAX)

1–DMAX











•RSENSE •D

MAX

To understand the magnitude of the improvement with

this VDS sensing technique, consider the 3.3V input,

5V output power supply shown in Figure 1. The maxi-

mum load current is 7A (10A peak) and the duty cycle

is 39%. Assuming a ripple current of 40%, the peak

inductor current is 13.8A and the average is 11.5A.

With a maximum sense voltage of about 140mV, the

sense resistor value would be 10m, and the power

LTC1871-1

18711fb

APPLICATIONS INFORMATION

Figure 13. Load Transient Response for a 3.3V Input,

5V Output Boost Converter Application, 0.7A to 7A Step

dissipated in this resistor would be 514mW at maxi-

mum output current. Assuming an efﬁ ciency of 90%,

this sense resistor power dissipation represents 1.3%

of the overall input power. In other words, for this ap-

plication, the use of VDS sensing would increase the

efﬁ ciency by approximately 1.3%.

For more details regarding the various terms in these

equations, please refer to the section Boost Converter:

Power MOSFET Selection.

3. The losses in the inductor are simply the DC input cur-

rent squared times the winding resistance. Expressing

this loss as a function of the output current yields:

R(WINDING) =IO(MAX)

1–DMAX











•RW

4. Losses in the boost diode. The power dissipation in the

boost diode is:

DIODE = IO(MAX) • VD

The boost diode can be a major source of power loss

in a boost converter. For the 3.3V input, 5V output at

7A example given above, a Schottky diode with a 0.4V

forward voltage would dissipate 2.8W, which represents

7% of the input power. Diode losses can become signiﬁ -

cant at low output voltages where the forward voltage

is a signiﬁ cant percentage of the output voltage.

5. Other losses, including CIN and CO ESR dissipation and

inductor core losses, generally account for less than

2% of the total additional loss.

Checking Transient Response

The regulator loop response can be veriﬁ ed by looking at

the load transient response. Switching regulators generally

take several cycles to respond to an instantaneous step

in resistive load current. When the load step occurs, VO

immediately shifts by an amount equal to (ΔILOAD)(ESR),

and then CO begins to charge or discharge (depending on

the direction of the load step) as shown in Figure 13. The

regulator feedback loop acts on the resulting error amp

output signal to return VO to its steady-state value. During

this recovery time, VO can be monitored for overshoot or

ringing that would indicate a stability problem.

IOUT

2V/DIV

VOUT (AC)

100mV/DIV

100µs/DIV 18711 F13

VIN = 3.3V

VOUT = 5V

MODE/SYNC = INTVCC

(PULSE-SKIP MODE)

A second, more severe transient can occur when con-

necting loads with large (>1µF) supply bypass capacitors.

The discharged bypass capacitors are effectively put in

parallel with CO, causing a nearly instantaneous drop in

VO. No regulator can deliver enough current to prevent

this problem if the load switch resistance is low and it is

driven quickly. The only solution is to limit the rise time

of the switch drive in order to limit the inrush current

di/dt to the load.

Boost Converter Design Example

The design example given here will be for the circuit shown

in Figure 1. The input voltage is 3.3V, and the output is 5V

at a maximum load current of 7A (10A peak).

1. The duty cycle is:

D=VO+VD–V

VO+VD









=5+0.4 – 3.3

5+0.4 =38.9%

2. Pulse-skip operation is chosen so the MODE/SYNC pin

is shorted to INTVCC.

3. The operating frequency is chosen to be 300kHz to

reduce the size of the inductor. From Figure 5, the

resistor from the FREQ pin to ground is 80k.

4. An inductor ripple current of 40% of the maximum load

current is chosen, so the peak input current (which is

also the minimum saturation current) is:

IIN(PEAK) =1+









•IO(MAX)

1–DMAX

=1.2 • 7

1– 0.39 =13.8A

LTC1871-1

18711fb

APPLICATIONS INFORMATION

The inductor ripple current is:

IL=•IO(MAX)

1–DMAX

=0.4 • 7

1– 0.39 =4.6A

And so the inductor value is:

L=VIN(MIN)

IL• f •D

MAX =3.3V

4.6A • 300kHz • 0.39 =0.93μH

The component chosen is a 1µH inductor made by

Sumida (part number CEP125-H 1ROMH) which has

a saturation current of greater than 20A.

5. With the input voltage to the IC bootstrapped to the

output of the power supply (5V), a logic-level MOSFET

can be used. Because the duty cycle is 39%, the maxi-

mum SENSE pin threshold voltage is reduced from its

low duty cycle typical value of 150mV to approximately

140mV. Assuming a MOSFET junction temperature of

125°C, the room temperature MOSFET RDS(ON) should

be less than:

RDS(ON) VSENSE(MAX) •1–DMAX

1+









•I

O(MAX) •T

=0.140V • 1– 0.39

1+0.4









•7A•1.5

=6.8m

The MOSFET used was the Fairchild FDS7760A, which

has a maximum RDS(ON) of 8m at 4.5V VGS, a BVDSS

of greater than 30V, and a gate charge of 37nC at 5V

VGS.

6. The diode for this design must handle a maximum

DC output current of 10A and be rated for a minimum

reverse voltage of VOUT

, or 5V. A 25A, 15V diode from

On Semiconductor (MBRB2515L) was chosen for its

high power dissipation capability.

7. The output capacitor usually consists of a high valued

bulk C connected in parallel with a lower valued, low

ESR ceramic. Based on a maximum output ripple voltage

of 1%, or 50mV, the bulk C needs to be greater than:

COUT IOUT(MAX)

0.01• VOUT • f =

0.01• 5V • 300kHz =466μF

The RMS ripple current rating for this capacitor needs

to exceed:

IRMS(COUT) IO(MAX) •VO–V

IN(MIN)

VIN(MIN)

7A • 5V – 3.3V

3.3V =5A

To satisfy this high RMS current demand, four 150µF

Panasonic capacitors (EEFUEOJ151R) are required.

In parallel with these bulk capacitors, two 22µF, low

ESR (X5R) Taiyo Yuden ceramic capacitors (JMK-

325BJ226MM) are added for HF noise reduction.

Check the output ripple with a single oscilloscope

probe connected directly across the output capacitor

terminals, where the HF switching currents ﬂ ow.

8. The choice of an input capacitor for a boost converter

depends on the impedance of the source supply and the

amount of input ripple the converter will safely toler-

ate. For this particular design and lab setup a 100µF

Sanyo Poscap (6TPC 100M), in parallel with two 22µF

Taiyo Yuden ceramic capacitors (JMK325BJ226MM)

is required (the input and return lead lengths are kept

to a few inches, but the peak input current is close to

20A!). As with the output node, check the input ripple

with a single oscilloscope probe connected across the

input capacitor terminals.

LTC1871-1

18711fb

APPLICATIONS INFORMATION

Figure 14. LTC1871-1 Boost Converter Suggested Layout

Figure 15. LTC1871-1 Boost Converter Layout Diagram

LTC1871-1

VIN

18711 F14

VOUT

SWITCH NODE IS ALSO

THE HEAT SPREADER

FOR L1, M1, D1

RCCC

CIN

COUT

CVCC

PSEUDO-KELVIN

SIGNAL GROUND

CONNECTION

TRUE REMOTE

OUTPUT SENSING

VIAS TO GROUND

PLANE

PIN 1

COUT

BULK C LOW ESR CERAMIC

JUMPER

RUN

ITH

FREQ

MODE/

SYNC

SENSE

VIN

INTVCC

GATE

GND

LTC1871-1

CVCC

PSEUDO-KELVIN

GROUND CONNECTION

CIN

VIN

GND

18711 F15

VOUT

SWITCH

NODE

COUT

BOLD LINES INDICATE HIGH CURRENT PATHS

PC Board Layout Checklist

1. In order to minimize switching noise and improve output

load regulation, the GND pin of the LTC1871-1 should

be connected directly to 1) the negative terminal of the

INTVCC decoupling capacitor, 2) the negative terminal

of the output decoupling capacitors, 3) the

source of

the power MOSFET or the bottom terminal of the sense

resistor, 4) the negative terminal of the input capacitor

and 5) at least one via to the ground plane immediately

adjacent to Pin 6. The ground trace on the top layer of

the PC board should be as wide and short as possible

to minimize series resistance and inductance.

LTC1871-1

18711fb

APPLICATIONS INFORMATION

2. Beware of ground loops in multiple layer PC boards.

Try to maintain one central ground node on the board

and use the input capacitor to avoid excess input ripple

for high output current power supplies. If the ground

plane is to be used for high DC currents, choose a path

away from the small-signal components.

3. Place the CVCC capacitor immediately adjacent to the

INTVCC and GND pins on the IC package. This capaci-

tor carries high di/dt MOSFET gate drive currents. A

low ESR and ESL 4.7µF ceramic capacitor works well

here.

4. The high di/dt loop from the bottom terminal of the

output capacitor, through the power MOSFET, through

the boost diode and back through the output capacitors

should be kept as tight as possible to reduce inductive

ringing. Excess inductance can cause increased stress

on the power MOSFET and increase HF noise on the

output. If low ESR ceramic capacitors are used on the

output to reduce output noise, place these capacitors

close to the boost diode in order to keep the series

inductance to a minimum.

5. Check the stress on the power MOSFET by measuring

its drain-to-source voltage directly across the device

terminals (reference the ground of a single scope probe

directly to the source pad on the PC board). Beware

of inductive ringing which can exceed the maximum

speciﬁ ed voltage rating of the MOSFET. If this ringing

cannot be avoided and exceeds the maximum rating

of the device, either choose a higher voltage device

or specify an avalanche-rated power MOSFET. Not all

MOSFETs are created equal (some are more equal than

others).

6. Place the small-signal components away from high

frequency switching nodes. In the layout shown in

Figure 14, all of the small-signal components have

been placed on one side of the IC and all of the power

components have been placed on the other. This also

allows the use of a pseudo-Kelvin connection for the

signal ground, where high di/dt gate driver currents

ﬂ ow out of the IC ground pin in one direction (to the

bottom plate of the INTVCC decoupling capacitor) and

small-signal currents ﬂ ow in the other direction.

7. If a sense resistor is used in the source of the power

MOSFET, minimize the capacitance between the SENSE

pin trace and any high frequency switching nodes. The

LTC1871-1 contains an internal leading edge blanking

time of approximately 180ns, which should be adequate

for most applications.

8. For optimum load regulation and true remote sensing,

the top of the output resistor divider should connect

independently to the top of the output capacitor (Kelvin

connection), staying away from any high dV/dt traces.

Place the divider resistors near the LTC1871-1 in order

to keep the high impedance FB node short.

9. For applications with multiple switching power convert-

ers connected to the same input supply, make sure

that the input ﬁ lter capacitor for the LTC1871-1 is not

shared with other converters. AC input current from

another converter could cause substantial input volt-

age ripple, and this could interfere with the operation

of the LTC1871-1. A few inches of PC trace or wire

(L ≈ 100nH) between the CIN of the LTC1871-1 and the

actual source VIN should be sufﬁ cient to prevent current

sharing problems.

Figures 16. SEPIC Topology and Current Flow

•

SW L2 COUT RL

VOUT

VIN

C1 D1

16a. SEPIC Topology

•

VOUT

VIN

16c. Current Flow During Switch Off-Time

•

VOUT

VIN

16b. Current Flow During Switch On-Time

LTC1871-1

18711fb

APPLICATIONS INFORMATION

SEPIC Converter Applications

The LTC1871-1 is also well suited to SEPIC (single-ended

primary inductance converter) converter applications. The

SEPIC converter shown in Figure 16 uses two inductors.

The advantage of the SEPIC converter is the input voltage

may be higher or lower than the output voltage, and the

output is short-circuit protected.

The ﬁ rst inductor, L1, together with the main switch,

resembles a boost converter. The second inductor, L2,

together with the output diode D1, resembles a ﬂ yback or

buck-boost converter. The two inductors L1 and L2 can be

independent but can also be wound on the same core since

identical voltages are applied to L1 and L2 throughout the

switching cycle. By making L1 = L2 and winding them on

the same core the input ripple is reduced along with cost

and size. All of the SEPIC applications information that

follows assumes L1 = L2 = L.

SEPIC Converter: Duty Cycle Considerations

For a SEPIC converter operating in a continuous conduction

mode (CCM), the duty cycle of the main switch is:

D=VO+VD

VIN +VO+VD











where VD is the forward voltage of the diode. For convert-

ers where the input voltage is close to the output voltage

the duty cycle is near 50%.

The maximum output voltage for a SEPIC converter is:

VO(MAX) =VIN +VD

()

DMAX

1–DMAX

–V

1–DMAX

The maximum duty cycle of the LTC1871-1 is typically

92%.

SEPIC Converter: The Peak and Average

Input Currents

The control circuit in the LTC1871-1 is measuring the input

current (either using the RDS(ON) of the power MOSFET

or by means of a sense resistor in the MOSFET source),

so the output current needs to be reﬂ ected back to the

input in order to dimension the power MOSFET properly.

Based on the fact that, ideally, the output power is equal

to the input power, the maximum input current for a SEPIC

converter is:

IN(MAX)

O(MAX)

•D

MAX

1–D

MAX

The peak input current is:

IN(PEAK)

=1+









•I

O(MAX)

•D

MAX

1–D

MAX

The maximum duty cycle, DMAX, should be calculated at

minimum VIN.

Figure 17. SEPIC Converter Switching Waveforms

17a. Input Inductor Current

IIN

IL1 SW

OFF

17b. Output Inductor Current

IL2

17c. DC Coupling Capacitor Current

IIN

IC1

17e. Output Ripple Voltage

VOUT

(AC)

ΔVESR

RINGING DUE TO

TOTAL INDUCTANCE

(BOARD + CAP)

ΔVCOUT

17d. Diode Current

ID1

LTC1871-1

18711fb

APPLICATIONS INFORMATION

The constant ‘χ’ represents the fraction of ripple current in

the inductor relative to its maximum value. For example, if

30% ripple current is chosen, then χ = 0.30 and the peak

current is 15% greater than the average.

It is worth noting here that SEPIC converters that operate

at high duty cycles (i.e., that develop a high output volt-

age from a low input voltage) can have very high input

currents, relative to the output current. Be sure to check

that the maximum load current will not overload the input

supply.

SEPIC Converter: Inductor Selection

For most SEPIC applications the equal inductor values

will fall in the range of 10µH to 100µH. Higher values will

reduce the input ripple voltage and reduce the core loss.

Lower inductor values are chosen to reduce physical size

and improve transient response.

Like the boost converter, the input current of the SEPIC

converter is calculated at full load current and minimum

input voltage. The peak inductor current can be signiﬁ cantly

higher than the output current, especially with smaller in-

ductors and lighter loads. The following formulas assume

CCM operation and calculate the maximum peak inductor

currents at minimum VIN:

IL1(PEAK) =1+









•I

O(MAX) •VO+VD

VIN(MIN)

IL2(PEAK) =1+









•I

O(MAX) •VIN(MIN) +VD

VIN(MIN)

The ripple current in the inductor is typically 20% to 40%

(i.e., a range of ‘χ’ from 0.20 to 0.40) of the maximum

average input current occurring at VIN(MIN) and IO(MAX) and

ΔIL1 = ΔIL2. Expressing this ripple current as a function of

the output current results in the following equations for

calculating the inductor value:

L=VIN(MIN)

IL• f •D

MAX

where:

IL=•I

O(MAX) •DMAX

1–DMAX

By making L1 = L2 and winding them on the same core,

the value of inductance in the equation above is replace

by 2L due to mutual inductance. Doing this maintains the

same ripple current and energy storage in the inductors. For

example, a Coiltronix CTX10-4 is a 10µH inductor with two

windings. With the windings in parallel, 10µH inductance is

obtained with a current rating of 4A (the number of turns

hasn’t changed, but the wire diameter has doubled). Split-

ting the two windings creates two 10µH inductors with a

current rating of 2A each. Therefore, substituting 2L yields

the following equation for coupled inductors:

L1=L2=VIN(MIN)

2•IL• f •D

MAX

Specify the maximum inductor current to safely handle

IL(PK) speciﬁ ed in the equation above.

The saturation

current rating for the inductor should be checked at the

minimum input voltage (which results in the highest

inductor current) and maximum output current.

SEPIC Converter: Power MOSFET Selection

The power MOSFET serves two purposes in the LTC1871-1:

it represents the main switching element in the power path,

and its RDS(ON) represents the current sensing element

for the control loop. Important parameters for the power

MOSFET include the drain-to-source breakdown voltage

(BVDSS), the threshold voltage (VGS(TH)), the on-resistance

(RDS(ON)) versus gate-to-source voltage, the gate-to-source

and gate-to-drain charges (QGS and QGD, respectively),

the maximum drain current (ID(MAX)) and the MOSFET’s

thermal resistances (RTH(JC) and RTH(JA)).

The gate drive voltage is set by the 5.2V INTVCC low dropout

regulator. Consequently, logic-level threshold MOSFETs

should be used in most LTC1871-1 applications. If low

input voltage operation is expected (e.g., supplying power

from a lithium-ion battery), then sublogic-level threshold

MOSFETs should be used.

The maximum voltage that the MOSFET switch must

sustain during the off-time in a SEPIC converter is equal

to the sum of the input and output voltages (VO + VIN).

As a result, careful attention must be paid to the BVDSS

speciﬁ cations for the MOSFETs relative to the maximum

actual switch voltage in the application. Many logic-level

LTC1871-1

18711fb

APPLICATIONS INFORMATION

devices are limited to 30V or less. Check the switching

waveforms directly across the drain and source terminals

of the power MOSFET to ensure the VDS remains below

the maximum rating for the device.

During the MOSFET’s on-time, the control circuit limits

the maximum voltage drop across the power MOSFET to

about 150mV (at low duty cycle). The peak inductor current

is therefore limited to 150mV/RDS(ON). The relationship

between the maximum load current, duty cycle and the

RDS(ON) of the power MOSFET is:

DS(ON)

V

SENSE(MAX)

O(MAX)

•1

1+









•

•1

IN(MIN)









+1

The VSENSE(MAX) term is typically 150mV at low duty cycle

and is reduced to about 100mV at a duty cycle of 92% due

to slope compensation, as shown in Figure 8. The constant

‘χ’ in the denominator represents the ripple current in the

inductors relative to their maximum current. For example,

if 30% ripple current is chosen, then χ = 0.30. The ρT term

accounts for the temperature coefﬁ cient of the RDS(ON) of

the MOSFET, which is typically 0.4%/°C. Figure 9 illustrates

the variation of normalized RDS(ON) over temperature for

a typical power MOSFET.

Another method of choosing which power MOSFET to

use is to check what the maximum output current is for a

given RDS(ON) since MOSFET on-resistances are available

in discrete values.

IO(MAX) VSENSE(MAX)

RDS(ON)

•1

1+









•T

•1

VO+VD

VIN(MIN)









+1

Calculating Power MOSFET Switching and Conduction

Losses and Junction Temperatures

In order to calculate the junction temperature of the

power MOSFET, the power dissipated by the device must

be known. This power dissipation is a function of the

duty cycle, the load current and the junction temperature

itself. As a result, some iterative calculation is normally

required to determine a reasonably accurate value. Since

the controller is using the MOSFET as both a switching

and a sensing element, care should be taken to ensure

that the converter is capable of delivering the required

load current over all operating conditions (load, line and

temperature) and for the worst-case speciﬁ cations for

VSENSE(MAX) and the RDS(ON) of the MOSFET listed in the

manufacturer’s data sheet.

The power dissipated by the MOSFET in a SEPIC converter

is:

FET =IO(MAX) •DMAX

1–DMAX











•RDS(ON) •D

MAX •T

+k• V

IN(MIN) +VO

()

1.85 •I

O(MAX) •DMAX

1–DMAX

•C

RSS •f

The ﬁ rst term in the equation above represents the I2R

losses in the device and the second term, the switching

losses. The constant k = 1.7 is an empirical factor inversely

related to the gate drive current and has the dimension

of 1/current.

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

J = TA + PFET •RTH(JA)

The RTH(JA) to be used in this equation normally includes

the RTH(JC) for the device plus the thermal resistance from

the board to the ambient temperature in the enclosure.

This value of TJ can then be used to check the original

assumption for the junction temperature in the iterative

calculation process.

SEPIC Converter: Output Diode Selection

To maximize efﬁ ciency, a fast-switching diode with low

forward drop and low reverse leakage is desired. The output

diode in a SEPIC converter conducts current during the

switch off-time. The peak reverse voltage that the diode

must withstand is equal to VIN(MAX) + VO. The average

forward current in normal operation is equal to the output

current, and the peak current is equal to:

D(PEAK)

=1+









•I

O(MAX)

•V

IN(MIN)











The power dissipated by the diode is:

D = IO(MAX) • VD

LTC1871-1

18711fb

APPLICATIONS INFORMATION

and the diode junction temperature is:

J = TA + PD • RTH(JA)

The RTH(JA) to be used in this equation normally includes

the RTH(JC) for the device plus the thermal resistance from

the board to the ambient temperature in the enclosure.

SEPIC Converter: Output Capacitor Selection

Because of the improved performance of today’s electro-

lytic, tantalum and ceramic capacitors, engineers need

to consider the contributions of ESR (equivalent series

resistance), ESL (equivalent series inductance) and the

bulk capacitance when choosing the correct component

for a given output ripple voltage. The effects of these three

parameters (ESR, ESL, and bulk C) on the output voltage

ripple waveform are illustrated in Figure 17 for a typical

coupled-inductor SEPIC converter.

The choice of component(s) begins with the maximum

acceptable ripple voltage (expressed as a percentage of

the output voltage), and how this ripple should be divided

between the ESR step and the charging/discharging ΔV.

For the purpose of simplicity we will choose 2% for the

maximum output ripple, to be divided equally between the

ESR step and the charging/discharging ΔV. This percentage

ripple will change, depending on the requirements of the

application, and the equations provided below can easily

be modiﬁ ed.

For a 1% contribution to the total ripple voltage, the ESR

of the output capacitor can be determined using the fol-

lowing equation:

ESRCOUT 0.01• VO

IIN(PEAK)

where:

ID(PEAK) =1+









•I

O(MAX) •VO+VD

VIN(MIN)











For the bulk C component, which also contributes 1% to

the total ripple:

COUT IO(MAX)

0.01• VO• f

For many designs it is possible to choose a single capacitor

type that satisﬁ es both the ESR and bulk C requirements

for the design. In certain demanding applications, however,

the ripple voltage can be improved signiﬁ cantly by con-

necting two or more types of capacitors in parallel. For

example, using a low ESR ceramic capacitor can minimize

the ESR step, while an electrolytic or tantalum capacitor

can be used to supply the required bulk C.

Once the output capacitor ESR and bulk capacitance have

been determined, the overall ripple voltage waveform

should be veriﬁ ed on a dedicated PC board (see Board

Layout section for more information on component place-

ment). Lab breadboards generally suffer from excessive

series inductance (due to inter-component wiring), and

these parasitics can make the switching waveforms look

signiﬁ cantly worse than they would be on a properly

designed PC board.

The output capacitor in a SEPIC regulator experiences

high RMS ripple currents, as shown in Figure 17. The

RMS output capacitor ripple current is:

IRMS(C1) =IO(MAX) •VO+VD

VIN(MIN)

Note that the ripple current ratings from capacitor manu-

facturers are often based on only 2000 hours of life. This

makes it advisable to further derate the capacitor or to

choose a capacitor rated at a higher temperature than

required. Several capacitors may also be placed in parallel

to meet size or height requirements in the design.

Manufacturers such as Nichicon, United Chemicon and

Sanyo should be considered for high performance through-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest product of

ESR and size of any aluminum electrolytic, at a somewhat

higher price.

In surface mount applications, multiple capacitors may

have to be placed in parallel in order to meet the ESR or

RMS current handling requirements of the application.

Aluminum electrolytic and dry tantalum capacitors are

both available in surface mount packages. In the case of

tantalum, it is critical that the capacitors have been surge

tested for use in switching power supplies. An excellent

LTC1871-1

18711fb

APPLICATIONS INFORMATION

choice is AVX TPS series of surface mount tantalum. Also,

ceramic capacitors are now available with extremely low

ESR, ESL and high ripple current ratings.

SEPIC Converter: Input Capacitor Selection

The input capacitor of a SEPIC converter is less critical

than the output capacitor due to the fact that an inductor

is in series with the input and the input current waveform

is triangular in shape. The input voltage source impedance

determines the size of the input capacitor which is typi-

cally in the range of 10µF to 100µF. A low ESR capacitor

is recommended, although it is not as critical as for the

output capacitor.

The RMS input capacitor ripple current for a SEPIC con-

verter is:

IRMS(CIN) =1

12 •IL

Please note that the input capacitor can see a very high

surge current when a battery is suddenly connected to

the input of the converter and solid tantalum capacitors

can fail catastrophically under these conditions. Be sure

to specify surge-tested capacitors!

SEPIC Converter: Selecting the DC Coupling Capacitor

The coupling capacitor C1 in Figure 16 sees nearly a rectan-

gular current waveform as shown in Figure 17. During the

switch off-time the current through C1 is IO(VO/VIN) while

approximately –IO ﬂ ows during the on-time. This current

waveform creates a triangular ripple voltage on C1:

VC1(PP) =IO(MAX)

C1• f•VO

VIN +VO+VD

The maximum voltage on C1 is then:

VC1(MAX) =VIN +

VC1(PP)

which is typically close to VIN(MAX). The ripple current

through C1 is:

IRMS(C1) =IO(MAX) •VO+VD

VIN(MIN)

The value chosen for the DC coupling capacitor normally

starts with the minimum value that will satisfy 1) the RMS

current requirement and 2) the peak voltage requirement

(typically close to VIN). Low ESR ceramic and tantalum

capacitors work well here.

SEPIC Converter Design Example

The design example given here will be for the circuit shown

in Figure 18. The input voltage is 5V to 15V and the output

is 12V at a maximum load current of 1.5A (2A peak).

1. The duty cycle range is:

D=VO+VD

VIN +VO+VD









=45.5% to 71.4%

2. The operating mode chosen is pulse skipping, so the

MODE/SYNC pin is shorted to INTVCC.

3. The operating frequency is chosen to be 300kHz to

reduce the size of the inductors; the resistor from the

FREQ pin to ground is 80k.

4. An inductor ripple current of 40% is chosen, so the peak

input current (which is also the minimum saturation

current) is:

IL1(PEAK) =1+









•I

O(MAX) •VO+VD

VIN(MIN)

=1+0.4









• 1.5 • 12 +0.5

5=4.5A

The inductor ripple current is:

IL=•I

O(MAX) •DMAX

1–DMAX

=0.4 • 1.5 • 0.714

1– 0.714 =1.5A

LTC1871-1

18711fb

APPLICATIONS INFORMATION

And so the inductor value is:

L=VIN(MIN)

2•IL• f •D

MAX =5

2 • 1.5 • 300k • 0.714 =4μH

he component chosen is a BH Electronics BH510-

1007, which has a saturation current of 8A.

5. With an minimum input voltage of 5V, only logic-level

power MOSFETs should be considered. Because the

maximum duty cycle is 71.4%, the maximum SENSE

pin threshold voltage is reduced from its low duty

cycle typical value of 150mV to approximately 120mV.

Assuming a MOSFET junction temperature of 125°C,

the room temperature MOSFET RDS(ON) should be less

than:

RDS(ON) VSENSE(MAX)

IO(MAX)

•1

1+









•T

•1

VO+VD

VIN(MIN)









+1

=0.12

1.5 •1

1.2 • 1.5 •1

12.5









+1

=12.7m

For a SEPIC converter, the switch BVDSS rating must be

greater than VIN(MAX) + VO, or 27V. This comes close to

an IRF7811W, which is rated to 30V, and has a maximum

room temperature RDS(ON) of 12m at VGS = 4.5V.

Figure 18a. 4.5V to 15V Input, 12V/2A Output SEPIC Converter

Figure 18b. SEPIC Efﬁ ciency vs Output Current

RUN

ITH

FREQ

MODE/SYNC

SENSE

VIN

INTVCC

GATE

GND

LTC1871-1

80.6k

12.1k

105k

CVCC

4.7µF

X5R

CIN

47µF

CIN, COUT1: KEMET T495X476K020AS

CDC, COUT2: TAIYO YUDEN TMK432BJ106MM

D1: INTERNATIONAL RECTIFIER 30BQ040

•

L1*

L2*

33k

CC1

6.8nF

CC2

47pF

COUT1

47µF

20V

×2

VIN

4.5V to 15V

VOUT

12V

1.5A

(2A PEAK)

GND

18711 F018a

COUT2

10µF

25V

X5R

×2

L1, L2: BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS)

M1: INTERNATIONAL RECTIFIER IRF7811W

CDC

10µF

25V

X5R

OUTPUT CURRENT (A)

EFFICIENCY (%)

0.001 0.1 1 10

18711 F18b

0.01

100

VIN = 4.5V

VIN = 15V

VIN = 12V

VO = 12V

MODE = INTVCC

LTC1871-1

18711fb

APPLICATIONS INFORMATION

Figure 19. LTC1871-1 SEPIC Converter Load Step Response

VOUT (AC)

200mV/DIV

IOUT

0.5A/DIV

50µs/DIV 18711 F19

VIN = 15V

VOUT = 12V

VOUT (AC)

200mV/DIV

IOUT

0.5A/DIV

50µs/DIV

VIN = 4.5V

VOUT = 12V

6. The diode for this design must handle a maximum

DC output current of 2A and be rated for a minimum

reverse voltage of VIN + VOUT

, or 27V. A 3A, 40V diode

from International Rectiﬁ er (30BQ040) is chosen for its

small size, relatively low forward drop and acceptable

reverse leakage at high temp.

7. The output capacitor usually consists of a high valued

bulk C connected in parallel with a lower valued, low ESR

ceramic. Based on a maximum output ripple voltage of

1%, or 120mV, the bulk C needs to be greater than:

COUT IOUT(MAX)

0.01• VOUT • f =

1.5A

0.01• 12V • 300kHz =41μF

The RMS ripple current rating for this capacitor needs

to exceed:

IRMS(COUT) IO(MAX) •VO

VIN(MIN)

1.5A • 12V

5V=2.3A

To satisfy this high RMS current demand, two 47µF

Kemet capacitors (T495X476K020AS) are required. As a

result, the output ripple voltage is a low 50mV to 60mV.

In parallel with these tantalums, two 10µF, low ESR (X5R)

Taiyo Yuden ceramic capacitors (TMK432BJ106MM) are

added for HF noise reduction. Check the output ripple

with a single oscilloscope probe connected directly

across the output capacitor terminals, where the HF

switching currents ﬂ ow.

8. The choice of an input capacitor for a SEPIC converter

depends on the impedance of the source supply and the

amount of input ripple the converter will safely toler-

ate. For this particular design and lab setup, a single

47µF Kemet tantalum capacitor (T495X476K020AS) is

adequate. As with the output node, check the input ripple

with a single oscilloscope probe connected across the

input capacitor terminals. If any HF switching noise is

observed it is a good idea to decouple the input with

a low ESR, X5R ceramic capacitor as close to the VIN

and GND pins as possible.

9. The DC coupling capacitor in a SEPIC converter is cho-

sen based on its RMS current requirement and must be

rated for a minimum voltage of VIN plus the AC ripple

voltage. Start with the minimum value which satisﬁ es

the RMS current requirement and then check the ripple

voltage to ensure that it doesn’t exceed the DC rating.

IRMS(CI) IO(MAX) •VO+VD

VIN(MIN)

=1.5A • 12V +0.5V

5V =2.4A

For this design a single 10µF, low ESR (X5R) Taiyo

Yuden ceramic capacitor (TMK432BJ106MM) is

adequate.

LTC1871-1

18711fb

TYPICAL APPLICATIONS

2.5V to 3.3V Input, 5V/2A Output Boost Converter

Output Efﬁ ciency at 2.5V and 3.3V Input

RUN

ITH

FREQ

MODE/SYNC

SENSE

VIN

INTVCC

GATE

GND

LTC1871-1

80.6k

12.1k

37.4k

CVCC

4.7µF

X5R

CIN

47µF

6.3V

CIN: SANYO POSCAP 6TPA47M

COUT1: SANYO POSCAP 6TPB150M

COUT2: TAIYO YUDEN JMK316BJ106ML

CVCC: TAIYO YUDEN LMK316BJ475ML

1.8µH

22k

CC1

6.8nF

CC2

47pF

COUT1

150µF

6.3V

×2

VIN

2.5V to 3.3V

VOUT

GND

18711 TA01a

COUT2

10µF

6.3V

X5R

×2

D1: INTERNATIONAL RECTIFIER 30BQ015

L1: TOKO DS104C2 B952AS-1R8N

M1: SILICONIX/VISHAY Si9426

OUTPUT CURRENT (A)

EFFICIENCY (%)

100

0.001 0.1 1 10

18711 TA01b

0.01

LTC1871-1

18711fb

TYPICAL APPLICATIONS

18V to 27V Input, 28V Output, 400W 2-Phase, Low Ripple, Synchronized RF Base Station Power Supply (Boost)

5V to 12V Input, ±12V/0.2A Output SEPIC Converter with Undervoltage Lockout

RUN

ITH

FREQ

MODE/SYNC

SENSE

VIN

INTVCC

GATE

GND

LTC1871-1

RT1

150k

RS1

0.007Ω

EXT CLOCK

INPUT (200kHz)

8.45k

CVCC1

4.7µF

X5R

CIN2

2.2µF

35V

X5R

5.6µH

L5*

0.3µH

CC1

47pF

CFB1

47pF

VIN

18V to 27V

GND

VOUT

28V

14A

18711 TA04

COUT1

2.2µF

35V

X5R

×3

COUT2

330µF

50V

CIN1: SANYO 50MV330AX

CIN2, 3: TAIYO YUDEN GMK325BJ225MN

COUT2, 4, 5: SANYO 50MV330AX

COUT1, 3, 6: TAIYO YUDEN GMK325BJ225MN

CVCC1, 2: TAIYO YUDEN LMK316BJ475ML

L1 TO L4: SUMIDA CEP125-5R6MC-HD

L5: SUMIDA CEP125-0R3NC-ND

D1, D2: ON SEMICONDUCTOR MBR2045CT

M1, M2: INTERNATIONAL RECTIFIER IRLZ44NS

93.1k

5.6µH

*L5, COUT5 AND

COUT6 ARE AN

OPTIONAL SECONDARY

FILTER TO REDUCE

OUTPUT RIPPLE FROM

<500mVP-P TO <100mVP-P

COUT5*

330µF

50V

×4COUT6*

2.2µF

35V

X5R

CIN1

330µF

50V

RUN

ITH

FREQ

MODE/SYNC

SENSE

VIN

INTVCC

GATE

GND

LTC1871-1

RT2

150k

12.1k

22k

261k

CVCC2

4.7µF

X5R

CIN3

2.2µF

35V

X5R

5.6µH

CC2

47pF

CC3

6.8nF

CFB2

47pF

COUT3

2.2µF

35V

X5R

×3

COUT4

330µF

50V

5.6µH

RS2

0.007Ω

RUN

ITH

FREQ

MODE/SYNC

SENSE

VIN

INTVCC

GATE

GND

LTC1871-1

60.4k

1% RS

0.02Ω

127Ω

54.9k

1.10k

CVCC

4.7µF

10V

X5R

CIN1

1µF

16V

X5R

L1*

•

22k

CC1

6.8nF

CC2

100pF

CDC1

4.7µF

16V

X5R

VIN

5V to 12V

VOUT1

12V

0.4A

GND

VOUT2

–12V

0.4A

18711 TA03

COUT1

4.7µF

16V

X5R

×3

COUT2

4.7µF

16V

X5R

×3

D1, D2: MBS120T3

L1 TO L3: COILTRONICS VP1-0076 (*COUPLED INDUCTORS)

M1: SILICONIX/VISHAY Si4840

127k

CIN2

47µF

16V

AVX

CDC2

4.7µF

16V

X5R

L2*

L3*

•

NOTE:

1. VIN UVLO+ = 4.47V

VIN UVLO– = 4.14V

LTC1871-1

18711fb

TYPICAL APPLICATIONS

4.5V to 28V Input, 5V/2A Output SEPIC Converter with Undervoltage Lockout and Soft-Start

Soft-Start Load Step Response at VIN = 4.5V

Load Step Response at VIN = 28V

RUN

ITH

FREQ

MODE/SYNC

SENSE

VIN

INTVCC

GATE

GND

LTC1871-1

162k

1µF

X5R NOTES:

1. VIN UVLO+ = 4.17V

VIN UVLO– = 3.86V

2. SOFT-START dVOUT/dt = 5V/6ms

49.9k

154k

115k

54.9k

CVCC

4.7µF

10V

X5R

CIN1

2.2µF

35V

X5R

CIN2

22µF

35V

•

L1*

L2*

12k

CC1

8.2nF

4.7nF

CC2

47pF

750Ω

100Ω

COUT1

330µF

6.3V

VIN

4.5V to 28V

VOUT

(3A TO 4A PEAK)

GND

18711 TA02a

COUT2

22µF

6.3V

X5R

CDC

2.2µF

25V

X5R

×3

CIN1, CDC: TAIYO YUDEN GMK325BJ225MN

CIN2: AVX TPSE226M035R0300

COUT1: SANYO 6TPB330M

COUT2: TAIYO YUDEN JMK325BJ226MN

CVCC: LMK316BJ475ML

D1: INTERNATIONAL RECTIFIER 30BQ040

L1, L2: BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS)

M1: SILICONIX/VISHAY Si4840

Q1: PHILIPS BC847BF

VOUT

1V/DIV

1ms/DIV 18711 TA02b

VOUT

100mV/DIV

(AC)

2.2A

0.5A

250µs/DIV 18711 TA02c

IOUT

1A/DIV

(DC)

VOUT

100mV/DIV

(AC)

2.2A

0.5A

250µs/DIV 18711 TA02d

IOUT

1A/DIV

(DC)

LTC1871-1

18711fb

TYPICAL APPLICATIONS

5V to 15V Input, –5V/5A Output Positive-to-Negative Converter with Undervoltage Lockout and Level-Shifted Feedback

RUN

ITH

FREQ

MODE/SYNC

SENSE

VIN

INTVCC

GATE

GND

LTC1871-1

80.6k

154k

68.1k

1nF

CVCC

4.7µF

10V

X5R

10nF

10k

1% R5

40.2k

10k

CIN

47µF

16V

X5R

CIN: TDK C5750X5R1C476M

CDC: TDK C5750X7R1E226M

COUT: TDK C5750X5R0J107M

CVCC: TAIYO YUDEN LMK316BJ475ML

•

L1* L2*

10k

CC1

10nF

CC2

330pF

VIN

5V to 15V

VOUT

–5V

GND

18711 TA05

COUT

100µF

6.3V

X5R

×2

D1: ON SEMICONDUCTOR MBRB2035CT

L1, L2: COILTRONICS VP5-0053 (*3 WINDINGS IN PARALLEL

FOR THE PRIMARY, 3 IN PARALLEL FOR SECONDARY)

M1: INTERNATIONAL RECTIFIER IRF7822

CDC

22µF

25V

X7R

–

LT1783

LTC1871-1

18711fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661 Rev E)

MSOP (MS) 0307 REV E

0.53 ± 0.152

(.021 ± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 – 0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

12345

4.90 ± 0.152

(.193 ± .006)

0.497 ± 0.076

(.0196 ± .003)

REF

8910 76

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ± 0.038

(.0120 ± .0015)

TYP

0.50

(.0197)

BSC

0.1016 ± 0.0508

(.004 ± .002)

LTC1871-1

18711fb

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0108 REV B • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

High Power SLIC Supply with Undervoltage Lockout

(Also See the LTC3704 Data Sheet)

RUN

ITH

FREQ

MODE/SYNC

SENSE

VIN

INTVCC

GATE

GND

LTC1871-1

120k f = 200kHz

*COILTRONICS VP5-0155

(PRIMARY = 3 WINDINGS IN PARALLEL)

4.7µF

X5R

+CIN

220µF

16V

TPS

10µF

25V

X5R

IRL2910

0.012Ω

0.1µF

10BQ060

•

VIN

7V TO 12V

T1*

1, 2, 3

82k

CC1

1nF

CC2

100pF

1nF

49.9k

150k

10BQ060

•

10BQ060

•

10µF

25V

X5R

COUT

3.3µF

100V

GND

VOUT1

–24V

200mA

VOUT2

–72V

200mA

10µF

25V

X5R

18711 TA06

10k

RF1

10k

RF2

196k

4.7µF

50V

X5R

–

LT1783

PART NUMBER DESCRIPTION COMMENTS

1619 Current Mode PWM Controller 300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology

LTC1624 Current Mode DC/DC Controller SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design;

VIN Up to 36V

LTC1700 No RSENSE Synchronous Step-Up Controller Up to 95% Efﬁ ciency, Operation as Low as 0.9V Input

LTC1871 Wide Input Range Controller No RSENSE, 5V Gate Drive, Current Mode Control

LTC1871-7 Wide Input Range Controller No RSENSE, 7V Gate Drive, Current Mode Control

LTC1872 SOT-23 Boost Controller Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode

LT1930 1.2MHz, SOT-23 Boost Converter Up to 34V Output, 2.6V ≤ VIN ≤ 16V, Miniature Design

LT1931 Inverting 1.2MHz, SOT-23 Converter Positive-to-Negative DC/DC Conversion, Miniature Design

LTC3401/LTC3402 1A/2A 3MHz Synchronous Boost Converters Up to 97% Efﬁ ciency, Very Small Solution, 0.5V ≤ VIN ≤ 5V

LTC3704 Positive-to-Negative DC/DC Controller No RSENSE, Current Mode Control, 50kHz to 1MHz

LT3782 2-Phase Step-Up DC/DC Controller 6V ≤ VIN ≤ 40V; 4A Gate Drive, 150kHz to 500kHz