PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY 128Mb BURST CellularRAMTM 1.5 MT45W8MW16BGX Features Figure 1: Ball Assignment 54-Ball VFBGA * Single device supports asynchronous, page, and burst operations * Vcc, VccQ Voltages 1.7V-1.95V Vcc 1.7V-1.95V VccQ * Random Access Time: 70ns * Burst Mode READ and WRITE Access 4, 8, 16, or 32 words, or continuous burst Burst wrap or sequential MAX clock rate: 104 MHz (tCLK = 9.62ns) Burst initial latency: 39ns (4 clocks) @ 104 MHz t ACLK: 7ns @ 104 MHz * Page Mode Read Access Sixteen-word page size Interpage read access: 70ns Intrapage read access: 20ns * Low Power Consumption Asynchronous READ: < 30mA Intrapage Read: < 15mA Initial access, burst READ: (39ns [4 clocks] @ 104 MHz) < 40mA Continuous burst READ: < 25mA Standby: < 40A (TYP at 25 C) Deep power-down: < 3A (TYP) * Low-Power Features On-chip Temperature Compensated Refresh (TCR) Partial Array Refresh (PAR) Deep Power-Down (DPD) Mode Options * Configuration: 8 Meg x 16 VCC Core Voltage Supply: 1.8V VCCQ I/O Voltage Supply: 1.8V * Package 54-ball VFBGA--"green" * Timing 70ns access 85ns access 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CRE B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSSQ DQ11 A17 A7 DQ3 VCC E VCCQ DQ12 A21 A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 J WAIT CLK ADV# A22 RFU RFU Top View (Ball Down) Options (continued) * Frequency 66 MHz 80 MHz 104 MHz * Standby Power at 85C Standard: 200A (MAX) Low-power: 160A (MAX) * Operating Temperature Range Wireless (-30C to +85C) Industrial (-40C to +85C) Designator MT45W8MW16B GX -70 -85 Designator 6 8 1 None L WT IT Part Number Example: MT45W8MW16BGX-701LWT 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__1.fm - Rev. A 9/04 EN 1 (c)2003 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Part-Numbering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Burst Wrap (BCR[3]) Default = No Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .22 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Latency Counter (BCR[13:11]) Default = Three Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Initial Access Latency (BRC[14]) Default = Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Partial Array Refresh (RCR[2:0] Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Page Mode Operation (RCR[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Data Sheet Designation: Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128TOC.fm - Rev. A 9/04 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: Ball Assignment 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Functional Block Diagram--8 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 READ Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 WRITE Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Page Mode READ Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Mode READ (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Burst Mode WRITE (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Wired or WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Refresh Collision During Variable-Latency READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Configuration Register WRITE, Asynchronous Mode Followed by READ ARRAY Operation . . . . . .16 Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation . . . . . . .16 Register READ, Asynchronous Mode Followed by READ ARRAY Operation . . . . . . . . . . . . . . . . . . . .17 Register READ, Synchronous Mode Followed by READ ARRAY Operation . . . . . . . . . . . . . . . . . . . . .18 Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 WAIT Configuration During Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Latency Counter (Variable Initial Latency, No Refresh Collision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Latency Counter (Fixed Latency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Typical Refresh Current vs. Temperature (ITCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 AC Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Asynchronous READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Single-Access Burst READ Operation--Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4-Word Burst READ Operation--Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Single-Access Burst READ Operation--Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4-Word Burst READ Operation--Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4-Word Burst READ Operation (with LB#/UB#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Continuous Burst READ Showing an Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Burst WRITE Operation--Variable Latency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Burst WRITE Operation--Fixed Latency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Continuous Burst WRITE Showing an Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Burst READ Interrupted by Burst READ or WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Burst WRITE Interrupted by Burst WRITE or READ--Variable Latency Mode . . . . . . . . . . . . . . . . . .55 Burst WRITE Interrupted by Burst WRITE or READ--Fixed Latency Mode . . . . . . . . . . . . . . . . . . . . .56 Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Asynchronous WRITE (ADV# LOW) Followed By Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Burst READ Followed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Asynchronous WRITE Followed by Asynchronous READ--ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . .61 Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128LOF.fm - Rev. A 9/04 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Table 49: Table 50: Table 51: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Bus Operations--Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Bus Operations--Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Variable Latency Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Fixed Latency Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 128Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Device Identification Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Partial Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Asynchronous READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Asynchronous READ Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Asynchronous READ Timing Parameters--Page Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Burst READ Timing Parameters--Single Access, Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Burst READ Timing Parameters--4-Word Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Burst READ Timing Parameters--Single Access, Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Burst READ Timing Parameters--4-Word Burst, Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Burst READ Timing Parameters--4-Word Burst with LB#/UB#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Burst READ Timing Parameters--Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Burst READ Timing Parameters--BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Asynchronous WRITE Timing Parameters--CE#-Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Asynchronous WRITE Timing Parameters--LB#/UB#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Asynchronous WRITE Timing Parameters--WE#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Asynchronous WRITE Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Burst WRITE Timing Parameters--BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 WRITE Timing Parameters--Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . .53 READ Timing Parameters--Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 READ Timing Parameters--Burst WRITE Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 WRITE Timing Parameters--Burst WRITE Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 WRITE Timing Parameters--Burst READ Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 READ Timing Parameters--Burst READ Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 WRITE Timing Parameters--Burst READ Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 READ Timing Parameters--Burst READ Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 WRITE Timing Parameters--Async WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . .57 READ Timing Parameters--Async WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Asynchronous WRITE Timing Parameters--ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Asynchronous WRITE Timing Parameters--WE# Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Asynchronous WRITE Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128LOT.fm - Rev. A 9/04 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 52: Table 53: Table 54: Table 55: WRITE Timing Parameters--ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 READ Timing Parameters--ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 WRITE Timing Parameters--Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . .62 READ Timing Parameters--Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . . .62 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128LOT.fm - Rev. A 9/04 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY General Description Micron CellularRAMTM products are high-speed, CMOS pseudo-static random access memories developed for low-power, portable applications. The MT45W8MW16BGX device has a 128Mb DRAM core, organized as 8 Meg x 16 bits. These devices include an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature compensated refresh (TCR) uses an on-chip sensor to adjust the refresh rate to match the device temperature--the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system configurable refresh mechanisms are accessed through the RCR. This CellularRAM device is compliant with the industry-standard CellularRAM 1.5 feature set established by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with three output-device drive-strength settings, additional wrap options, and a device ID register (DIDR). Figure 2: Functional Block Diagram--8 Meg x 16 A[22:0] Address Decode Logic 8,192K x 16 DRAM MEMORY ARRAY Refresh Configuration Register (RCR) Input/ Output MUX and Buffers DQ[7:0] DQ[15:8] Device ID Register (DIDR) Bus Configuration Register (BCR) CE# WE# OE# CLK ADV# CRE WAIT LB# UB# Control Logic NOTE: Functional block diagrams illustrate simplified device operation. See ball descriptions (Table 1); bus operations tables (Tables 2 and 3); and timing diagrams for detailed information. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY l 1: Table VFBGA Ball Descriptions VFBGA ASSIGNMENT SYMBOL TYPE DESCRIPTION A3, A4, A5, B3, B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4, E4, D3, H1, G2, H6, E3, J4 J2 A[22:0] Input Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the BCR or the RCR. CLK Input J3 ADV# Input A6 CRE Input B5 CE# Input A2 OE# Input G5 WE# Input A1 B2 B6, C5, C6, D5, E5, F5, F6, G6, B1, C1, C2, D2, E2, F2, F1, G1 J1 LB# UB# DQ[15:0] Input Input Input/ Output Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK is static LOW during asynchronous access READ and WRITE operations and during PAGE READ ACCESS operations. Address Valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during asynchronous READ and WRITE operations. ADV# can be held LOW during asynchronous READ and WRITE operations. Control Register Enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ operations access the RCR, BCR, or DIDR. Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby or deep power-down mode. Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Lower Byte Enable. DQ[7:0] Upper Byte Enable. DQ[15:8] Data Inputs/Outputs. WAIT Output J5, J6 D6 E1 E6 D1 RFU VCC VCCQ VSS VSSQ -- Supply Supply Supply Supply Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to mask the delay associated with opening a new internal page. WAIT is asserted and should be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH. Reserved for future use. Device Power Supply: (1.70V-1.95V) Power supply for device core operation. I/O Power Supply: (1.70V-1.95V) Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground. NOTE: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. WAIT will be asserted but should be ignored during asynchronous and page mode operations. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 2: Bus Operations--Asynchronous Mode MODE POWER CLK1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT2 DQ[15:0]3 NOTES Read Write Standby No Operation Configuration Register Write Configuration Register Read DPD Active Active Standby Idle Active L L L L L L L X X L L L H L L L X X X H H L X X L L L L L H L L X X X Low-Z Low-Z High-Z Low-Z Low-Z Data-Out Data-In High-Z X High-Z 4 4 5, 6 4, 6 Active L L L L H H L Deep Power-Down L X H X X X X Low-Z Config. Reg. Out High-Z High-Z Table 3: 7 Bus Operations--Burst Mode MODE POWER CLK1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT2 DQ[15:0]3 NOTES Async Read Async Write Standby No Operation Initial Burst Read Active Active Standby Idle Active L L L L L L X X L L L H L L L X X X X H L X X H L L L L L L L X X L Low-Z Low-Z High-Z Low-Z Low-Z Data-Out Data-In High-Z X Data-Out 4 4 5, 6 4, 6 4, 8 Initial Burst Write Active L L H L L X Low-Z Data-In 4, 8 Burst Continue Active H L X X X L Low-Z Data-In or Data-Out 4, 8 Burst Suspend Configuration Register Write Active Active X L L L H H X L X H X X Low-Z Low-Z High-Z High-Z 4, 8 8, 9 Configuration Register Read Active L L L H H L Low-Z Config. Reg. Out X H X X X X High-Z DPD Deep Power-Down X L High-Z 8, 9 7 NOTE: 1. CLK must be LOW during async read and async write modes; and to achieve standby power during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current. 7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transitions from HIGH to LOW. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]). 9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated by WAIT). 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Part-Numbering Information Micron CellularRAM devices are available in several different configurations and densities (see Figure 3). Figure 3: Part Number Chart MT 45 W 8M W 16 B GX -70 8 WT ES Micron Technology Production Status Blank = Production Product Family ES = Engineering Sample 45 = PSRAM/CellularRAM Memory MS = Mechanical Sample Operating Core Voltage Operating Temperature W = 1.70V-1.95V WT = -30C to +85C IT = -40 to +85C Address Locations Standby Power Options M = Megabits Blank = Standard Operating Voltage L = Low Power W = 1.70V-1.95V Frequency 6 = 66 MHz 8 = 80 MHz Bus Configuration 1 = 104 MHz 16 = x16 Access/Cycle Time READ/WRITE Operation Mode 70 = 70ns B = Asynchronous/Page/Burst 85 = 85ns Package Codes GX = "Green" VFBGA (6 x 9 grid, 0.75mm pitch, 8.0mm x 10.0mm x 1.0mm) 54-ball Valid Part Number Combinations Device Marking After building the part number from the part numbering chart above, please go to the Micron Part Marking Decoder Web site at http://www.micron.com/ partsearch to verify that the part number is offered and valid. If the device required is not on this list, please contact the factory. Due to the size of the package, the Micron standard part number is not printed on the top of the device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at http://www.micron.com/partsearch. To view the location of the abbreviated mark on the device, please refer to customer service note, CSN-11, "Product Mark/Label," at http://www.micron.com/ csn. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Functional Description UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a "Don't Care," and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can either use the ADV input to latch the address, or ADV can be driven LOW during the entire READ/WRITE operation. During asynchronous operation, the CLK input must be held static LOW. WAIT will be driven while the device is enabled and its state should be ignored. WE# LOW time must be limited to tCEM. In general, the MT45W8MW16BGX device is a highdensity alternative to SRAM and Pseudo SRAM products, popular in low-power, portable applications. MT45W8MW16BGX contains a 134,217,728-bit DRAM core, organized as 8,388,608 addresses by 16 bits. The device implements the same high-speed bus interface found on burst mode Flash products. The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. Power-Up Initialization Figure 5: READ Operation (ADV# LOW) CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings (see Table 18 on page 20 and Table 24 on page 26). VCC and VCCQ must be applied simultaneously. When they reach a stable level at or above 1.7V, the device will require 150s to complete its self-initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. CE# OE# WE# ADDRESS DATA Figure 4: Power-Up Initialization Timing Vcc = 1.7V Vcc VccQ ADDRESS VALID DATA VALID LB#/UB# tRC = READ Cycle Time tPU > 150s Device ready for Device Initialization normal operation DON'T CARE NOTE: ADV must remain LOW for page mode operation. Bus Operating Modes The MT45W8MW16BGX CellularRAM product incorporates a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]). Figure 6: WRITE Operation (ADV# LOW) CE# OE# < tCEM WE# ADDRESS ADDRESS VALID Asynchronous Mode DATA CellularRAM products power up in the asynchronous operating mode. This mode uses the industrystandard SRAM control bus (CE#, OE#, WE#, LB#/ UB#). READ operations (Figure 5) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 6) occur when CE#, WE#, and LB#/ 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN DATA VALID LB#/UB# tWC = WRITE Cycle Time DON'T CARE 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Page Mode READ Operation The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, sixteen, or thirty-two words. Continuous bursts have the ability to start at a specified address and burst through the entire memory. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device. The initial latency for READ operations can be configured as fixed or variable (WRITE operations always use fixed latency). Variable latency allows the CellularRAM to be configured for minimum latency at high clock frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles. Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency time and clock speed determine the latency count setting. The boundaries of 128-word rows should not be crossed in fixed latency mode. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency also provides improved performance at lower clock frequencies. The WAIT output asserts as soon as CE# goes LOW, and de-asserts to indicate when data is to be transferred into (or out of ) the memory. WAIT will again be asserted if the burst crosses a row boundary (variable latency only--do not cross row boundaries when using fixed latency). Once the CellularRAM device has restored the previous row's data and accessed the next row, WAIT will be de-asserted and the burst can continue (see Figure 38 on page 45). To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is available on the bus. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle. Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In pagemode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Any change in addresses A[4] or higher will initiate a new tAA access time. Figure 7 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. During asynchronous page mode operation, the CLK input must be held LOW. CE# must be driven HIGH upon completion of a page mode access. WAIT will be driven while the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH. ADV must be driven LOW during all page mode read accesses. Due to refresh considerations, CE# must not be LOW longer than tCEM. Figure 7: Page Mode READ Operation (ADV# LOW) < tCEM CE# OE# WE# ADDRESS Add[0] tAA DATA Add[1] tAPA D[0] Add[2] tAPA D[1] Add[3] tAPA D[2] D[3] LB#/UB# DON'T CARE Burst Mode Operation Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge of the next clock that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH, Figure 8 on page 12) or WRITE (WE# = LOW, Figure 9 on page 12). 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 8: Burst Mode READ (4-word burst) CLK A[22:0] ADDRESS VALID ADV# Latency Code 2 (3 clocks) CE# OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# DON'T CARE READ Burst Identified (WE# = HIGH) UNDEFINED NOTE: Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Diagram above is representative of variable latency with no refresh collision or fixed-latency access. Figure 9: Burst Mode WRITE (4-word burst) CLK A[22:0] ADDRESS VALID ADV# CE# Latency Code 2 (3 clocks) OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# DON'T CARE WRITE Burst Identified (WE# = LOW) NOTE: Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Mixed-Mode Operation CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT configuration BCR[8] = 1). Bringing CE# HIGH during WAIT cycles may cause data corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after WAIT de-asserts, and for row boundary crossings, start one cycle after the WAIT signal asserts.) When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for READ operations launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has completed (see Figures 11 on page 14). When the refresh operation has completed, the READ operation will continue normally. WAIT is also asserted when a continuous READ or WRITE burst crosses the boundary between 128-word rows. The WAIT assertion allows time for the new row to be accessed, and permits any pending refresh operations to be performed. WAIT will be asserted but should be ignored during asynchronous READ and WRITE, and page READ operations. By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst mode without monitoring the WAIT signal. However, WAIT can still be used to determine when valid data is available at the start of the burst and at row-boundary crossings. If WAIT is not monitored, the controller must stop burst accesses at row boundaries and restart the burst to access the next row. The device supports a combination of synchronous READ and asynchronous READ and WRITE operations when the BCR is configured for synchronous operation. The asynchronous READ and WRITE operations require that the clock (CLK) remain LOW during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain LOW during the entire WRITE operation. CE# can remain LOW when transitioning between mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed tCEM. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 50 on page 57 for the "Asynchronous WRITE Followed by Burst READ" timing diagram. WAIT Operation The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal (see Figure 10). The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. Figure 10: Wired or WAIT Configuration CellularRAM WAIT External Pull-Up/ Pull-Down Resistor READY Processor WAIT WAIT Other Device Other Device LB#/UB# Operation The LB# enable and UB# enable signals support byte-wide data transfers. During READ operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. Once a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 11: Refresh Collision During Variable-Latency READ Operation CLK A[22:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] VIH VIL VIH VIL VALID ADDRESS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D[0] VOL Additional WAIT states inserted to allow refresh completion. D[1] D[2] D[3] UNDEFINED DON'T CARE NOTE: Non-default BCR settings for refresh collision during variable-latency READ operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation, or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs. device will require 150s to perform an initialization procedure before normal operations can resume. During this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD can be enabled by writing to the RCR using CRE or the software access sequence; DPD starts when CE# goes HIGH. DPD is disabled the next time CE# goes LOW. Temperature Compensated Refresh Registers Temperature compensated refresh (TCR) allows for adequate refresh at different temperatures. This CellularRAM device includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The device continually adjusts the refresh rate to match that temperature. Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. A DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. The DIDR is read-only. Partial Array Refresh Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 8 on page 27). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR. Access Using CRE The registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (CRE) input is HIGH (see Figures 12 through 15 on pages 16 through 18). When CRE is LOW, a READ or WRITE operation will access the memory array. The configuration register values are written via addresses A[22:0]. In an asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are "Don't Care." The BCR is accessed when A[19:18] are 10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when A[19:18] are 01b. For reads, address inputs other than A[19:18] are "Don't Care," and register bits 15:0 are output on DQ[15:0]. Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled by rewriting the RCR, the CellularRAM 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 12: Configuration Register WRITE, Asynchronous Mode Followed by READ ARRAY Operation A[22:0] (except A[19:18]) OPCODE ADDRESS tAVH tAVS Select Control Register A[19:18]1 ADDRESS tAVS CRE tAVH tVPH ADV# tVP tCBPH Initiate Control Register Access CE# tCW OE# tWP Write Address Bus Value to Control Register WE# LB#/UB# DQ[15:0] DATA VALID DON'T CARE NOTE: 1. A[19:18] = 00b to load RCR, and 10b to load BCR. Figure 13: Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation CLK Latch Control Register Value A[22:0] (except A[19:18]) OPCODE t tSP HD ADDRESS Latch Control Register Address A[19:18]2 ADDRESS tSP CRE tSP ADV# tHD tHD tCBPH3 tCSP CE# OE# tSP WE# tHD LB#/UB# WAIT tCEW High-Z High-Z DATA VALID DQ[15:0] DON'T CARE NOTE: 1. Non-default BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. A[19:18] = 00b to load RCR, and 10b to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 14: Register READ, Asynchronous Mode Followed by READ ARRAY Operation A[22:0] (except A[19:18]) ADDRESS tAVH tAVS Select Register A[19:18]1 ADDRESS tAA tAVH tAVS CRE tAA tVPH ADV# tVP tAAVD CE# tCBPH Initiate Register Access tHZ tCO OE# tOHZ tOE tBA WE# tOLZ tLZ tBHZ LB#/UB# tLZ DQ[15:0] CR VALID DATA VALID DON'T CARE UNDEFINED NOTE: A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 15: Register READ, Synchronous Mode Followed by READ ARRAY Operation CLK Latch Control Register Value A[22:0] (except A[19:18]) ADDRESS tSP Latch Control Register Address A[19:18]2 ADDRESS tHD tSP CRE tHD tSP ADV# tHD tABA tCBPH3 tCSP CE# tHZ OE# tOHZ WE# tBOE tSP LB#/UB# tHD tCW WAIT tOLZ tACLK High-Z DQ[15:0] High-Z CR VALID DATA VALID tKOH DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Software Access Figure 16: Load Configuration Register Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be modified and all registers can be read using the software sequence. The configuration registers are loaded using a fourstep sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations (see Figure 16). The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation (see Figure 17). The address used during all READ and WRITE operations is the highest address of the CellularRAM device being accessed (7FFFFFh for 128Mb); the contents of this address are not changed by using this sequence. The data value presented during the third operation (WRITE) in the sequence defines whether the BCR, RCR, or the DIDR is to be accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR; if the data is 0002h, the sequence will access the DIDR. During the fourth operation, DQ[15:0] transfer data in to or out of bits 15-0 of the registers. The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for CRE. If the software mechanism is used, CRE can simply be tied to VSS. The port line often used for CRE control purposes is no longer required. ADDRESS READ READ WRITE WRITE ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) XXXXh XXXXh CE# OE# WE# LB#/UB# DATA CR VALUE IN RCR: 0000h BCR: 0001h DON'T CARE Figure 17: Read Configuration Register ADDRESS READ READ WRITE READ ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) XXXXh XXXXh CE# OE# WE# LB#/UB# DATA CR VALUE OUT RCR: 0000h BCR: 0001h DIDR: 0002h 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 19 DON'T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Bus Configuration Register The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the register access software sequence with DQ = 0001h on the third cycle. The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 18 describes the control bits in the BCR. At power-up, the BCR is set to 9D1Fh. Figure 18: Bus Configuration Register Definition A[22:20] A[19:18] A[17:16] A15 22-20 19-18 17-16 Reserved Register Select Reserved A14 A13 A12A11 A10 15 14 Operating Mode 13 12 11 Initial Latency Latency Counter Must be set to "0" All must be set to "0" 10 WAIT Polarity A8 A9 9 Reserved A7 7 8 WAIT Configuration (WC) Must be set to "0" A5 A6 Must be set to "0" 3 4 5 6 Reserved A2 A1 A0 2 0 Setting is ignored (Default to "0") Initial Access Latency BCR[14] 0 Variable (default) 1 Fixed Burst Wrap (Note 1) BCR[3] BCR[13] BCR[12] BCR[11] 0 Burst wraps within the burst length 1 Burst no wrap (default) Latency Counter 0 0 0 Code 0-Reserved BCR[5] BCR[4] 0 0 1 Code 1-Reserved 0 0 Full 0 1 0 Code 2 0 1 1/2 (default) 0 1 1 Code 3 (Default) 1 0 1/4 1 0 0 Code 4 1 1 Reserved 1 0 1 Code 5 1 1 0 Code 6 1 1 1 Code 7-Reserved BCR[8] BCR[10] Drive Strength WAIT Configuration 0 Asserted during delay 1 Asserted one data cycle before delay (default) WAIT Polarity 0 Active LOW 1 Active HIGH (default) BCR[2] BCR[1] BCR[0] Burst Length (Note 1) 0 0 1 4 words 0 1 0 8 words 0 Synchronous burst access mode 0 1 1 16 words 1 Asynchronous access mode (default) 1 0 0 32 words 1 1 1 Continuous burst (default) BCR[15] 1 Burst Burst Wrap (BW)* Length (BL)* Drive Strength Reserved A3 A4 Operating Mode Register Select BCR[19] BCR[18] 0 0 Select RCR 1 0 Select BCR 0 1 Select DIDR Others Reserved NOTE: 1. Burst wrap and length apply to both READ and WRITE operations. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 4: STARTING ADDRESS 4WORD BURST LENGTH WRAP (DECIMAL) BURST WRAP BCR[3] 0 Sequence and Burst Length Yes 8-WORD BURST LENGTH 16-WORD BURST LENGTH No CONTINUOUS BURST LINEAR LINEAR LINEAR LINEAR LINEAR 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-...-29-30-31 0-1-2-3-4-5-6-... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-...-30-31-0 1-2-3-4-5-6-7-... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-...-31-0-1 2-3-4-5-6-7-8-... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-...-0-1-2 3-4-5-6-7-8-9-... 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-...-1-2-3 4-5-6-7-8-9-10-... 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-...-2-3-4 5-6-7-8-9-10-11-... 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-...-3-4-5 6-7-8-9-10-11-12- 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-...-4-5-6 7-8-9-10-11-12-13-... ... ... ... ... 14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-...-11-12-13 14-15-16-17-18-19-20-... 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-...-12-13-14 15-16-17-18-19-20-21-... ... ... ... 30 30-31-0-...-27-28-29 30-31-32-33-34-... 31 1 32-WORD BURST LENGTH 31-0-1-...-28-29-30 31-32-33-34-35-... 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2...--29-30-31 0-1-2-3-4-5-6-... 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-...-30-31-32 1-2-3-4-5-6-7-... 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-...-31-32-33 2-3-4-5-6-7-8-... 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-...-32-33-34 3-4-5-6-7-8-9-... 4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-...-33-34-35 4-5-6-7-8-9-10-... 5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 5-6-7-...-34-35-36 5-6-7-8-9-10-11... 6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 6-7-8-...-35-36-37 6-7-8-9-10-11-12... 7 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 7-8-9-...-36-37-38 7-8-9-10-11-12-13... ... ... ... ... 14 14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-...-43-44-45 14-15-16-17-18-19-20-... 15 15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-...-44-45-46 15-16-17-18-19-20-21-... ... ... ... 30 30-31-32-...-59-60-61 30-31-32-33-34-35-36-... 31 31-32-33-...-60-61-62 31-32-33-34-35-36-37-... Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The reduced-strength options are intended for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-strength option minimizes the noise generated on the data bus during READ operations. Full output drive strength should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are configured at half-drive strength during testing. See Table 5 for additional information. Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst length of 4, 8, 16, or 32 words. The device can also be set in continuous burst mode where data is accessed sequentially without regard to address boundaries; the internal address wraps to 000000h if the burst goes past the last address. Burst Wrap (BCR[3]) Default = No Wrap The burst-wrap option determines if a 4-, 8-, 16-, or 32-word READ or WRITE burst wraps within the burst length, or steps through sequential addresses. If the wrap option is not enabled, the device accesses data from sequential addresses without regard to burst boundaries; the internal address wraps to 000000h if the burst goes past the last address. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 5: Drive Strength BCR[5] BCR[4] DRIVE STRENGTH IMPEDANCE TYP () 0 0 Full 25-30 0 1 1/2 (default) 50 1 0 1/4 1 1 USE RECOMMENDATION CL = 30pF to 50pF CL = 15pF to 30pF 104 MHz at light load CL = 15pF or lower 100 Reserved Figure 19: WAIT Configuration (BCR[8] = 0) WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively (Figures 19 and 21). When A8 = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid (Figures 20 and 21). CLK WAIT DQ[15:0] High-Z Data[0] Data[1] Data immediately valid (or invalid) NOTE: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 21. Figure 20: WAIT Configuration (BCR[8] = 1) CLK WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state. WAIT D[15:0] High-Z Data[0] Data valid (or invalid) after one clock delay NOTE: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 21. Figure 21: WAIT Configuration During Burst Operation CLK BCR[8] = 0 Data valid in current cycle. WAIT BCR[8] = 1 Data valid in next cycle. WAIT DQ[15:0] D[0] D[1] D[2] D[3] DON'T CARE NOTE: Non-default BCR setting: WAIT active LOW. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Latency Counter (BCR[13:11]) Default = Three Clock Latency The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. For allowable latency codes, see Tables 6 and 7 and Figures 22 and 23). Fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency counter. The burst will pause (and WAIT will be asserted) at the boundary of a 128-word row. (See Table 7 and Figure 23 on page 25.) Initial Access Latency (BRC[14]) Default = Variable Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to detect delays caused by collisions with refresh operations. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 6: Variable Latency Configuration Codes LATENCY1 LATENCY BCR[13:11] CONFIGURATION CODE 010 011 Others MAX INPUT CLK FREQUENCY (MHz) REFRESH COLLISION NORMAL -701 -708 -856 40 (25ns) 66 (15ns) -- 2 (3 clocks) 2 4 66 (15ns) 54 (18.5ns) 3 (4 clocks)--default Reserved 3 -- 6 -- 104 (9.62ns) -- 80 (12.5ns) -- NOTE: 1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle. Figure 22: Latency Counter (Variable Initial Latency, No Refresh Collision) CLK A[22:0] ADV# VIH VIL VIH VIL VALID ADDRESS VIH VIL Code 2 DQ[15:0] VOH VALID OUTPUT VOL Code 3 DQ[15:0] VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT (Default) VOH VOL DON'T CARE 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 24 UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 7: Fixed Latency Configuration Codes BCR[13:11] 010 011 100 101 110 Others LATENCY CONFIGURATION CODE MAX INPUT CLK FREQUENCY (MHz) LATENCY COUNT (N) -701 -708 -856 2 (3 clocks) 3 (4 clocks)--default 4 (5 clocks) 5 (6 clocks) 6 (7 clocks) 2 3 4 5 6 33 (30ns) 52 (19.2ns) 66 (15ns) 75 (13.3ns) 33 (30ns) 52 (19.2ns) 66 (15ns) 75 (13.3ns) 80 (12.5ns) 20 (50ns) 33 (30ns) 40 (25ns) 52 (19.2ns) 66 (15ns) Reserved -- -- -- 104 (9.62ns)1 -- NOTE: 1. Fixed latency > 80 MHz available only with VCC/VCCQ from 1.8V-1.95V. Figure 23: Latency Counter (Fixed Latency) N-1 Cycles CLK A[22:0] ADV# CE# Cycle N VIH VIL VIH VIL tAA VALID ADDRESS tAADV VIH VIL tCO VIH VIL tACLK VOH VALID OUTPUT DQ[15:0] V (READ) OL tSP VOH Burst Identified (ADV# = LOW) VALID OUTPUT VALID OUTPUT VALID INPUT VALID INPUT VALID INPUT DON'T CARE 25 VALID OUTPUT tHD VALID INPUT DQ[15:0] V (WRITE) OL 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN VALID OUTPUT VALID INPUT UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Refresh Configuration Register Partial Array Refresh (RCR[2:0] Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 8 on page 27). The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Figure 24 describes the control bits used in the RCR. At power-up, the RCR is set to 0010h. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the register access software sequence with DQ = 0000h on the third cycle (see "Registers" on page 15.) Figure 24: Refresh Configuration Register Mapping A[22:20] A[19:18] 22-20 Reserved 19-18 Register Select All must be set to "0" RCR[19] RCR[18] A[17:8] 17-8 Reserved A6 A7 7 Page All must be set to "0" 6 A5 A4 5 4 DPD Reserved Setting is ignored (Default 00b) A3 A1 A2 3 0 Select RCR 1 0 Select BCR 0 1 Select DIDR RCR[7] Page Mode Disabled (default) 1 Page Mode Enable Read Configuration Register Must be set to "0" RCR[4] 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN Address Bus PAR 26 Refresh Coverage RCR[2] RCR[1] RCR[0] 0 0 0 Full array (default) 0 0 1 Bottom 1/2 array 0 1 0 Bottom 1/4 array 0 1 1 Bottom 1/8 array 1 0 0 None of array 1 0 1 Top 1/2 array 1 1 0 Top 1/4 array 1 1 1 Top 1/8 array Page Mode Enable/Disable 0 0 1 2 Reserved Register Select 0 A0 Deep Power-Down 0 DPD Enable 1 DPD Disable (default) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 8: 128Mb Address Patterns for PAR (RCR[4] = 1) RCR[2] RCR[1] RCR[0] ACTIVE SECTION ADDRESS SPACE SIZE DENSITY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die 000000h-7FFFFFh 000000h-3FFFFFh 000000h-1FFFFFh 000000h-0FFFFFh 0 400000h-7FFFFFh 600000h-7FFFFFh 700000h-7FFFFFh 8 Meg x 16 4 Meg x 16 2 Meg x 16 1 Meg x 16 0 Meg x 16 4 Meg x 16 2 Meg x 16 1 Meg x 16 128Mb 64Mb 32Mb 16Mb 0Mb 64Mb 32Mb 16Mb Page Mode Operation (RCR[7]) Default = Disabled The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default state, page mode is disabled. Deep Power-Down (RCR[4]) Default = DPD Disabled The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. Taking CE# LOW disables DPD and sets RCR[4] = 1; it is not necessary to write to the RCR to disable DPD. DPD can be enabled using CRE or the software sequence to access the RCR. Table 9: BIT FIELD Device Identification Register The DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. Table 9 describes the bit fields in the DIDR. This register is read-only, and is set to 0343h (see Table 9). The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the register access software sequence with DQ = 0002h on the third cycle. Device Identification Register Mapping DIDR[15] DIDR[14:11] DIDR[10:8] DIDR[7:5] DIDR[4:0] Reserved Device Version Device Density CellularRAM Generation Vendor ID Bit Setting 0b Bit Setting Version 0000b 1st 0001b 2nd 011b 010b 00011b Meaning -- 128Mb CellularRAM 1.5 Micron Field Name 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage to Any Ball Except VCC, VCCQ Relative to VSS 0.50V to (4.0V or VCCQ + 0.3V, whichever is less) Voltage on VCC Supply Relative to VSS . . -0.2V to +2.45V Voltage on VCCQ Supply Relative to VSS -0.2V to +2.45V Storage Temperature (plastic). . . . . . . . -55C to +150C Operating Temperature (case) Wireless. . . . . . . . . . . . . . . . . . . . . . . . . . -30C to +85C Industrial . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Soldering Temperature and Time 10s (solder ball only) . . . . . . . . . . . . . . . . . . . . . +260C Table 10: Electrical Characteristics and Operating Conditions Wireless Temperature (-30C < TC < +85C); Industrial Temperature (-40C < TC < +85C) DESCRIPTION Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Operating Current Asynchronous Random READ/ WRITE Asynchronous Page READ CONDITIONS IOH = -0.2mA IOL = +0.2mA VIN = 0 to VCCQ OE# = VIH or Chip Disabled SYMBOL VCC VCCQ VIH VIL VOH VOL ILI ILO VIN = VCCQ or 0V ICC1 Chip Enabled, IOUT = 0 ICC1P ICC2 Initial Access, Burst READ/WRITE Continuous Burst READ ICC3R Continuous Burst WRITE ICC3W Standby Current VIN = VCCQ or 0V CE# = VCCQ ISB W: 1.8V MIN MAX UNITS NOTES 1.7 1.7 VCCQ - 0.4 -0.20 0.80 VCCQ 1.95 1.95 VCCQ + 0.2 0.4 V V V V V V A A 1 2 3 3 mA 4 mA 4 mA 4 mA 4 mA 4 A 5 0.20 VCCQ 1 1 -70 -85 -70 -85 104 MHz 80 MHz 66 MHz 104 MHz 80 MHz 66 MHz 104 MHz 80 MHz 66 MHz Standard 30 25 15 12 40 35 30 25 20 18 40 35 30 200 Low-Power (L) 160 NOTE: 1. 2. 3. 4. Input signals may overshoot to VccQ + 1.0V for periods less than 2ns during transitions. Input signals may undershoot to Vss - 1.0V for periods less than 2ns during transitions. BCR[5:4] = 01b (default setting of one-half drive strength). This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 5. ISB (MAX) values measured with PAR set to FULL ARRAY and at +85C. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up, or after changes to the PAR array partition. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 11: Partial Array Refresh Specifications and Conditions DESCRIPTION CONDITIONS Partial Array Refresh Standby Current VIN = VCCQ or 0V, CE# = VCCQ SYMBOL IPAR ARRAY PARTITION MAX UNITS Full 1/2 1/4 1/8 0 Full 1/2 1/4 1/8 0 200 170 155 150 140 160 130 115 110 100 A Standard Power (no desig.) Low-Power Option (L) A NOTE: IPAR (MAX) values measured at 85C. IPAR might be slightly higher for up to 500ms after changes to the PAR array partition. Figure 25: Typical Refresh Current vs. Temperature (ITCR) 120 110 100 90 Current (A) 80 PAR = Full Array PAR = 1/2 of Array 70 PAR = 1/4 of Array 60 PAR = 1/8 of Array PAR = None of Array 50 40 30 20 10 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) Table 12: Deep Power-Down Specifications DESCRIPTION Deep Power-Down CONDITIONS VIN = VCCQ or 0V; VCC, VCCQ = 1.95V; +85C SYMBOL TYP MAX UNITS IZZ 3 25 A NOTE: Typical (TYP) IZZ value applies across all operating temperatures and voltages. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 13: Capacitance DESCRIPTION Input Capacitance Input/Output Capacitance (DQ) CONDITIONS SYMBOL MIN MAX UNITS NOTES TC = +25C; f = 1 MHz; VIN = 0V CIN CIO 2.0 3.5 6 6 pF pF 1 1 NOTE: 1. These parameters are verified in device characterization and are not 100% tested. Figure 26: AC Input/Output Reference Waveform VCCQ Input 1 2 VCCQ/2 VCCQ/2 Test Points 3 Output VSS NOTE: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2. Figure 27: AC Output Load Circuit Test Point 50 DUT VccQ/2 30pF NOTE: All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b). 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 14: Asynchronous READ Cycle Timing Requirements All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b). -701/708 MIN MAX -856 PARAMETER SYMBOL Address Access Time t MIN MAX UNITS NOTES ADV# Access Time t Page Access Time tAPA Address Hold from ADV# HIGH t AVH 2 2 ns Address Setup to ADV# HIGH t AVS 5 5 ns LB#/UB# Access Time t BA 70 85 ns LB#/UB# Disable to DQ High-Z Output tBHZ 8 8 ns 1 LB#/UB# Enable to Low-Z Output t ns 2 Maximum CE# Pulse Width tCEM 4 s 3 CE# LOW to WAIT Valid tCEW 7.5 ns Chip Select Access Time tCO 85 ns CE# LOW to ADV# HIGH tCVS Chip Disable to DQ and WAIT High-Z Output tHZ Chip Enable to Low-Z Output tLZ Output Enable to Valid Output tOE Output Hold from Address Change tOH Output Disable to DQ High-Z Output tOHZ Output Enable to Low-Z Output tOLZ 3 Page Cycle Time tPC READ Cycle Time tRC ADV# Pulse Width LOW tVP ADV# Pulse Width HIGH tVPH AA 70 85 ns AADV 70 85 ns 20 25 ns BLZ 10 10 4 1 7.5 1 70 7 7 8 10 ns 8 10 20 5 20 5 8 ns 1 ns 2 ns ns 8 ns 1 3 ns 2 20 25 ns 70 85 ns 5 7 ns 10 10 ns NOTE: 1. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 30. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 2. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 30. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 3. Page mode enabled only. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 15: Burst READ Cycle Timing Requirements All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b). -701 PARAMETER SYMBOL Address Access Time (Fixed Latency) t ADV# Access Time (Fixed Latency) t Burst to READ Access Time (Variable Latency) tABA CLK to Output Delay t ACLK Address Hold from ADV# HIGH (Fixed Latency) t AVH Burst OE# LOW to Output Delay t BOE MIN -708 MAX MAX UNITS AA 70 70 85 ns AADV 70 70 85 ns 35 46 55 ns 7 9 11 ns 2 MIN -856 2 20 5 CE# HIGH between Subsequent Burst or Mixed- tCBPH Mode Operations tCEM Maximum CE# Pulse Width tCEW CE# LOW to WAIT Valid 2 6 7.5 9.62 MIN 20 4 1 MAX 1 ns 20 8 4 7.5 12.5 1 ns ns 1 4 s 1 7.5 ns 15 ns CLK Period tCLK Chip Select Access Time (Fixed Latency) tCO CE# Setup Time to Active CLK Edge tCSP 3 4 5 ns Hold Time from Active CLK Edge tHD 2 2 2 ns Chip Disable to DQ and WAIT High-Z Output tHZ CLK Rise or Fall Time 70 70 85 ns 8 8 8 ns tKHKL 1.6 1.8 2.0 ns CLK to WAIT Valid tKHTL 7 9 11 ns CLK to DQ High-Z Output tKHZ 3 8 3 8 3 8 ns CLK to Low-Z Output tKLZ 2 5 2 5 2 5 ns Output HOLD from CLK tKOH 2 2 2 ns CLK HIGH or LOW Time tKP 3 4 5 ns Output Disable to DQ High-Z Output tOHZ Output Enable to Low-Z Output tOLZ 3 3 Setup Time to Active CLK Edge t 3 3 8 SP 8 NOTES 8 2 ns 2 3 ns 3 3 ns NOTE: 1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 30. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 30. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 16: Asynchronous WRITE Cycle Timing Requirements -701/708 PARAMETER SYMBOL Address and ADV# LOW Setup Time t 0 0 ns Address Hold from ADV# Going HIGH t 2 2 ns Address Setup to ADV# Going HIGH tAVS 5 5 ns Address Valid to End of WRITE t 70 85 ns LB#/UB# Select to End of WRITE t 70 85 ns CE# LOW to WAIT Valid t 1 CE# HIGH between Subsequent Async Operations t CPH 5 5 ns CE# LOW to ADV# HIGH tCVS 7 7 ns Chip Enable to End of WRITE tCW 70 85 ns Data Hold from WRITE Time tDH 0 0 ns Data WRITE Setup Time tDW 20 20 ns Chip Disable to WAIT High-Z Output tHZ Chip Enable to Low-Z Output tLZ 10 End WRITE to Low-Z Output tOW 5 ADV# Pulse Width tVP ADV# Pulse Width HIGH AS AVH AW BW CEW MIN MAX -856 7.5 MIN 1 8 MAX 7.5 8 UNITS NOTES ns ns 1 10 ns 2 5 ns 2 5 7 ns tVPH 10 10 ns ADV# Setup to End of WRITE tVS 70 85 ns WRITE Cycle Time tWC 70 85 ns WRITE to DQ High-Z Output tWHZ WRITE Pulse Width tWP 45 WRITE Pulse Width HIGH tWPH WRITE Recovery Time tWR 8 8 ns 1 55 ns 3 10 10 ns 0 0 ns NOTE: 1. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 30. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 2. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 30. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 3. WE# LOW time must be limited to tCEM (4s). 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 17: Burst WRITE Cycle Timing Requirements -701 MIN -708 PARAMETER SYMBOL Address and ADV# LOW setup time t AS 0 0 Address Hold from ADV# HIGH (Fixed Latency) t AVH 2 CE# HIGH between Subsequent Burst or MixedMode Operations t Maximum CE# Pulse Width CEM t CE# LOW to WAIT Valid CEW 5 tCBPH MAX MIN UNITS NOTES 0 ns 1 2 2 ns 6 8 ns 2 4 s 2 7.5 ns 4 1 7.5 -856 MAX MIN 4 1 7.5 1 MAX 9.62 12.5 15 ns CSP 3 4 5 ns Hold Time from Active CLK Edge tHD 2 2 2 ns Chip Disable to WAIT High-Z Output tHZ Last Clock to ADV# LOW tKADV CLK Rise or Fall Time tKHKL 1.6 1.8 2.0 ns Clock to WAIT Valid tKHTL 7 9 11 ns CLK HIGH or LOW Time tKP 3 4 5 ns Setup Time to Activate CLK Edge tSP 3 3 3 ns Clock Period tCLK CE# Setup to CLK Active Edge t 8 4 8 6 8 6 ns 3 ns NOTE: 1. tAS required if tCSP > 20ns. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 30. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Timing Diagrams Figure 28: Initialization Period Vcc (MIN) Vcc, VccQ = 1.7V tPU Device ready for normal operation Table 18: Initialization Timing Parameters -701/708 PARAMETER SYMBOL Initialization Period (required before normal operations) tPU 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 35 MIN MAX 150 -856 MIN MAX UNITS 150 s NOTE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 29: Asynchronous READ tRC VIH A[22:0] VALID ADDRESS VIL tAA ADV# VIH VIL tHZ CE# VIH VIL LB#/UB# tCO tBA VIH tBHZ VIL tOE OE# WE# tOHZ VIH VIL VIH VIL tBLZ tOLZ tLZ VOH DQ[15:0] High-Z VOL VALID OUTPUT tCEW tHZ VIH WAIT High-Z VIL High-Z DON'T CARE UNDEFINED Table 19: Asynchronous READ Timing Parameters -701/708 SYMBOL UNITS AA 85 ns t tBA 70 85 ns tLZ 8 8 ns t OE 20 20 ns ns tOHZ 8 8 ns 7.5 ns tOLZ 85 ns t BHZ tBLZ tCEW t 10 1 CO 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN MIN 10 7.5 70 1 SYMBOL 36 MIN MIN 8 HZ RC MAX -856 MAX t MAX -701/708 70 t MIN -856 10 MAX UNITS 8 ns 10 ns 3 3 ns 70 85 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 30: Asynchronous READ Using ADV# VIH A[22:0] VALID ADDRESS VIL tAA tAVS tVPH tAVH VIH ADV# VIL tAADV tVP tCVS tHZ VIH CE# VIL tCO tBA tBHZ VIH LB#/UB# VIL tOE tOHZ VIH OE# VIL VIH WE# tOLZ tBLZ VIL tLZ VOH DQ[15:0] High-Z VALID OUTPUT VOL tCEW tHZ VIH WAIT High-Z VIL High-Z DON'T CARE UNDEFINED Table 20: Asynchronous READ Timing Parameters Using ADV# -701/708 SYMBOL tAA tAADV MIN MAX -856 MIN -701/708 MAX UNITS SYMBOL 70 85 ns tCVS 70 85 ns tHZ AVH 2 2 ns t tAVS 5 5 ns tOE t tBA tBHZ tBLZ t CEW tCO 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN MAX 7 MIN MAX 7 8 10 UNITS ns 8 10 ns ns 20 20 ns 8 8 ns 70 85 ns tOHZ 8 8 ns tOLZ 3 3 ns ns tVP 5 7 ns 7.5 ns t 10 10 ns 85 ns 10 1 LZ MIN -856 10 7.5 70 1 37 VPH Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 31: Page Mode READ tRC A[22:4] VIH VALID ADDRESS VIL VIH A[3:0] ADV# VALID ADDRESS VIL VALID ADDRESS VALID ADDRESS tPC tAA VIH VALID ADDRESS VIL tCEM tCO VIH tHZ CE# VIL LB#/UB# tBA VIH tBHZ VIL tOHZ tOE VIH OE# VIL VIH WE# tOLZ tBLZ VIL VOH DQ[15:0] tAPA tOH tLZ VALID OUTPUT High-Z VOL VALID OUTPUT VALID OUTPUT tCEW tHZ VIH WAIT VALID OUTPUT High-Z VIL High-Z DON'T CARE UNDEFINED Table 21: Asynchronous READ Timing Parameters--Page Mode Operation -701/708 SYMBOL MIN MAX -856 MIN -701/708 MAX UNITS SYMBOL tAA 70 85 ns tHZ t 20 25 ns t 70 85 ns tOE 8 8 APA tBA tBHZ t BLZ 10 t CEW 1 tCO 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN ns tOH ns t 4 s tOLZ 7.5 ns t 85 ns 10 4 tCEM 7.5 70 1 LZ 38 MIN MAX -856 MIN 8 10 UNITS 8 ns 10 20 5 ns 20 5 8 OHZ MAX ns ns 8 ns 3 3 ns PC 20 25 ns tRC 70 85 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 32: Single-Access Burst READ Operation--Variable Latency tCLK tKP tKP VIH CLK VIL tKHKL A[22:0] tSP VIH tHD VALID ADDRESS VIL tHD tSP VIH ADV# VIL tHD tCEM CE# tCSP VIH tHZ tABA VIL tBOE tOHZ VIH OE# VIL tSP WE# tOLZ tHD VIH VIL tHD tSP VIH LB#/UB# VIL tCEW VOH WAIT tKHTL High-Z High-Z VOL DQ[15:0] tKOH tACLK VOH VALID OUTPUT High-Z VOL READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Table 22: Burst READ Timing Parameters--Single Access, Variable Latency -701 -708 -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS -708 -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS ABA 35 46 55 ns t tACLK 7 9 11 ns tKHKL BOE 20 20 20 ns t tCEM 4 4 4 s tKOH 2 2 2 ns 7.5 ns tKP 3 4 5 ns t t tCEW 1 7.5 1 7.5 1 HZ CLK 9.62 12.5 15 ns t OHZ t CSP 3 4 5 ns t OLZ tHD 2 2 2 ns tSP 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 39 8 8 ns 1.6 1.8 2.0 ns 11 ns 7 KHTL t 8 9 8 8 8 ns 3 3 3 ns 3 3 3 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 33: 4-Word Burst READ Operation--Variable Latency tKHKL CLK A[22:0] tKP VIL tHD tSP VIH VALID ADDRESS VIL tSP ADV# tKP tCLK VIH tHD VIH VIL tCEM CE# VIH tHD tABA tCSP VIL tCBPH tHZ tBOE OE# WE# LB#/UB# VIH VIL tOHZ tSP tHD tSP tHD tOLZ VIH VIL VIH VIL tKHTL tCEW WAIT VOH High-Z VOL High-Z tACLK DQ[15:0] VOH VALID OUTPUT High-Z VOL tKOH VALID OUTPUT VALID OUTPUT VALID OUTPUT READ Burst Identified (WE# = HIGH) UNDEFINED DON'T CARE NOTE: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Table 23: Burst READ Timing Parameters--4-Word Burst -701 SYMBOL -708 -856 -701 -708 -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS MIN MAX MIN MAX MIN MAX UNITS tABA 35 46 55 ns tHZ tACLK 7 9 11 ns tKHKL 20 20 20 ns t ns tKOH 2 2 2 ns 4 s t 3 4 5 ns 7.5 ns tOHZ t BOE tCBPH t 5 6 4 CEM 8 4 1 1 8 ns 1.6 1.8 2.0 ns 7 9 11 ns 1 tCLK 9.62 12.5 15 ns tOLZ 3 3 3 ns CSP 3 4 5 ns t 3 3 3 ns tHD 2 2 2 ns 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 7.5 KP 8 tCEW t 7.5 KHTL 8 40 SP 8 8 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 34: Single-Access Burst READ Operation--Fixed Latency tKP tCLK tKP VIH CLK A[22:0] VIL tKHKL tSP VIH VALID ADDRESS VIL tAVH tAA VIH ADV# tHD tSP VIL tAADV tHD tCEM CE# tHZ tCSP VIH VIL tCO tBOE tOHZ VIH OE# VIL tSP WE# tOLZ tHD VIH VIL tHD tSP VIH LB#/UB# VIL tCEW VOH WAIT tKHTL High-Z High-Z VOL DQ[15:0] tKOH VOH VALID OUTPUT High-Z VOL READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: Non-default BCR settings: Fixed latency; latency code four (five clocks); WAIT active LOW; WAIT asserted during delay. Table 24: Burst READ Timing Parameters--Single Access, Fixed Latency -701 SYMBOL -708 -856 -701 MIN MAX MIN MAX MIN MAX UNITS 70 70 85 ns t tAADV 70 70 85 ns tHZ ns tAVH 2 tBOE t CEM t CEW tCLK 1 CSP 2 2 HD 2 2 ns 8 8 8 ns tKHKL 1.6 1.8 2.0 ns 7 9 11 ns 20 20 20 ns tKHTL 4 4 4 s t 7.5 ns t ns tOHZ ns tOLZ 3 3 3 ns ns t 3 3 3 ns 7.5 9.62 1 7.5 12.5 70 tCO t 2 -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS t AA -708 3 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 1 15 70 4 85 5 41 KOH 2 2 2 ns KP 3 4 5 ns SP 8 8 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 35: 4-Word Burst READ Operation--Fixed Latency tKHKL CLK A[22:0] VIL tKP tSP VIH VALID ADDRESS VIL tAVH tSP ADV# tKP tCLK VIH tAA tHD VIH VIL tAADV tCEM CE# tHD tCSP VIH VIL tHZ tCO OE# WE# LB#/UB# tCBPH tBOE VIH VIL tSP tHD tSP tHD tOHZ tOLZ VIH VIL VIH VIL tKHTL tCEW WAIT VOH High-Z VOL High-Z tKOH DQ[15:0] VOH VALID OUTPUT High-Z VOL READ Burst Identified (WE# = HIGH) VALID OUTPUT VALID OUTPUT VALID OUTPUT tACLK DON'T CARE UNDEFINED NOTE: Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Table 25: Burst READ Timing Parameters--4-Word Burst, Fixed Latency -701 SYMBOL t AA ACLK tAVH CBPH tCLK 9.62 SYMBOL MIN MAX MIN MAX MIN MAX UNITS ns t CSP 3 4 5 ns 70 70 85 ns tHD 2 2 2 ns 7 9 11 ns t ns 2 6 1 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 8 ns tKHKL 1.6 1.8 2.0 ns ns tKHTL 7 9 11 ns ns t 2 2 2 ns 4 s tKP 3 4 5 ns 7.5 ns tOHZ ns tOLZ 3 3 3 ns ns tSP 3 3 3 ns 8 7.5 12.5 70 8 20 4 7.5 8 2 20 4 1 -856 85 5 tCEW -708 70 20 tCEM tCO -701 70 2 tBOE t -856 MIN MAX MIN MAX MIN MAX UNITS tAADV t -708 1 15 70 85 HZ KOH 42 8 8 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 36: 4-Word Burst READ Operation (with LB#/UB#) tCLK CLK VIH VIL tHD tSP A[22:0] VIH VALID ADDRESS VIL tHD tSP ADV# VIH VIL tCEM CE# tHD tCSP VIH VIL tCBPH tHZ tBOE OE# WE# LB#/UB# VIH VIL tOHZ tSP tHD tSP tHD tOLZ VIH VIL VIH VIL tCEW WAIT tKHTL VOH High-Z VOL High-Z tKOH tACLK DQ[15:0] VOH VALID OUTPUT High-Z VOL tKHZ tKHZ tKLZ VALID OUTPUT VALID OUTPUT High-Z READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: Non-default BCR settings: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst length four. Table 26: Burst READ Timing Parameters--4-Word Burst with LB#/UB# -701 SYMBOL MIN tACLK t BOE tCBPH -708 MAX MIN MAX MIN -701 MAX UNITS SYMBOL MIN -708 MAX MIN -856 MAX MIN MAX UNITS 7 9 11 ns tHZ 8 8 8 ns 20 20 20 ns t 7 9 11 ns ns tKHZ 3 8 3 8 3 8 ns 4 s tKLZ 2 5 2 5 2 5 ns 7.5 ns tKOH 2 5 6 4 tCEM -856 8 4 tCEW 1 tCLK 9.62 12.5 15 ns tOHZ CSP 3 4 5 ns t 3 3 3 ns tHD 2 2 2 ns tSP 3 3 3 ns t 7.5 1 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 7.5 1 KHTL OLZ 43 2 8 2 8 ns 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 37: READ Burst Suspend tCLK NOTE 2 VIH CLK VIL tSP VIH tHD VALID ADDRESS VALID ADDRESS A[22:0] VIL tHD tSP VIH ADV# VIL tCEM tCBPH tHZ tCSP VIH CE# VIL tOHZ OE# tSP VIH tOHZ NOTE 3 VIH VIL tHD WE# VIL tSP tHD VIH LB#/UB# VIL tBOE VOH tOLZ WAIT VOL High-Z High-Z tKOH tOLZ VOH DQ[15:0] VOL VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT tBOE VALID OUTPUT VALID OUTPUT VALID OUTPUT tACLK DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings for READ burst suspend: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. CLK can be stopped LOW or HIGH, but must be static, with no LOW-to-HIGH transitions during burst suspend. 3. OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data. Table 27: Burst READ Timing Parameters--Burst Suspend -701 SYMBOL tBOE CBPH t CSP -701 SYMBOL -708 -856 MIN MAX MIN MAX MIN MAX UNITS 7 9 11 ns tHD 20 20 20 ns tHZ ns t s tOHZ 3 3 3 ns 3 3 3 ns 5 6 4 tCEM tCLK -856 MIN MAX MIN MAX MIN MAX UNITS tACLK t -708 8 4 4 KOH 9.62 12.5 15 ns tOLZ 3 4 5 ns t 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 44 SP 2 2 8 2 2 8 2 8 ns 8 2 8 ns ns 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 38: Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for Variable Latency End-of-Row Condition CLK VIH VIL tCLK A[22:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH NOTE 2 VIL OE# VIH VIL WE# VIH VIL tKHTL tKHTL WAIT VOH NOTE 3 VOL DQ[15:0] VOH VALID OUTPUT VOL VALID OUTPUT VALID OUTPUT VALID OUTPUT tKOH tACLK End of Row DON'T CARE NOTE: 1. Non-default BCR settings for continuous burst READ, BCR[8] = 0: WAIT active LOW; WAIT asserted during delay. Do not cross row boundaries with fixed latency. 2. CE# must not remain LOW longer than tCEM. 3. WAIT asserts for anywhere from LC to 2LC cycles. LC = Latency Code (BCR[13:11]). Table 28: Burst READ Timing Parameters--BCR[8] = 0 -701 SYMBOL CLK -856 -701 MIN MAX MIN MAX MIN MAX UNITS 7 tACLK t -708 9.62 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 9 12.5 11 15 SYMBOL ns tKHTL ns t KOH 45 -708 -856 MIN MAX MIN MAX MIN MAX UNITS 7 2 9 2 11 2 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 39: CE#-Controlled Asynchronous WRITE tWC A[22:0] VIH VALID ADDRESS VIL tAW tWR tAS VIH ADV# VIL tCW CE# tCPH VIH VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP VIH WE# VIL tDH tDW DQ[15:0] IN VIH DQ[15:0] OUT VOH High-Z VIL tWHZ tLZ WAIT VALID INPUT VOL tCEW VIH tHZ High-Z VIL High-Z DON'T CARE Table 29: Asynchronous WRITE Timing Parameters--CE#-Controlled -701/708 SYMBOL MIN MAX -856 MIN -701/708 MAX UNITS SYMBOL MIN MAX -856 MIN UNITS 8 ns AS 0 0 ns t tAW 70 85 ns tLZ 10 10 ns tBW 70 85 ns tWC 70 85 ns ns t 45 55 10 10 ns 0 0 ns t t CEW 1 7.5 1 7.5 8 MAX HZ 5 5 ns tWP tCW 70 85 ns tWPH tDH 0 0 ns tWR tDW 20 20 ns 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 8 WHZ tCPH 46 8 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 40: LB#/UB#-Controlled Asynchronous WRITE tWC A[22:0] VIH VALID ADDRESS VIL tAW tAS ADV# CE# LB#/UB# OE# tWR VIH VIL tCW VIH VIL tBW VIH VIL VIH VIL tWP tWPH VIH WE# VIL tDW DQ[15:0] IN VIH DQ[15:0] OUT VOH High-Z VIL VALID INPUT tWHZ tLZ VOL tCEW WAIT tDH tHZ VIH High-Z VIL High-Z DON'T CARE Table 30: Asynchronous WRITE Timing Parameters--LB#/UB#-Controlled -701/708 SYMBOL MIN MAX -856 MIN -701/708 MAX UNITS SYMBOL MIN MAX -856 MIN UNITS 8 ns 0 ns tHZ AW 70 85 ns t LZ 10 10 ns tBW 70 85 ns tWC 70 85 ns ns tWHZ t tCEW 1 7.5 1 7.5 8 MAX 0 tAS 8 8 ns tCW 70 85 ns tWP 45 55 ns tDH 0 0 ns tWPH 10 10 ns 20 20 ns t 0 0 ns t DW 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 47 WR Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 41: WE#-Controlled Asynchronous WRITE tWC VIH A[22:0] VALID ADDRESS VIL tAW tWR VIH ADV# VIL tCW VIH CE# VIL tBW VIH LB#/UB# VIL VIH OE# VIL tAS tWP tWPH VIH WE# VIL tDH tDW VIH DQ[15:0] IN High-Z VIL VALID INPUT tOW tWHZ tLZ VOH DQ[15:0] OUT VOL tCEW tHZ VIH WAIT High-Z VIL High-Z DON'T CARE Table 31: Asynchronous WRITE Timing Parameters--WE#-Controlled -701/708 SYMBOL MIN MAX -856 MIN -701/708 MAX UNITS SYMBOL 0 0 ns tLZ AW 70 85 ns t tBW 70 85 tAS t tCEW t CW tDH t DW 1 7.5 1 7.5 MIN MAX -856 MIN MAX UNITS 10 10 ns OW 5 5 ns ns tWC 70 ns tWHZ 85 8 ns 8 ns 70 85 ns t WP 45 55 ns 0 0 ns tWPH 10 10 ns 20 20 ns t 0 0 ns tHZ 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 8 8 WR ns 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 42: Asynchronous WRITE Using ADV# A[22:0] VIH VALID ADDRESS VIL tAVS tVS tVPH ADV# tAVH tVP tAS VIH VIL tAS tAW tCW VIH CE# VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP WE# VIH VIL tDW DQ[15:0] VIH IN VIL DQ[15:0] VOH OUT VOL High-Z VALID INPUT tWHZ tLZ tOW tCEW WAIT tDH tHZ VIH High-Z VIL High-Z DON'T CARE Table 32: Asynchronous WRITE Timing Parameters Using ADV# -701/708 SYMBOL MIN MAX -856 MIN -701/708 MAX UNITS SYMBOL 0 0 ns t tAVH 2 2 ns tLZ tAVS 5 5 ns AW 70 85 tBW 70 85 t t AS tCEW 1 7.5 1 7.5 MIN MAX -856 MIN 8 HZ MAX UNITS 8 ns 10 10 ns tOW 5 5 ns ns t VP 5 7 ns ns tVPH 10 10 ns ns tVS 70 85 ns tCW 70 85 ns tWHZ tDH 0 0 ns tWP 45 55 ns 20 20 ns t 10 10 ns t DW 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 49 WPH 8 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 43: Burst WRITE Operation--Variable Latency Mode tCLK CLK tKP tKP tKHKL VIH VIL tSP A[22:0] tHD VIH VALID ADDRESS VIL tAS 3 ADV# VIL LB#/UB# tKADV tHD tSP VIH tAS3 tSP tHD VIH VIL tCEM CE# tCSP VIH tCBPH tHD VIL OE# VIH VIL tSP WE# tHD VIH VIL tKHTL tCEW tHZ VOH WAIT High-Z VOL High-Z NOTE 2 tHD tSP VIH DQ[15:0] D[1] VIL D[2] D[3] D[0] WRITE Burst Identified (WE# = LOW) DON'T CARE NOTE: 1. Non-default BCR settings for burst WRITE operation in variable latency mode: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst length four; burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]). 3. tAS required if tCSP > 20ns. Table 33: Burst WRITE Timing Parameters -701 SYMBOL -708 -856 -701 MIN MAX MIN MAX MIN MAX UNITS SYMBOL -708 -856 MIN MAX MIN MAX MIN MAX UNITS tAS 0 0 0 ns tHZ t 5 6 8 ns t 4 s tKHKL 1.6 1.8 2.0 ns 7.5 ns tKHTL 7 9 11 ns 3 4 5 ns 3 3 3 ns CBPH 4 tCEM 1 tCLK 9.62 12.5 15 ns tKP tCSP 3 4 5 ns tSP t 2 2 2 ns 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 1 7.5 1 KADV tCEW HD 7.5 4 50 8 4 8 6 8 6 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 44: Burst WRITE Operation--Fixed Latency Mode tCLK CLK tKP tKP tKHKL VIH VIL tSP A[22:0] VIH VALID ADDRESS VIL tAS3 ADV# VIH VIL LB#/UB# tAVH tSP tKADV tHD tAS3 tSP tHD VIH VIL tCEM CE# tCSP VIH tCBPH tHD VIL OE# VIH VIL tSP WE# tHD VIH VIL tKHTL tCEW tHZ VOH WAIT High-Z VOL High-Z NOTE 2 tSP tHD VIH DQ[15:0] D[1] VIL D[2] D[3] D[0] WRITE Burst Identified (WE# = LOW) DON'T CARE NOTE: 1. Non-default BCR settings for burst WRITE operation in fixed latency mode: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst length four; burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]). 3. tAS required if tCSP > 20ns. Table 34: Burst WRITE Timing Parameters -701 SYMBOL -708 -856 -701 MIN MAX MIN MAX MIN MAX UNITS -708 -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS tAS 0 0 0 ns tHD t AVH 2 2 2 ns t tCBPH 5 6 8 ns tKADV 4 s tKHKL 1.6 1.8 2.0 ns 7.5 ns tKHTL 7 9 11 ns 4 tCEM 4 1 4 6 ns 8 6 ns ns tCLK 9.62 12.5 15 ns tKP 3 4 5 ns 3 4 5 ns t 3 3 3 ns 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 7.5 HZ 2 8 1 CSP 1 2 8 tCEW t 7.5 2 SP 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 45: Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for Variable Latency End-of-Row Condition CLK VIH VIL tCLK A[22:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH NOTE 2 VIL VIH WE# VIL VIH OE# VIL tKHTL tKHTL WAIT VOH NOTE 3 VOL tSP tHD VIH DQ[15:0] VALID INPUT VALID INPUT VIL VALID INPUT VALID INPUT END OF ROW DON'T CARE NOTE: 1. Non-default BCR settings for continuous burst WRITE, BCR[8] = 0: WAIT active LOW; WAIT asserted during delay. Do not cross row boundaries with fixed latency. 2. CE# must not remain LOW longer than tCEM. 3. WAIT asserts for anywhere from LC to 2LC cycles. LC = Latency Code (BCR[13:11]). Table 35: Burst WRITE Timing Parameters--BCR[8] = 0 -701 -708 -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL tCLK 9.62 12.5 15 ns tKHTL tHD 2 2 2 ns tSP 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 52 -708 -856 MIN MAX MIN MAX MIN MAX UNITS 7 3 8 3 11 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 46: Burst WRITE Followed by Burst READ tCLK CLK VIH VIL A[22:0] VIH VIL ADV# VIH VIL tSP tSP tHD tSP tHD LB#/UB# tKADV OE# WE# WAIT tSP tHD tSP tHD VIH VIL tCSP CE# tHD VALID ADDRESS VALID ADDRESS tHD VIH VIL tCBPH NOTE 2 tCSP VIH VIL tOHZ tSP tHD VIH VIL tSP tHD VOH VOL tBOE High-Z tSP tHD DQ[15:0] VIH IN/OUT VIL tACLK VOH High-Z D[1] D[0] D[2] D[3] VOL High-Z tKOH VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings for burst WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. CE# can stay LOW between burst READ and burst WRITE operations, but CE# must not remain LOW longer than tCEM. Table 36: WRITE Timing Parameters--Burst WRITE Followed by Burst READ -701 SYMBOL t CBPH -708 -856 -701 MIN MAX MIN MAX MIN MAX UNITS 5 6 8 SYMBOL ns t HD -708 -856 MIN MAX MIN MAX MIN MAX UNITS 2 2 2 ns tCLK 9.62 20 12.5 20 15 20 ns tKADV 4 6 6 ns tCSP 3 20 4 20 5 20 ns tSP 3 3 3 ns Table 37: READ Timing Parameters--Burst WRITE Followed by Burst READ -701 SYMBOL t -708 -856 -701 MIN MAX MIN MAX MIN MAX UNITS ACLK tBOE SYMBOL -708 -856 MIN MAX MIN MAX MIN MAX UNITS 7 9 11 ns t HD 2 2 2 ns 20 20 20 ns tKOH 2 2 2 ns tCLK 9.62 12.5 15 ns tOHZ tCSP 3 4 5 ns tSP 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 53 8 3 8 3 8 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 47: Burst READ Interrupted by Burst READ or WRITE tCLK VIH CLK VIL tSP VIH A[22:0] VIL ADV# VIH VIL CE# VIH VIL WE# VIH VIL READ Burst interrupted with new READ or WRITE. See Note 2. tHD tSP VALID ADDRESS tSP tHD tSP tHD tCEM (Note 3) tCSP tHD tSP tHD tSP tHD WAIT tHD VALID ADDRESS VOH tBOE tBOE VOL High-Z tOHZ tOHZ OE# VIH 2nd Cycle READ VIL LB#/UB# VIH 2nd Cycle READ VIL tKOH tACLK High-Z DQ[15:0] OUT VOH 2nd Cycle READ VOL VALID OUTPUT tKOH VALID OUTPUT VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT tACLK OE# VIH 2nd Cycle WRITE VIL LB#/UB# VIH 2nd Cycle WRITE VIL tSP tHD DQ[15:0] IN VIH 2nd Cycle WRITE VIL High-Z D[0] D[1] D[2] D[3] DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings for burst READ interrupted by burst READ or WRITE: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision. 2. Burst interrupt shown on first allowable clock (i.e., after the first data received by controller). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM. Table 38: READ Timing Parameters--Burst WRITE Interrupted -701 SYMBOL BOE tCLK t CSP -856 -701 MIN MAX MIN MAX MIN MAX UNITS tACLK t -708 SYMBOL -708 -856 MIN MAX MIN MAX MIN MAX UNITS 7 9 11 ns tHD 2 2 2 ns 20 20 20 ns t 2 2 2 ns KOH 9.62 12.5 15 ns tOHZ 3 4 5 ns t 8 3 SP 8 3 8 3 ns ns Table 39: WRITE Timing Parameters--Burst WRITE Interrupted -701 -708 -856 -701 -708 -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL tCLK 9.62 20 12.5 20 15 20 ns tHD 2 2 2 ns tCSP 3 20 4 20 5 20 ns tSP 3 3 3 ns 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 54 MIN MAX MIN MAX MIN MAX UNITS Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 48: Burst WRITE Interrupted by Burst WRITE or READ-- Variable Latency Mode WRITE Burst interrupted with new WRITE or READ. See Note 2. tCLK VIH CLK VIL tSP tSP tHD A[22:0] VIH VIL ADV# VIH VIL CE# VIH VIL WE# VIH VIL tHD VALID ADDRESS VALID ADDRESS tSP tHD tKADV tSP tHD tCEM (NOTE 3) WAIT tCSP tHD tSP tHD tSP tHD VALID ADDRESS VOH High-Z VOL High-Z OE# VIH 2nd Cycle WRITE VIL tSP tHD LB#/UB# VIH 2nd Cycle WRITE VIL tSP tHD DQ[15:0] IN VIH 2nd Cycle WRITE VIL High-Z tSP D[0] tHD D[1] D[0] D[2] D[3] tOHZ tBOE OE# VIH 2nd Cycle READ VIL LB#/UB# VIH 2nd Cycle READ VIL DQ[15:0] OUT VOH 2nd Cycle READ VOL VOH VOL tKOH tACLK High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in variable latency mode: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision. 2. Burst interrupt shown on first allowable clock (i.e., after first data word written). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM. Table 40: WRITE Timing Parameters--Burst READ Interrupted -701 -708 -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL t CLK 9.62 20 12.5 20 15 20 ns t tCSP 3 20 4 20 5 20 ns tSP tHD 2 2 2 KADV -708 -856 MIN MAX MIN MAX MIN MAX UNITS 4 6 6 ns 3 3 3 ns ns Table 41: READ Timing Parameters--Burst READ Interrupted -701 -708 -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS tACLK tBOE SYMBOL -856 MIN MAX MIN MAX MIN MAX UNITS 7 9 11 ns tHD 2 2 2 ns 20 20 20 ns tKOH 2 2 2 ns CLK 9.62 12.5 15 ns t tCSP 3 4 5 ns tSP t -708 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 55 8 OHZ 3 8 3 8 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 49: Burst WRITE Interrupted by Burst WRITE or READ--Fixed Latency Mode WRITE Burst interrupted with new WRITE or READ. See Note 2. tCLK CLK VIH VIL A[22:0] VIH VIL tSP tSP VALID ADDRESS VALID ADDRESS tAVH tKADV tSP tHD tAVH tSP tHD ADV# VIH VIL tCEM (NOTE 3) tCSP VIH CE# VIL WE# WAIT tHD tSP tHD VIH VIL tSP tHD VALID ADDRESS VOH VOL High-Z High-Z OE# VIH 2nd Cycle WRITE VIL tSP tHD LB#/UB# VIH 2nd Cycle WRITE VIL tSP tHD DQ[15:0] IN VIH 2nd Cycle WRITE VIL High-Z tSP D[0] tHD D[0] D[1] D[2] D[3] tOHZ tBOE OE# VIH 2nd Cycle READ VIL LB#/UB# VIH 2nd Cycle READ VIL tKOH DQ[15:0] OUT VOH 2nd Cycle READ VOL VOH VOL High-Z VALID OUTPUT VALID OUTPUT tACLK VALID OUTPUT VALID OUTPUT DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in fixed latency mode: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Burst interrupt shown on first allowable clock (i.e., after first data word written). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM. Table 42: WRITE Timing Parameters--Burst READ Interrupted -701 -708 -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS tAVH 2 tCLK 9.62 20 12.5 20 15 3 20 4 20 5 t CSP 2 2 -708 -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS ns tHD 2 2 2 ns 20 ns tKADV 4 6 6 ns 20 ns t 3 3 3 ns SP Table 43: READ Timing Parameters--Burst READ Interrupted -701 -708 -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS tACLK tBOE -708 -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS 7 9 11 ns tHD 2 2 2 ns 20 20 20 ns tKOH 2 2 2 ns tCLK 9.62 12.5 15 ns tOHZ tCSP 3 4 5 ns tSP 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 56 8 3 8 3 8 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 50: Asynchronous WRITE Followed by Burst READ tCLK VIH CLK VIL VIH VIL VALID ADDRESS tAVS VALID ADDRESS tAVH tAW tWR tSP tVP VIH LB#/UB# VIL tVS tBW tHD tSP tHD tCVS tCW VIH VIL tHD VALID ADDRESS tVPH VIH ADV# VIL CE# tSP tWC tWC A[22:0] tCBPH tCSP NOTE 2 tAS tOHZ VIH OE# VIL tWC tAS VIH WE# VIL WAIT tWP tSP tHD tWPH tCEW VOH VOL tBOE DQ[15:0] VIH IN/OUT VIL High-Z VOH DATA DATA tDH VOL tDW High-Z tKOH tACLK VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. Table 44: WRITE Timing Parameters--Async WRITE Followed by Burst READ -701/708 SYMBOL MIN -856 MAX MIN -701/708 MAX UNITS SYMBOL AVH 2 2 ns t AS 0 0 ns t AVS 5 5 ns t tAW 70 85 ns t t t t MIN -856 MAX MIN MAX UNITS DW 20 20 VP 5 7 ns ns VPH 10 10 ns tVS 70 85 ns BW 70 85 ns t WC 70 85 ns tCVS 7 7 ns tWP 45 55 ns tCW 70 85 ns tWPH 10 10 ns 0 0 ns t 0 0 ns t DH WR Table 45: READ Timing Parameters--Async WRITE Followed by Burst READ -701 SYMBOL t MIN ACLK tBOE t CBPH tCEW t CLK -708 MAX MIN 9.62 MIN -701 MAX UNITS SYMBOL 7 9 11 ns t 20 20 20 ns 5 1 -856 MAX 6 7.5 1 12.5 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 8 7.5 1 15 7.5 MIN -708 MAX MIN -856 MAX MIN MAX UNITS CSP 3 4 5 ns tHD 2 2 2 ns ns t 2 2 2 ns tOHZ ns t 57 KOH SP 8 3 8 3 ns 8 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 51: Asynchronous WRITE (ADV# LOW) Followed By Burst READ CLK VIH VIL A[22:0] VIH VIL ADV# VIH VIL tCLK tWC LB#/UB# CE# OE# WE# WAIT DQ[15:0] IN/OUT tWC VALID ADDRESS tSP VALID ADDRESS tWR tAW tSP tBW VIH tHD VALID ADDRESS tHD tSP tHD VIL tCW VIH tCSP tCBPH VIL NOTE 2 tOHZ VIH tWC VIL VIH tSP tHD tWPH tWP VIL VOH tCEW tBOE VIH High-Z VIL DATA VOH DATA tDH VOL tDW High-Z tKOH VOL tACLK VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT UNDEFINED DON'T CARE NOTE: 1. Non-default BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. Table 46: Asynchronous WRITE Timing Parameters--ADV# LOW -701/708 SYMBOL MIN -856 MAX MIN tAW 70 85 t BW 70 85 -701/708 MAX UNITS SYMBOL MAX MIN MAX UNITS ns tWC 70 85 ns ns t WP 45 55 ns WPH 10 10 ns WR 0 0 ns CW 70 85 ns t t DH 0 0 ns t t DW 20 20 ns t MIN -856 Table 47: Burst READ Timing Parameters -701 SYMBOL MIN MIN CBPH 5 t CEW 1 9.62 -856 MAX MIN 9 20 BOE t tCLK MAX 7 tACLK t -708 7.5 1 12.5 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN MAX UNITS 11 20 6 -701 20 8 7.5 1 15 7.5 SYMBOL MIN ns tCSP 3 -708 MAX MIN -856 MAX 4 MIN MAX UNITS 5 ns ns t HD 2 2 2 ns ns t KOH 2 2 2 ns ns t OHZ ns tSP 58 8 3 8 3 8 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 52: Burst READ Followed by Asynchronous WRITE (WE#-Controlled) tCLK VIH CLK A[22:0] VIL tSP VIH VIL tSP VIH ADV# CE# tWC tHD VALID ADDRESS VALID ADDRESS tAW tHD VIL tHD tCBPH tHZ tCSP VIH tWR tCW NOTE 2 VIL tBOE tOHZ VIH OE# WE# tAS VIL tSP VIH tHD tOLZ tWP tWPH VIL tHD tSP VIH tBW LB#/UB# VIL tCEW VOH WAIT tKHTL tCEW High-Z High-Z VOL DQ[15:0] tHZ tKOH tACLK VOH VALID INPUT VALID OUTPUT High-Z VOL tDH tDW READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings for burst READ followed by asynchronous WE#-controlled WRITE: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. Table 48: Burst READ Timing Parameters -701 SYMBOL MIN -708 MAX MAX UNITS 9 11 ns t t 20 20 20 ns t 8 ns t 7 BOE CBPH 5 6 7.5 1 7.5 MAX KHTL ns tKOH 15 ns t t 3 4 5 ns t MIN 2 MAX MIN MAX UNITS 8 8 ns 9 11 ns 8 ns 2 2 8 OHZ ns 2 ns 8 3 SP -856 2 HZ 12.5 CSP 1 MIN 2 HD 9.62 CLK 7.5 8 SYMBOL t tCEW 1 MIN -708 7 t MAX -701 t ACLK MIN -856 3 3 ns Table 49: Asynchronous WRITE Timing Parameters--WE# Controlled -701/-708 SYMBOL tAS MIN MAX -856 MIN 0 -701/-708 MAX UNITS 0 ns SYMBOL tHZ MIN -856 MAX MIN 8 MAX 8 UNITS ns tAW 70 85 ns tWC 70 85 ns t 70 85 ns t WP 45 55 ns t 70 85 ns t WPH 10 10 ns t DH 0 0 ns t WR 0 0 ns tDW 20 20 ns BW CW 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 53: Burst READ Followed by Asynchronous WRITE Using ADV# CLK A[22:0] tCLK VIH VIL VIH tSP VIL ADV# CE# tHD VALID ADDRESS VALID ADDRESS tSP VIH tVPH tHD WE# tAVH tVS tVP VIL tAW tHD tCSP VIH tCBPH tAS tCW tHZ NOTE 2 VIL tOHZ tBOE VIH OE# tAVS VIL tSP VIH VIL VIH tHD tAS tOLZ tWP tHD tSP tWPH tBW LB#/UB# VIL tCEW VOH WAIT tKHTL tCEW High-Z VOL High-Z tACLK DQ[15:0] tHZ VOH tDH tDW VALID INPUT VALID OUTPUT High-Z VOL tKOH READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings for burst READ followed by asynchronous WRITE using ADV#: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. Table 50: Burst READ Timing Parameters -701 SYMBOL MIN MAX t ACLK tBOE t 5 tCEW 1 CBPH -708 MIN -856 MAX MAX UNITS 7 9 11 ns t 20 20 20 ns tHZ ns t ns tKOH 6 7.5 1 MIN -701 8 7.5 1 7.5 SYMBOL 9.62 12.5 15 ns t 3 4 5 ns t MIN 8 MAX 7 MAX UNITS 8 ns 2 ns 9 11 2 8 OHZ MIN 8 2 2 8 3 ns ns 8 3 SP -856 2 KHTL t CSP MAX 2 HD t CLK MIN -708 3 ns ns Table 51: Asynchronous WRITE Timing Parameters Using ADV# -701/-708 SYMBOL MIN -856 MAX MIN -701/-708 MAX UNITS SYMBOL MIN -856 MAX MAX 0 ns t t 2 2 ns t t 5 5 ns t 5 7 ns t AW 70 85 ns t 10 10 ns tBW 70 85 ns tVS 70 85 ns AVH AVS t CEW tCW t DH 1 7.5 7.5 8 HZ VP VPH ns 8 ns ns t WP 45 55 ns 70 85 ns tWPH 10 10 ns 0 0 ns 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 1 DW 20 UNITS 0 AS 20 MIN t 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 54: Asynchronous WRITE Followed by Asynchronous READ--ADV# LOW A[22:0] VIH VALID ADDRESS VIL VALID ADDRESS VALID ADDRESS tAA tWR tAW VIH ADV# LB#/UB# CE# VIL tBLZ tBW VIH tBHZ VIL tCPH tCW VIH VIL tHZ NOTE 1 tLZ OE# tOE VIH VIL tAS WE# tOHZ tWC tWPH tWP VIH VIL tHZ WAIT tHZ VOH VOL tOLZ tWHZ DQ[15:0] VIH IN/OUT VIL High-Z DATA VOH High-Z DATA VALID OUTPUT VOL tDW tDH UNDEFINED DON'T CARE NOTE: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval. Otherwise, tCPH is only required after CE#-controlled WRITEs. Table 52: WRITE Timing Parameters--ADV# LOW -701/-708 SYMBOL MIN MAX -856 MIN -701/-708 MAX UNITS SYMBOL MIN MAX -856 MIN MAX UNITS 8 ns AS 0 0 ns t tAW 70 85 ns tWC tBW 70 85 ns tWHZ 5 5 ns t WP 45 55 ns 70 85 ns tWPH 10 10 ns DH 0 0 ns t 0 0 ns tDW 20 20 ns t t CPH tCW t 8 HZ 70 WR 85 ns 8 8 ns Table 53: READ Timing Parameters--ADV# LOW -701/-708 SYMBOL MIN MAX tAA t BHZ tBLZ 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN MIN -701/-708 UNITS 70 85 ns tLZ 8 8 ns t OE 20 20 ns ns tOHZ 8 8 ns ns tOLZ 10 8 8 SYMBOL 61 MIN MAX -856 MAX 10 tHZ -856 10 3 MIN MAX 10 3 UNITS ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 55: Asynchronous WRITE Followed by Asynchronous READ VIH A[22:0] VALID ADDRESS VIL tAVS tVPH VIH ADV# VALID ADDRESS tAVH VALID ADDRESS tAA tWR tAW tVS tVP VIL LB#/UB# tBW tCVS VIH tBHZ tBLZ VIL tCW VIH CE# tHZ tCPH VIL NOTE 1 tAS tLZ tOHZ VIH OE# VIL tWC tAS VIH WE# tWP tOLZ tWPH VIL VOH WAIT VOL tOE tWHZ DQ[15:0] VIH IN/OUT VIL High-Z DATA VOH DATA VOL tDW tDH VALID OUTPUT High-Z UNDEFINED DON'T CARE NOTE: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval. Otherwise, tCPH is only required after CE#-controlled WRITEs. Table 54: WRITE Timing Parameters--Async WRITE Followed by Async READ -701/-708 SYMBOL MIN MAX -856 MIN -701/-708 MAX UNITS SYMBOL tAS 0 0 ns tDW tAVH 2 2 ns tVP tAVS 5 5 ns AW 70 85 tBW 70 t MIN MAX -856 MIN MAX UNITS 20 20 ns 5 7 ns tVPH 10 10 ns ns t VS 70 85 ns 85 ns tWC 70 85 ns CPH 5 5 ns t tCVS 7 7 ns tWP 45 55 ns tCW 70 85 ns tWPH 10 10 ns 0 0 ns t 0 0 ns t t DH 8 WHZ WR 8 ns Table 55: READ Timing Parameters--Async WRITE Followed by Async READ -701/-708 SYMBOL MIN MAX -856 MIN -701/-708 MAX UNITS SYMBOL tAA 70 85 ns tLZ tBHZ 8 8 ns tOE ns tOHZ ns t tBLZ t 10 HZ 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 10 8 8 OLZ 62 MIN MAX 10 -856 MIN 10 20 8 3 MAX 3 UNITS ns 20 ns 8 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 56: 54-Ball VFBGA 0.70 0.05 SEATING PLANE 0.10 C C SOLDER BALL MATERIAL: 96.5% Sn, 3% Ag, 0.5% Cu SOLDER BALL PAD: O 0.30 SOLDER MASK DEFINED SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC 3.75 0.75 TYP 54X O 0.37 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS O 0.35 BALL A1 ID BALL A1 ID 5.00 0.05 BALL A1 BALL A6 CL 6.00 10.00 0.10 3.00 0.05 0.75 TYP CL 1.875 0.05 1.00 MAX 4.00 0.05 8.00 0.10 NOTE: 1. All dimensions in millimeters; MAX/MIN, or typical, as noted. Data Sheet Designation: Preliminary This data sheet contains initial characterization limits, subject to change upon full characterization of production devices. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Infineon Technologies outside the U.S. All other trademarks are the property of their respective owners. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 63 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 8 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Revision History Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/04 * Initial release. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip Burst CellularRAM_128__2.fm - Rev. A 9/04 EN 64 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.