Precision, Ultralow Noise, RRIO,
Zero-Drift Op Amp
Data Sheet
ADA4528-1/ADA4528-2
Rev. F Document Feedback
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FEATURES
Low offset voltage: 2.5 µV maximum
Low offset voltage drift: 0.015 μV/°C maximum
Low noise
5.6 nV/√Hz at f = 1 kHz, AV = +100
97 nV p-p at f = 0.1 Hz to 10 Hz, AV = +100
Open-loop gain: 130 dB minimum
CMRR: 135 dB minimum
PSRR: 130 dB minimum
Unity-gain crossover: 4 MHz
Gain bandwidth product: 3 MHz at AV = +100
−3 dB closed-loop bandwidth: 6.2 MHz
Single-supply operation: 2.2 V to 5.5 V
Dual-supply operation: ±1.1 V to ±2.75 V
Rail-to-rail input and output
Unity-gain stable
APPLICATIONS
Thermocouple/thermopile
Load cell and bridge transducers
Precision instrumentation
Electronic scales
Medical instrumentation
Handheld test equipment
GENERAL DESCRIPTION
The ADA4528-1/ADA4528-2 are ultralow noise, zero-drift
operational amplifiers featuring rail-to-rail input and output
swing. With an offset voltage of 2.5 μV, offset voltage drift of
0.015 μV/°C, and typical noise of 97 nV p-p (0.1 Hz to 10 Hz,
AV = +100), the ADA4528-1/ADA4528-2 are well suited for
applications in which error sources cannot be tolerated.
The ADA4528-1/ADA4528-2 have a wide operating supply range
of 2.2 V to 5.5 V, high gain, and excellent CMRR and PSRR specifi-
cations, which make it ideal for applications that require precision
amplification of low level signals, such as position and pressure
sensors, strain gages, and medical instrumentation.
The ADA4528-1/ADA4528-2 are specified over the extended
industrial temperature range (−40°C to +125°C). The ADA4528-1
and ADA4528-2 are available in 8-lead MSOP and 8-lead LFCSP
packages.
For more information about the ADA4528-1/ADA4528-2,
see the AN-1114 Application Note, Lowest Noise Zero-Drift
Amplifier Has 5.6 nV/√Hz Voltage Noise Density.
PIN CONNECTION DIAGRAMS
NIC
1
–IN
2
+IN 3
V– 4
NIC
8
V+
7
OUT
6
NIC
5
NOTES
1. NI C = NO INTERNAL CONNECTION.
ADA4528-1
TOP VIEW
(No t t o Scal e)
09437-001
Figure 1. ADA4528-1 Pin Configuration, 8-Lead MSOP
09437-102
ADA4528-1
TOP VIEW
(No t t o Scal e)
3+IN
4V–
1NIC
2–IN
6OUT
5NIC
8NIC
7 V+
NOTES
1. NI C = NO INTERNAL CONNECT ION.
2. CO NNE CT THE E X P OSED P AD TO
V– OR LEAVE IT UNCONNECT E D.
Figure 2. ADA4528-1 Pin Configuration, 8-Lead LFCSP
For ADA4528-2 pin connections and for more information about
the pin connections for these products, see the Pin Configurations
and Function Descriptions section.
1
10
100
110 100 1k 10k 100k 1M 10M
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
09437-063
V
SY
= 5V
V
CM
= V
SY
/2
A
V
= 1
Figure 3. Voltage Noise Density vs. Frequency
Table 1. Analog Devices, Inc., Zero-Drift Op Amp Portfolio1
Type
Ultralow
Noise
Micropower
(<20 µA)
Low
Power
(<1 mA)
16 V
Operating
Voltage
30 V
Operating
Voltage
Single ADA4528-1
ADA4051-1 AD8628 AD8638 ADA4638-1
AD8538
Dual
ADA4051-2
AD8629
AD8639
AD8539
Quad
AD8630
1 See www.analog.com for the latest selection of zero-drift operational amplifiers.
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Connection Diagrams ............................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—2.5 V Operation ............................. 3
Electrical Characteristics—5 V Operation ................................ 4
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ............................7
Typical Performance Characteristics ..............................................9
Applications Information .............................................................. 19
Input Protection ......................................................................... 19
Rail-to-Rail Input and Output .................................................. 19
Noise Considerations ................................................................. 19
Comparator Operation .............................................................. 21
Printed Circuit Board Layout ................................................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
8/2017—Rev. E to Rev. F
Deleted CP-8-19 .................................................................. Universal
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
6/2017—Rev. D to Re v. E
Deleted CP-8-12 .................................................................. Universal
Added CP-8-19 ................................................................... Universal
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
5/2013—Rev. C to Rev. D
Added 8-Lead LFCSP Package (CP-8-11) ....................... Universal
Changes to Table 5 ............................................................................ 7
Added Figure 7, Renumbered Sequentially .................................. 8
Added Figure 62 and Figure 63 .................................................... 19
Changes to Comparator Operation Section, Figure 68,
Figure 69, Figure 70, and Figure 71 .............................................. 21
Changes to Figure 72 ...................................................................... 22
Added Figure 76 .............................................................................. 24
9/2012—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Added Comparator Operation Section ....................................... 21
Added Figure 65 to Figure 69; Renumbered Sequentially ........ 21
7/2012—Rev. A to Rev. B
Added ADA4528-2 ............................................................. Universal
Changes to Features Section, Figure 1, Figure 2, and Table 1 .... 1
Added Pin Connection Diagrams Section and Figure 3;
Renumbered Sequentially ................................................................ 1
Changes to Table 2 ............................................................................. 3
Changes to Table 3 ............................................................................. 5
Change to Endnote 1 of Table 4 and Thermal Resistance
Section ................................................................................................. 7
Added Pin Configurations and Function Descriptions Section,
Figure 4, Figure 5, and Table 6 ......................................................... 8
Added Figure 6 and Table 7 ............................................................. 9
Changes to Input Protection Section ........................................... 19
Changes to Source Resistance Section and
Caption of Figure 63 ...................................................................... 20
Changes to Residual Voltage Ripple Section and
Caption of Figure 64 ...................................................................... 21
Changes to Ordering Guide .......................................................... 22
9/2011—Rev. 0 to Rev. A
Added 8-Lead LFCSP_WD Package ................................ Universal
Changes to General Description Section ...................................... 1
Added Figure 2; Renumbered Sequentially ................................... 1
Changes to Offset Voltage, Offset Voltage Drift, Power Supply
Rejection Ratio, and Settling Time to 0.1% Parameters, Table 2 ... 3
Changes to Thermal Resistance Section and Table 5 ................... 5
Changes to Figure 41 and Figure 44............................................. 12
Changes to Figure 45 and Figure 48............................................. 13
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
1/2011—Revision 0: Initial Version
Data Sheet ADA4528-1/ADA4528-2
Rev. F | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
VSY = 2.5 V, VCM = VSY/2, TA = 25°C, unless otherwise specified.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS VCM = 0 V to 2.5 V 0.3 2.5 μV
−40°C ≤ TA ≤ +125°C, MSOP package 4 μV
−40°C ≤ TA ≤ +125°C, LFCSP package 4.3 μV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C, MSOP package 0.002 0.015 μV/°C
−40°C ≤ TA ≤ +125°C, LFCSP package 0.018 μV/°C
Input Bias Current IB 220 400 pA
−40°C ≤ TA ≤ +125°C 600 pA
Input Offset Current IOS 440 800 pA
−40°C ≤ TA ≤ +125°C 1 nA
Input Voltage Range 0 2.5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.5 V 135 158 dB
−40°C ≤ TA ≤ +125°C 116 dB
Open-Loop Gain AVO RL = 10 kΩ, VO = 0.1 V to 2.4 V 130 140 dB
−40°C ≤ TA ≤ +125°C 126 dB
ADA4528-1 RL = 2 kΩ, VO = 0.1 V to 2.4 V 125 132 dB
−40°C ≤ TA ≤ +125°C 121 dB
ADA4528-2 RL = 2 kΩ, VO = 0.1 V to 2.4 V 122 132 dB
−40°C ≤ TA ≤ +125°C 119 dB
Input Resistance
Differential Mode RINDM 225 kΩ
Common Mode RINCM 1 GΩ
Input Capacitance
Differential Mode CINDM 15 pF
Common Mode CINCM 30 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 2.49 2.495 V
−40°C ≤ TA ≤ +125°C 2.485 V
RL = 2 kΩ to VCM 2.46 2.48 V
−40°C ≤ T
A
≤ +125°C
2.44
V
Output Voltage Low VOL RL = 10 kΩ to VCM 5 10 mV
−40°C ≤ TA ≤ +125°C 15 mV
RL = 2 kΩ to VCM 20 40 mV
−40°C ≤ TA ≤ +125°C 60 mV
Short-Circuit Current ISC ±30 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = +10 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 2.2 V to 5.5 V 130 150 dB
−40°C ≤ TA ≤ +125°C 127 dB
Supply Current per Amplifier ISY IO = 0 mA 1.4 1.7 mA
−40°C ≤ TA ≤ +125°C 2.1 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, CL = 100 pF, AV = +1 0.45 V/μs
Settling Time to 0.1% tS VIN = 1.5 V step, RL = 10 kΩ, CL = 100 pF, AV = −1 7 µs
Unity-Gain Crossover UGC VIN = 10 mV p-p, RL = 10 kΩ, CL = 100 pF, AV = +1 4 MHz
Phase Margin ΦM VIN = 10 mV p-p, RL = 10 kΩ, CL = 100 pF, AV = +1 57 Degrees
Gain Bandwidth Product GBP VIN = 10 mV p-p, RL = 10 kΩ, CL = 100 pF, AV = +100 3 MHz
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 4 of 24
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
−3 dB Closed-Loop Bandwidth f−3dB VIN = 10 mV p-p, RL = 10 kΩ, CL = 100 pF, AV = +1 6.2 MHz
Overload Recovery Time RL = 10 kΩ, CL = 100 pF, AV = −10 50 μs
NOISE PERFORMANCE
Voltage Noise en p-p f = 0.1 Hz to 10 Hz, AV = +100 97 nV p-p
Voltage Noise Density en f = 1 kHz, AV = +100 5.6 nV/√Hz
f = 1 kHz, AV = +100, VCM = 2.0 V 5.5 nV/√Hz
Current Noise in p-p f = 0.1 Hz to 10 Hz, AV = +100 10 pA p-p
Current Noise Density
i
n
f = 1 kHz, A
V
= +100
0.7
pA/√Hz
ELECTRICAL CHARACTERISTICS—5 V OPERATION
VSY = 5 V, VCM = VSY/2, TA = 25°C, unless otherwise specified.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS VCM = 0 V to 5 V 0.3 2.5 μV
−40°C ≤ TA ≤ +125°C 4 μV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.002 0.015 μV/°C
Input Bias Current IB
ADA4528-1 90 200 pA
−40°C ≤ TA ≤ +125°C 300 pA
ADA4528-2 125 250 pA
−40°C ≤ TA ≤ +125°C 350 pA
Input Offset Current IOS
ADA4528-1 180 400 pA
−40°C ≤ TA ≤ +125°C 500 pA
ADA4528-2 250 500 pA
−40°C ≤ TA ≤ +125°C 600 pA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 137 160 dB
−40°C ≤ TA ≤ +125°C 122 dB
Open-Loop Gain AVO RL = 10 kΩ, VO = 0.1 V to 4.9 V 127 139 dB
−40°C ≤ T
A
≤ +125°C
125
dB
RL = 2 kΩ, VO = 0.1 V to 4.9 V 121 131 dB
−40°C ≤ TA ≤ +125°C 120 dB
Input Resistance
Differential Mode RINDM 190 kΩ
Common Mode RINCM 1 GΩ
Input Capacitance
Differential Mode CINDM 16.5 pF
Common Mode CINCM 33 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 4.99 4.995 V
−40°C ≤ TA ≤ +125°C 4.98 V
RL = 2 kΩ to VCM 4.96 4.98 V
−40°C ≤ TA ≤ +125°C 4.94 V
Output Voltage Low VOL RL = 10 kΩ to VCM 5 10 mV
−40°C ≤ TA ≤ +125°C 20 mV
RL = 2 kΩ to VCM 20 40 mV
−40°C ≤ TA ≤ +125°C 60 mV
Short-Circuit Current ISC ±40 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = +10 0.1 Ω
Data Sheet ADA4528-1/ADA4528-2
Rev. F | Page 5 of 24
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 2.2 V to 5.5 V 130 150 dB
−40°C ≤ TA ≤ +125°C 127 dB
Supply Current per Amplifier ISY IO = 0 mA 1.5 1.8 mA
−40°C ≤ TA ≤ +125°C 2.2 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, CL = 100 pF, AV = +1 0.5 V/μs
Settling Time to 0.1%
t
S
V
IN
= 4 V step, R
L
= 10 kΩ, C
L
= 100 pF, A
V
= −1
10
µs
Unity-Gain Crossover UGC VIN = 10 mV p-p, RL = 10 kΩ, CL = 100 pF, AV = +1 4 MHz
Phase Margin ΦM VIN = 10 mV p-p, RL = 10 kΩ, CL = 100 pF, AV = +1 57 Degrees
Gain Bandwidth Product GBP VIN = 10 mV p-p, RL = 10 kΩ, CL = 100 pF, AV = +100 3.4 MHz
−3 dB Closed-Loop Bandwidth f−3dB VIN = 10 mV p-p, RL = 10 kΩ, CL = 100 pF, AV = +1 6.5 MHz
Overload Recovery Time RL = 10 kΩ, CL = 100 pF, AV = −10 50 μs
NOISE PERFORMANCE
Voltage Noise en p-p f = 0.1 Hz to 10 Hz, AV = +100 99 nV p-p
Voltage Noise Density en f = 1 kHz, AV = +100 5.9 nV/√Hz
f = 1 kHz, AV = +100, VCM = 4.5 V 5.3 nV/√Hz
Current Noise in p-p f = 0.1 Hz to 10 Hz, AV = +100 10 pA p-p
Current Noise Density in f = 1 kHz, AV = +100 0.5 pA/√Hz
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 6 V
Input Voltage
±V
SY
± 0.3 V
Input Current1 ±10 mA
Differential Input Voltage ±VSY
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
1 The input pins have clamp diodes to the power supply pins. Limit the input
current to 10 mA or less whenever input signals exceed the power supply
rail by 0.3 V.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages using a
4-layer JEDEC board. The exposed pad of the LFCSP package is
soldered to the board.
Table 5. Thermal Resistance
Package Type θJA θJC Unit
8-Lead MSOP (RM-8) 142 45 °C/W
8-Lead LFCSP (CP-8-11) 83.5 48.51 °C/W
1 θJC is measured on the top surface of the package.
ESD CAUTION
Data Sheet ADA4528-1/ADA4528-2
Rev. F | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NIC
1
–IN
2
+IN 3
V– 4
NIC
8
V+
7
OUT
6
NIC
5
NOTES
1. NI C = NO INTERNAL CONNECTION.
ADA4528-1
TOP VIEW
(No t t o Scal e)
09437-001
Figure 4. ADA4528-1 Pin Configuration, 8-Lead MSOP
09437-102
ADA4528-1
TOP VIEW
(No t t o Scal e)
3+IN
4V–
1NIC
2–IN
6OUT
5NIC
8NIC
7 V+
NOTES
1. NI C = NO INTERNAL CONNECT ION.
2. CO NNE CT THE E X P OSED P AD TO
V– OR LEAVE IT UNCONNECT E D.
Figure 5. ADA4528-1 Pin Configuration, 8-Lead LFCSP
Table 6. ADA4528-1 Pin Function Descriptions
Pin No. Mnemonic Description
1, 5, 8 NIC No Internal Connection.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 V− Negative Supply Voltage.
6 OUT Output.
7
V+
Positive Supply Voltage.
EPAD Exposed Pad (LFCSP Only). Connect the exposed pad to V− or leave it unconnected.
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 8 of 24
OUT A 1
–IN A 2
+IN A 3
V– 4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4528-2
TOP VIEW
(Not to Scale)
09437-103
Figure 6. ADA4528-2 Pin Configuration, 8-Lead MSOP
09437-107
ADA4528-2
TOP VIEW
(Not to Scale)
3+IN A
4V–
1OUT A
2–IN A
6–IN B
5+IN B
8V+
7OUT B
NOTES
1. CONNECT THE EXPOSED PAD TO
V– OR LEAVE I T UNCONNECTE D.
Figure 7. ADA4528-2 Pin Configuration, 8-Lead LFCSP
Table 7. ADA4528-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 OUT A Output, Channel A.
2 −IN A Inverting Input, Channel A.
3 +IN A Noninverting Input, Channel A.
4 V− Negative Supply Voltage.
5 +IN B Noninverting Input, Channel B.
6 −IN B Inverting Input, Channel B.
7 OUT B Output, Channel B.
8 V+ Positive Supply Voltage.
EPAD Connect the exposed pad to V- or leave it unconnected.
Data Sheet ADA4528-1/ADA4528-2
Rev. F | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
–1.0 –0.6 00.6 1.0
NUMBER O F AMPLIFIE RS
V
OS
(µV)
–0.8 –0.4 0.2
–0.2 0.4 0.8
09437-002
V
SY
= 2.5V
V
CM
= V
SY
/2
Figure 8. Input Offset Voltage Distribution
0
10
20
30
40
50
60
0 9
6
312 15
NUMBER O F AMPLIFIERS
TCVOS (nV/°C)
VSY = 2.5V
VCM
= V
SY
/2
09437-003
Figure 9. Input Offset Voltage Drift Distribution
1.0
0.8
0.6
0.4
0
–0.4
–0.8
–1.0 00.5 2.5
V
OS
(µV)
V
CM
(V)
0.2
–0.2
–0.6
1.5
1.0 2.0
09437-004
V
SY
= 2.5V
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
100
90
80
70
60
50
40
30
20
10
0
NUMBER O F AMPLIFIE RS
–1.0 –0.6 00.6 1.0
VOS (µV)
–0.8 –0.4 0.2
–0.2 0.4 0.8
09437-005
VSY = 5V
VCM = VSY/2
Figure 11. Input Offset Voltage Distribution
096
312 15
TCV
OS
(nV/° C)
0
10
20
30
40
50
60
NUMBER O F AMPLIFIERS
V
SY
= 5V
V
CM = VSY/2
09437-006
Figure 12. Input Offset Voltage Drift Distribution
1.0
0.8
0.6
0.4
0
–0.4
–0.8
–1.0 0 1 5
0.2
–0.2
–0.6
3
24
09437-007
V
SY
= 5V
V
OS
(µV)
V
CM
(V)
Figure 13. Input Offset Voltage vs. Common-Mode Voltage
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 10 of 24
–400
–300
–100
–200
0
200
300
100
400
–50 –25 025 50 75 100 125
IB (p A)
TEMPERATURE (°C)
IB+
IB–
09437-008
VSY = 2.5V
VCM = VSY/2
Figure 14. Input Bias Current vs. Temperature
–600
–400
–200
0
200
400
600
00.5 1.0 1.5 2.0 2.5
IB (p A)
VCM (V)
+25°C
+125°C
+85°C
–40°C
VSY = 2.5V
09437-009
Figure 15. Input Bias Current vs. Common-Mode Voltage
0.001 1000.01 0.1 110
LO AD CURRE NT (mA)
VSY = 2.5V
–40°C
+25°C
+85°C
+125°C
10
1
100m
10m
1m
0.1m
OUTPUT VOLTAGE (VOL) TO SUPPLY RAIL (V)
09437-014
Figure 16. Output Voltage (VOL) to Supply Rail vs. Load Current
–400
–300
–100
–200
0
200
300
100
400
–50 –25 025 50 75 100 125
I
B
(p A)
TEMPERATURE (°C)
I
B
+
I
B
–
09437-110
V
SY
= 5V
V
CM
= V
SY
/2
Figure 17. Input Bias Current vs. Temperature
–800
–600
–400
–200
0
200
400
600
0 1 2 3 4 5
I
B
(p A)
V
CM
(V)
+125°C
V
SY
= 5V
09437-012
+25°C
+85°C
–40°C
Figure 18. Input Bias Current vs. Common-Mode Voltage
0.001 1000.01 0.1 110
LO AD CURRE NT (mA)
V
S
= 5V
–40°C
+25°C
+85°C
+125°C
10
1
100m
10m
1m
0.1m
OUTPUT VOLTAGE (V
OL
) TO SUPPLY RAIL (V)
09437-017
Figure 19. Output Voltage (VOL) to Supply Rail vs. Load Current
Data Sheet ADA4528-1/ADA4528-2
Rev. F | Page 11 of 24
10
1
100m
10m
1m
0.1m
0.001 1000.01
OUTPUT VOLTAGE (VOH
) TO SUPPLY RAIL (V)
0.1 110
LO AD CURRE NT (mA)
V
SY
= 2.5V
–40°C
+25°C
+85°C
+125°C
09437-010
Figure 20. Output Voltage (VOH) to Supply Rail vs. Load Current
0
5
10
15
20
25
–50 –25 025 50 75 100 125
OUTPUT VOLTAGE (V
OL
) TO SUPPLY RAI L (mV)
TEMPERATURE (°C)
R
L
= 2kΩ
R
L
= 10kΩ
09437-016
V
SY
= 2.5V
Figure 21. Output Voltage (VOL) to Supply Rail vs. Temperature
0
5
10
15
20
25
–50 –25 025 50 75 100 125
OUTPUT VOLTAGE (V
OH
) TO SUPPLY RAI L (mV)
TEMPERATURE (°C)
R
L
= 2kΩ
V
SY
= 2.5V
R
L
= 10kΩ
09437-015
Figure 22. Output Voltage (VOH) to Supply Rail vs. Temperature
0.001 100
0.01 0.1 110
LO AD CURRE NT (mA)
V
SY
= 5V
–40°C
+25°C
+85°C
+125°C
10
1
100m
10m
1m
0.1m
OUTPUT VOLTAGE (V
OH
) TO SUPPLY RAIL (V)
09437-013
Figure 23. Output Voltage (VOH) to Supply Rail vs. Load Current
0
5
10
15
20
25
30
35
40
45
OUTPUT VOLTAGE (V
OL
) TO SUPPLY RAIL (mV)
R
L
= 2kΩ
R
L
= 10kΩ
–50 –25 025 50 75 100 125
TEMPERATURE (°C)
V
SY
= 5V
09437-019
Figure 24. Output Voltage (VOL) to Supply Rail vs. Temperature
0
5
10
15
20
25
–50 –25 025 50 75 100 125
OUTPUT VOLTAGE (V
OH
) TO SUPPLY RAI L (mV)
TEMPERATURE (°C)
R
L
= 2kΩ
V
SY
= 5V
R
L
= 10kΩ
09437-117
Figure 25. Output Voltage (VOH) to Supply Rail vs. Temperature
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 12 of 24
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
ISY PER AMPLIFIE R ( mA)
VSY (V)
+125°C
–40°C
+85°C
+25°C
09437-021
Figure 26. Supply Current vs. Supply Voltage
–90
–45
0
45
90
135
–30
0
30
60
90
120
1k 10k 100k 1M 10M
PHASE ( Degrees)
OPEN-LOOP GAIN ( dB)
FREQUENCY (Hz)
VSY = 2.5V
RL = 10kΩ
CL = 100pF
09437-022
PHASE
GAIN
Figure 27. Open-Loop Gain and Phase vs. Frequency
–20
–10
0
10
20
30
40
50
60
10 100 1k 10k 100k 1M 10M
CLOSED-LOOP GAIN (d B)
FREQUENCY (Hz)
AV = 100
VSY = 2.5V
AV = 10
AV = 1
09437-026
Figure 28. Closed-Loop Gain vs. Frequency
1.0
1.2
1.4
1.6
1.8
2.0
–50 –25 025 50 75 100 125
ISY PER AMPLIFIE R ( mA)
TEMPERATURE (°C)
VSY = 5.0V
VSY = 2.5V
09437-024
Figure 29. Supply Current vs. Temperature
–90
–45
0
45
90
135
–30
0
30
60
90
120
1k 10k 100k 1M 10M
PHASE ( Degrees)
OPEN-LOOP GAIN ( dB)
FREQUENCY (Hz)
VSY = 5V
RL = 10kΩ
CL = 100pF
09437-025
PHASE
GAIN
Figure 30. Open-Loop Gain and Phase vs. Frequency
–20
–10
0
10
20
30
40
50
60
10 100 1k 10k 100k 1M 10M
CLOSED-LOOP GAIN (d B)
FREQUENCY (Hz)
AV = 100
VSY = 5V
AV = 10
AV = 1
09437-029
Figure 31. Closed-Loop Gain vs. Frequency
Data Sheet ADA4528-1/ADA4528-2
Rev. F | Page 13 of 24
0
20
40
60
80
100
120
140
160
100 1k 10k 100k 1M 10M
CMRR (dB)
FREQUENCY (Hz)
V
SY
= 2.5V
V
CM
= V
SY
/2
V
CM
= 1.1V
09437-126
Figure 32. CMRR vs. Frequency
–20
0
20
40
60
80
100
120
100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
PSRR+
PSRR–
09437-032
VSY = 2.5V
Figure 33. PSRR vs. Frequency
0.001
0.01
0.1
1
10
100
1k
100 1k 10k 100k 1M 10M
Z
OUT
(Ω)
FREQUENCY (Hz)
A
V
= 100
V
SY
= 2.5V
A
V
= 10
A
V
= 1
09437-027
Figure 34. Closed-Loop Output Impedance vs. Frequency
0
20
40
60
80
100
120
140
100 1k 10k 100k 1M 10M
CMRR (dB)
FREQUENCY (Hz)
VSY = 5V
VCM = VSY/2
09437-031
Figure 35. CMRR vs. Frequency
–20
0
20
40
60
80
100
120
100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
PSRR+
PSRR–
09437-035
VSY = 5V
Figure 36. PSRR vs. Frequency
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
A
V
= 100
V
SY
= 5V
A
V
= 10
A
V
= 1
09437-030
Z
OUT
(Ω)
0.001
0.01
0.1
1
10
100
1k
Figure 37. Closed-Loop Output Impedance vs. Frequency
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 14 of 24
TI ME (20µ s/DIV )
VOLTAGE ( 0.5V/ DIV)
V
SY
= ±1. 25V
V
IN
= 2V p-p
A
V
= 1
R
L
= 10kΩ
C
L
= 100pF
09437-034
Figure 38. Large Signal Transient Response
TIME (1µs/DIV)
VOLTAGE ( 50mV /DIV )
V
SY
= ±1. 25V
V
IN
= 100mV p - p
A
V
= 1
R
L
= 10kΩ
C
L
= 100pF
09437-038
Figure 39. Small Signal Transient Response
0
2
4
6
8
10
12
14
16
110 100 1000
OVERSHOOT (%)
LO AD CAPACITANCE (p F)
OS+
OS–
VSY = 2.5V
VIN = 100mV p-p
AV = 1
RL = 10kΩ
09437-033
Figure 40. Small Signal Overshoot vs. Load Capacitance
TI ME (20µ s/DIV )
VOLTAGE (1V/DIV)
V
SY
= ±2. 5V
V
IN
= 4V p-p
A
V
= 1
R
L
= 10kΩ
C
L
= 100pF
09437-037
Figure 41. Large Signal Transient Response
TIME (1µs/DIV)
VOLTAGE ( 50mV /DIV )
V
SY
= ±2. 5V
V
IN
= 100mV p - p
A
V
= 1
R
L
= 10kΩ
C
L
= 100pF
09437-041
Figure 42. Small Signal Transient Response
0
2
4
6
8
10
12
14
16
110 100 1000
OVERSHOOT (%)
LO AD CAPACITANCE (p F)
OS+
OS–
V
SY
= 5V
V
IN
= 100mV p - p
A
V
= 1
R
L
= 10kΩ
09437-036
Figure 43. Small Signal Overshoot vs. Load Capacitance
Data Sheet ADA4528-1/ADA4528-2
Rev. F | Page 15 of 24
TI ME (10µ s/DIV )
0.5
0
–0.5
INPUT VOLTAGE (V)
–1
0
1
2
OUTPUT VOLTAGE (V)
VSY = ± 1.25V
A
V
= –10
V
IN
= 187.5mV
R
L
= 10kΩ
C
L
= 100pF
09437-040
INPUT
OUTPUT
Figure 44. Positive Overload Recovery
TI ME (10µ s/DIV )
0.5
0
–0.5
INPUT VOLTAGE (V)
–2
–1
0
1
OUTPUT VOLTAGE (V)
VSY = ±1. 25V
AV = –10
VIN = 187.5mV
RL = 10kΩ
CL = 100pF
09437-039
INPUT
OUTPUT
Figure 45. Negative Overload Recovery
09437-044
TI ME (10µ s/DIV )
VOLTAGE (1V/DIV)
VSY = 2.5V
RL = 10kΩ
CL = 100pF
DUT A V = –1
INPUT
+7.5mV
0
–7.5mV
OUTPUT
ERROR BAND
POST GAIN = 5
Figure 46. Positive Settling Time to 0.1%
TI ME (10µ s/DIV )
0.5
0
–0.5
INPUT VOLTAGE (V)
–1
0
1
2
3
OUTPUT VOLTAGE (V)
V
SY
= ±2. 5V
A
V
= –10
V
IN
= 375mV
R
L
= 10kΩ
C
L
= 100pF
09437-043
INPUT
OUTPUT
Figure 47. Positive Overload Recovery
TI ME (10µ s/DIV )
0.5
0
–0.5
INPUT VOLTAGE (V)
–3
–2
–1
0
1
OUTPUT VOLTAGE (V)
VSY = ± 2.5V
A
V
= –10
V
IN
= 375mV
R
L
= 10kΩ
C
L
= 100pF
09437-042
INPUT
OUTPUT
Figure 48. Negative Overload Recovery
09437-047
TIME ( 10µ s/DIV )
VOLTAGE (2V/DIV)
VSY = 5V
RL = 10kΩ
CL = 100pF
DUT A V = –1
INPUT
+20mV
0
–20mV
OUTPUT
ERROR BAND
POST GAIN = 5
Figure 49. Positive Settling Time to 0.1%
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 16 of 24
09437-045
TIME ( 10µ s/DIV )
VOLTAGE (1V/DIV)
VSY = 2.5V
RL = 10kΩ
CL = 100pF
DUT A V = –1
INPUT
OUTPUT +7.5mV
0
–7.5mV
ERROR BAND
POST GAIN = 5
Figure 50. Negative Settling Time to 0.1%
1
10
100
110 100 1k 10k
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
V
SY
= 2.5V
A
V
= 100
V
CM
= V
SY
/2
09437-046
Figure 51. Voltage Noise Density vs. Frequency
0.1
1
10
110 100 1k 10k 100k
CURRENT NOIS E DE NS ITY (pA/√Hz)
FREQUENCY (Hz)
V
SY
= 2.5V
V
CM
= V
SY
/2
A
V
= 100
09437-150
Figure 52. Current Noise Density vs. Frequency
09437-048
TIME ( 10µ s/DIV )
VOLTAGE (2V/DIV)
VSY = 5V
RL = 10kΩ
CL = 100pF
DUT A V = –1
INPUT
+20mV
0
–20mV
OUTPUT
ERROR BAND
POST GAIN = 5
Figure 53. Negative Settling Time to 0.1%
1
10
100
110 100 1k 10k
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
V
SY
= 5V
A
V
= 100
V
CM
= V
SY
/2
09437-049
Figure 54. Voltage Noise Density vs. Frequency
0.1
1
10
110 100 1k 10k 100k
CURRENT NOIS E DE NS ITY (pA/√Hz)
FREQUENCY (Hz)
V
SY
= 5V
V
CM
= V
SY
/2
A
V
= 100
09437-153
Figure 55. Current Noise Density vs. Frequency
Data Sheet ADA4528-1/ADA4528-2
Rev. F | Page 17 of 24
TIME (1s/DIV)
INPUT VOLTAG E ( 20nV/ DIV)
09437-050
V
SY
= 2.5V
V
CM
= V
SY
/2
A
V
= 100
Figure 56. 0.1 Hz to 10 Hz Noise
0.001
0.01
0.1
10
1
0.001 0.01 0.1 110
THD + N ( %)
AMPLITUDE (V p-p)
V
SY
= 2.5V
A
V
= 1
f = 1kHz
R
L
= 10kΩ
09437-152
Figure 57. THD + N vs. Amplitude
0.001
0.01
0.1
1
10 100 1k 10k 100k
THD + N ( %)
FREQUENCY (Hz)
09437-056
VSY = 2.5V
AV = 1
RL = 10kΩ
80kHz LOW-PASS FI L T ER
VIN = 2V p-p
Figure 58. THD + N vs. Frequency
TIME (1s/DIV)
INPUT VOLTAG E ( 20nV/ DIV)
09437-053
V
SY
= 5V
V
CM
= V
SY
/2
A
V
= 100
Figure 59. 0.1 Hz to 10 Hz Noise
0.001
0.01
0.1
10
1
0.001 0.01 0.1 110
THD + N ( %)
AMPLITUDE (V p-p)
VSY = 5V
f = 1kHz
RL = 10kΩ
09437-155
AV = 1
Figure 60. THD + N vs. Amplitude
0.001
0.01
0.1
1
10 100 1k 10k 100k
THD + N ( %)
FREQUENCY (Hz)
09437-057
VSY = 5V
AV = 1
RL = 10kΩ
80kHz LOW-PASS FI L T ER
VIN = 2V p-p
Figure 61. THD + N vs. Frequency
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 18 of 24
–140
–120
–100
–80
–60
–40
–20
0
100 1k 10k 100k
CHANNEL SEPERATION (dB)
FREQUENCY (Hz)
V
IN
= 0.5V p-p
V
IN
= 1V p-p
V
IN
= 1.2V p-p
V
SY
= 2.5V
R
L
= 2kΩ
A
V
= –100
09437-262
Figure 62. Channel Separation vs. Frequency
–140
–120
–100
–80
–60
–40
–20
0
100 1k 10k 100k
CHANNEL SEPERATION (dB)
FREQUENCY (Hz)
V
IN
= 1V p-p
V
IN
= 2V p-p
V
IN
=2.4V p-p
V
SY
= 5V
R
L
= 2kΩ
A
V
= –100
09437-263
Figure 63.Channel Separation vs. Frequency
Data Sheet ADA4528-1/ADA4528-2
Rev. F | Page 19 of 24
APPLICATIONS INFORMATION
The ADA4528-1/ADA4528-2 are precision, ultralow noise,
zero-drift operational amplifiers that feature a patented chop-
ping technique. This chopping technique offers ultralow input
offset voltage of 0.3 µV typical and input offset voltage drift of
0.002 µV/°C typical.
Offset voltage errors due to common-mode voltage swings
and power supply variations are also corrected by the chopping
technique, resulting in a typical CMRR figure of 158 dB and a
PSRR figure of 150 dB at 2.5 V supply voltage. The ADA4528-1/
ADA4528-2 have low broadband noise of 5.6 nV/√Hz (at f =
1 kHz, AV = +100, and VSY = 2.5 V) with no 1/f noise component.
These features are ideal for amplification of low level signals in
dc or subhertz high precision applications.
For more information about the chopper architecture of the
ADA4528-1/ADA4528-2, see the AN-1114 Application Note,
Lowest Noise Zero-Drift Amplifier Has 5.6 nV/√Hz Voltage
Noise Density.
INPUT PROTECTION
The ADA4528-1/ADA4528-2 have internal ESD protection diodes
that are connected between the inputs and each supply rail. These
diodes protect the input transistors in the event of electrostatic
discharge and are reverse biased during normal operation. This
protection scheme allows voltages as high as approximately 300 mV
beyond the rails to be applied at the input of either terminal
without causing permanent damage (see Table 4 in the Absolute
Maximum Ratings section).
When either input exceeds one of the supply rails by more than
300 mV, the ESD diodes become forward biased and large amounts
of current begin to flow through them. Without current limiting,
this excessive fault current causes permanent damage to the device.
If the inputs are subjected to overvoltage conditions, insert a
resistor in series with each input to limit the input current to 10 mA
maximum. However, consider the resistor thermal noise effect
on the entire circuit.
For example, at a 5 V supply voltage, the broadband voltage noise
of the ADA4528-1/ADA4528-2 is approximately 6 nV/√Hz (at
unity gain). A 1 kΩ resistor has thermal noise of 4 nV/√Hz. Adding
a 1 kΩ resistor at the noninverting input pin increases the total
noise by 30% root sum square (rss).
RAIL-TO-RAIL INPUT AND OUTPUT
The ADA4528-1/ADA4528-2 feature rail-to-rail input and
output with a supply voltage from 2.2 V to 5.5 V. Figure 64
shows the input and output waveforms of the ADA4528-
1/ADA4528-2 configured as a unity-gain buffer with a supply
voltage of ±2.5 V and a resistive load of 10 kΩ. With an input
voltage of ±2.5 V, the ADA4528-1/ADA4528-2 allow the output
to swing very close to both rails. Additionally, the devices do
not exhibit phase reversal.
3
2
1
0
–1
–2
–3
VOLTAGE (V)
TI M E ( 200µs/DIV)
VIN
VOUT
VSY = ± 2.5V
AV = 1
RL = 10kΩ
09437-059
Figure 64. Rail-to-Rail Input and Output
NOISE CONSIDERATIONS
For more information about the noise characteristics of the
ADA4528-1/ADA4528-2, see the AN-1114 Application Note,
Lowest Noise Zero-Drift Amplifier Has 5.6 nV/√Hz Voltage Noise
Density.
1/f Noise
1/f noise, also known as pink noise or flicker noise, is inherent
in semiconductor devices and increases as frequency decreases.
At low frequency, 1/f noise is a major noise contributor and
causes a significant output voltage offset when amplified by the
noise gain of the circuit. However, the ADA4528-1/ADA4528-2
eliminate the 1/f noise internally, thus making these devices an
excellent choice for dc or subhertz high precision applications.
The 0.1 Hz to 10 Hz amplifier voltage noise is only 97 nV p-p
(AV = +100) at a supply voltage of 2.5 V.
The low frequency 1/f noise, which appears as a slow varying
offset to the ADA4528-1/ADA4528-2, is greatly reduced by
the chopping technique. This reduction in 1/f noise allows the
ADA4528-1/ADA4528-2 to have much lower noise at dc and
low frequency compared to standard low noise amplifiers that
are susceptible to 1/f noise. Figure 51 and Figure 54 show the
voltage noise density of the amplifier with no 1/f noise.
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 20 of 24
Source Resistance
With 5.6 nV/√Hz of broadband noise at 1 kHz (VSY = 2.5 V
and AV = +100), the ADA4528-1/ADA4528-2 are among the
lowest noise zero-drift amplifiers currently available in the
industry. Therefore, it is important to carefully select the input
source resistance to maintain a total low noise.
The total input referred broadband noise (en total) from any
amplifier is primarily a function of three types of noise: input
voltage noise, input current noise, and thermal (Johnson) noise
from the external resistors.
These uncorrelated noise sources can be summed up in a root
sum squared (rss) manner using the following equation:
en total = [en2 + 4 kTRS + (in × RS)2]1/2
where:
en is the input voltage noise of the amplifier (V/√Hz).
k is the Boltzmann’s constant (1.38 × 10−23 J/K).
T is the temperature in Kelvin (K).
RS is the total input source resistance (Ω).
in is the input current noise of the amplifier (A/√Hz).
The total equivalent rms noise over a specific bandwidth is
expressed as
en,rms = en total × √BW
where BW is the bandwidth in hertz.
This analysis is valid for broadband noise calculation. If the
bandwidth of concern includes the chopping frequency, more
complicated calculations must be made to include the effect of
the noise energy spectrum at the chopping frequency (see the
Residual Voltage Ripple section).
With a low source resistance of RS < 1 kΩ, the voltage noise
of the amplifier dominates. As source resistance increases, the
thermal noise of RS dominates. As the source resistance increases
further, where RS > 100 kΩ, the current noise becomes the main
contributor to the total input noise. A good selection table for low
noise op amps can be found in the AN-940 Application Note, Low
Noise Amplifier Selection Guide for Optimal Noise Performance.
Voltage Noise Density with Different Gain Configurations
Figure 65 shows the voltage noise density vs. closed-loop gain of a
zero-drift amplifier from a leading competitor. The voltage noise
density of the amplifier increases from 11 nV/√Hz to 21 nV/√Hz
as the closed-loop gain decreases from 1000 to 1.
24
20
16
12
8
4
0110 100 1000
09437-061
VOLTAGE NOISE DENSITY (nV/√Hz)
CLOSED-LOOP GAIN (V/V)
VSY = 5V
f = 100Hz
COMPETITOR A
Figure 65. Competitor A: Voltage Noise Density vs. Closed-Loop Gain
Figure 66 shows the voltage noise density vs. frequency of the
ADA4528-1/ADA4528-2 for three different gain configurations.
The ADA4528-1/ADA4528-2 offer a constant input voltage
noise density of 6 nV/√Hz to 7 nV/√Hz, regardless of the gain
configuration.
1
10
100
110 100 1k 10k
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
A
V
= 10
A
V
= 100
A
V
= 1
V
SY
= 5V
V
CM
= V
SY
/2
09437-062
Figure 66. Voltage Noise Density vs. Frequency with Different Gain
Configurations
Data Sheet ADA4528-1/ADA4528-2
Rev. F | Page 21 of 24
Residual Voltage Ripple
Although autocorrection feedback (ACFB) suppresses the chop-
ping related voltage ripple, higher noise spectrum exists at the
chopping frequency and its harmonics due to the remaining ripple.
Figure 67 shows the voltage noise density of the ADA4528-1/
ADA4528-2 configured in unity gain. A noise energy spectrum
of 50 nV/√Hz can be seen at the chopping frequency of 200 kHz.
This noise energy spectrum is significant when the op amp has a
closed-loop frequency that is higher than the chopping frequency.
1
10
100
110 100 1k 10k 100k 1M 10M
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
09437-063
VSY = 5V
VCM = VSY/2
A
V
= 1
Figure 67. Voltage Noise Density vs. Frequency
To further suppress the noise at the chopping frequency, it is
recommended that a post filter be placed at the output of the
amplifier. For more information about residual voltage ripple,
see the AN-1114 Application Note, Lowest Noise Zero-Drift
Amplifier Has 5.6 nV/√Hz Voltage Noise Density.
COMPARATOR OPERATION
Figure 68 shows the ADA4528-2 configured as a voltage
follower with an input voltage that is always kept at midpoint
of the power supplies. The same configuration is applied to the
unused channel. A1 and A2 indicate the placement of ammeters
to measure supply current. As shown in Figure 69, as expected,
in normal operating condition, ISY+ = ISY− = 3 mA for the dual
ADA4528-2 at 5 V of supplies.
A1
1kΩ
1kΩ
ISY+
+VSY
VOUT
–VSY
ISY–
A2
ADA4528-2
1/2
09437-065
Figure 68. Voltage Follower
09437-066
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
I
SY
PER DUALAMPLIFIER (mA)
V
SY
(V)
Figure 69. Supply Current vs. Supply Voltage (Voltage Follower)
Figure 70 and Figure 71 show the ADA4528-2 configured as
comparators, with 1kΩ resistors in series with the input pins.
Figure 72 shows the supply currents for both configurations.
Supply currents increase slightly to 3.2 mA per dual amplifier at
5 V of supplies.
V
OUT
A1
1kΩ
1kΩ
I
SY
+
+V
SY
–V
SY
I
SY
–
A2
ADA4528-2
1/2
09437-067
Figure 70. Comparator A
V
OUT
A1
1kΩ
1kΩ
I
SY
+
+V
SY
–V
SY
I
SY
–
A2
ADA4528-2
1/2
09437-068
Figure 71. Comparator B
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 22 of 24
09437-069
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
I
SY
PER DUALAMPLIFIE R ( mA)
V
SY
(V)
Figure 72. Supply Current vs. Supply Voltage (Comparator A and
Comparator B)
For more details on op amps as comparators, refer to the
AN-849 Application Note, Using Op Amps as Comparators.
PRINTED CIRCUIT BOARD LAYOUT
The ADA4528-1/ADA4528-2 are high precision devices with
ultralow offset voltage and noise. Therefore, care must be taken
in the design of the printed circuit board (PCB) layout to achieve
the optimum performance of the ADA4528-1/ADA4528-2 at
board level.
To avoid leakage currents, keep the surface of the board clean
and free of moisture. Coating the board surface creates a barrier
to moisture accumulation and reduces parasitic resistance on
the board.
To minimize power supply disturbances caused by output current
variation, properly bypass the power supplies and keep the supply
traces short. Connect bypass capacitors as close as possible to the
device supply pins.
Stray capacitances are a concern at the outputs and the inputs of
the amplifier. It is recommended that signal traces be kept at a
distance of at least 5 mm from supply lines to minimize coupling.
A potential source of offset error is the Seebeck voltage on the
circuit board. The Seebeck voltage occurs at the junction of two
dissimilar metals and is a function of the temperature of the
junction. The most common metallic junctions on a circuit
board are solder-to-board trace and solder-to-component lead.
Figure 73 shows a cross section of a surface-mount component
soldered to a PCB. A variation in temperature across the board
(where TA1 ≠ TA2) causes a mismatch in the Seebeck voltages at
the solder joints, thereby resulting in thermal voltage errors
that degrade the ultralow offset voltage performance of the
ADA4528-1/ADA4528-2.
SOLDER
+
+
+
+
COMPONENT
LEAD
COPPER
TRACE
V
SC1
V
TS1
T
A1
SURFACE-MOUNT
COMPONENT
PC BOARD
T
A2
V
SC2
V
TS2
IF T
A1
≠ T
A2
, THEN
V
TS1
+ V
SC1
≠ V
TS2
+ V
SC2
09437-154
Figure 73. Mismatch in Seebeck Voltages Causes
Seebeck Voltage Error
To minimize these thermocouple effects, orient resistors so that
heat sources warm both ends equally. Where possible, the input
signal paths must contain matching numbers and types of com-
ponents to match the number and type of thermocouple junctions.
For example, dummy components, such as zero value resistors, can
be used to match the thermoelectric error source (real resistors
in the opposite input path). Place matching components in close
proximity and orient them in the same manner to ensure equal
Seebeck voltages, thus canceling thermal errors. Additionally, use
leads of equal length to keep thermal conduction in equilibrium.
Keep heat sources on the PCB as far away from the amplifier
input circuitry as practical.
It is highly recommended that a ground plane be used. A ground
plane helps to distribute heat throughout the board, maintains a
constant temperature across the board, and reduces EMI noise
pickup.
Data Sheet ADA4528-1/ADA4528-2
Rev. F | Page 23 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 74. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.44
2.34
2.24
0.30
0.25
0.20
PIN 1 INDEX
AREA
0.80
0.75
0.70
1.70
1.60
1.50
0.203 REF
0.05 M AX
0.02 NO M
0.50 BSC
3.10
3.00 SQ
2.90
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229- W3030D-4
0.20 M IN
8
1
5
4
PKG-005136
02-10-2017-C
SEATING
PLANE
TOP VIEW
SIDE VIEW
EXPOSED
PAD
BOTTOM VI EW
FOR PROP E R CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTIO N DE S CRIPT IONS
SECTION OF THIS DATA SHEET
PIN 1
INDIC ATOR AREA OPTI ONS
(SEE DETAIL A)
1
DETAIL A
(JEDEC 95)
Figure 75. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-11)
Dimensions shown in millimeters
ADA4528-1/ADA4528-2 Data Sheet
Rev. F | Page 24 of 24
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
ADA4528-1ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2R
ADA4528-1ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2R
ADA4528-1ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2R
ADA4528-1ACPZ-R2 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A2R
ADA4528-1ACPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A2R
ADA4528-1ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A2R
ADA4528-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A32
ADA4528-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A32
ADA4528-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A32
ADA4528-2ACPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A32
ADA4528-2ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A32
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D09437-0-8/17(F)