11/17/04
Benefits
lImproved Gate, Avalanche and Dynamic dV/dt
Ruggedness
lFully Characterized Capacitance and Avalanche
SOA
lEnhanced body diode dV/dt and dI/dt Capability
PD-95935A
www.irf.com 1
TO-220AB
IRFB3507PbF
IRFB3507PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
l Lead-Free
S
D
G
V
DSS
75V
R
DS(on)
typ.
7.0m
:
max. 8.8m
:
I
D
97A
GDS
Absolute Maximum Ratings
Symbol Parameter Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
IDM Pulsed Drain Current
d
PD @TC = 25°C Maximum P owe r Dissi pa ti o n W
Linear Derating Factor W/°C
VGS Gate-to-Source Voltage V
dv/dt Peak Diode Recov ery
f
V/ns
TJ Operating Junction and °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 s econds
(1 .6 m m from case )
Mounting tor que, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited)
Single Pul se Aval anche Energy
e
mJ
IAR
Avalanche Current
c
A
EAR
Repetitive Avalanche Energy
g
mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to- Case
j
––– 0.77
RθCS Case-to-Sink , Flat Greased Surface , TO-220 0.50 ––– °C/W
RθJA Junction-to- Ambient, TO-220
j
––– 62
280
See Fig. 14, 15, 16a, 16b
190
5.0
-55 to + 175
± 20
1.3
10lb
x
in (1.1N
x
m)
300
Max.
97
c
69
c
390
http://store.iiic.cc/
IRFB3507PbF
2www.irf.com
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.17mH,
RG = 25Ω, IAS = 58A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 58A, di/dt ≤ 390A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
S
D
G
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
Rθ is measured at TJ approximately 90°C.
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Units
V
(BR)DSS
Drain-to- Source Breakdown Voltage
75
–––
–––
V
∆
V
(BR)DSS
/
∆
T
J
Breakdown Voltage Temp. Coefficient
–––
0.070
–––
V/°C
R
DS(on)
Static Drai n-to-Source On-Resistance
–––
7.0
8.8
mΩ
V
GS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
I
DSS
Drain-to- Source Leakage Current
–––
–––
20
µA
–––
–––
250
I
GSS
Gate-to- Source Forward Leakage
–––
–––
200
nA
Gate-to- Source Reverse Leakage
–––
–––
-200
R
G
Gate Input Resistance
–––
1.3
–––
Ω
f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Units
gfs
Forward Transconductance
86
–––
–––
S
Q
g
Total Gate Charge
–––
88
130
nC
Q
gs
Gate-to- Source Charge
–––
24
–––
Q
gd
Gate-t o-Dr ain ("Miller") Charge
–––
36
–––
t
d(on)
Turn-On Delay Time
–––
20
–––
ns
t
r
Rise Time
–––
81
–––
t
d(off)
Turn-Of f Delay Time
–––
52
–––
t
f
Fall Time
–––
49
–––
C
iss
Input Capacitance
–––
3540
–––
pF
C
oss
Output Capacitance
–––
340
–––
C
rss
Reverse Transfer Capacitance
–––
210
–––
C
oss
eff. (ER)
Effective Output Capacitance (Energy Related)
–––
460
–––
C
oss
eff. (TR)
Effective Output Capacitance (Time Related)
h
–––
520
–––
Diode Charac teristics
Symbol
Parameter
Min.
Typ.
Max.
Units
I
S
Continuous Source Current
–––
–––
97
c
A
(Body Diode)
I
SM
Pulsed Source Current
–––
–––
390
A
(Body Diode)
d
V
SD
Diode Forward Voltage
–––
–––
1.3
V
t
rr
Reverse Recovery Time
–––
37
56
ns
T
J
= 25°C
V
R
= 64V,
–––
45
68
T
J
= 125°C
I
F
= 58A
Q
rr
Reverse Recovery Charge
–––
32
48
nC
T
J
= 25°C
di/dt = 100A/µs
g
–––
51
77
T
J
= 125°C
I
RRM
Reverse Recovery Current
–––
1.7
–––
A
T
J
= 25°C
t
on
Forward Turn-On Time
Intrinsic turn-on time is negli gible (turn-on is dominated by LS+LD)
Conditions
VDS = 50V, ID = 58A
ID = 58A
VGS = 20V
VGS = -20V
MOSFET symbol
showing t he
VDS = 60V
Conditions
VGS = 10V
g
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V
i
, See Fig.11
VGS = 0V, VDS = 0V to 60V
h
, See Fig. 5
TJ = 25°C, IS = 58A, VGS = 0V
g
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
d
VGS = 10V, ID = 58A
g
VDS = VGS, ID = 100µA
VDS = 75V, VGS = 0V
VDS = 75V, VGS = 0 V, T J = 125°C
ID = 58A
RG = 5.6Ω
VGS = 10V
g
VDD = 48V
http://store.iiic.cc/
IRFB3507PbF
www.irf.com 3
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1 110 100 1000
VDS, Drain-to-Source Voltage ( V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
≤60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100 1000
VDS, Drain-to-Source Voltage ( V)
1
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
2 4 6 8 10
VGS, Gate-to-Source Voltage ( V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 175°C
VDS = 25V
≤60µs PU LSE W IDT H
-60 -40 -20 020 40 60 80 100120140160180
TJ , Junct ion Temperature ( °C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 97A
VGS = 10V
110 100
VDS, Dr ain-t o-Source Volt age (V)
100
1000
10000
100000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 20406080100
QG Total Gate Char ge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VGS, Gate-to-Source Voltage (V)
VDS= 60V
VDS= 38V
VDS= 15V
ID= 58A
http://store.iiic.cc/
IRFB3507PbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
0.0 0.4 0.8 1.2 1.6 2.0
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
25 50 75 100 125 150 175
TC , Case Temper ature (°C)
0
20
40
60
80
100
ID, Drain Current (A)
Lim ited B y Package
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Temperature ( °C )
70
75
80
85
90
95
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
0 1020304050607080
VDS, Drai n-to-Source Voltage ( V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Energy (µJ)
25 50 75 100 125 150 175
Starting TJ , Junction T em perature ( °C)
0
200
400
600
800
1000
1200
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 8.9 A
12A
BOTTOM58A
1 10 100 1000
VDS, Drain-to-Source Voltage ( V)
0.01
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
Tc = 25°C
Tj = 175°C
Single P ulse
100µsec
1msec
10msec
DC
http://store.iiic.cc/
IRFB3507PbF
www.irf.com 5
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1E-006 1E-005 0.0001 0.001 0.01 0.1 1
t1 , R ectangular Pulse D ur ation ( sec)
0.0001
0.001
0.01
0.1
1
10
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthj c + Tc
Ri (°C/W) τi (sec)
0.2963 0.000504
0.4738 0.013890
τJ
τJ
τ1
τ1τ2
τ2
R1
R1R2
R2
τ
τ
C
Ci= i/Ri
Ci= τi/Ri
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
1000
Avalanche Current (A)
0.05
Dut y Cycle = Single Puls e
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses
0.01
25 50 75 100 125 150 175
Starting TJ , Juncti on Temperature (°C)
0
50
100
150
200
250
300
EAR , Avalanche Energy (mJ)
TOP Sing le Pulse
BOTTOM 1% Duty Cycle
ID = 58A
http://store.iiic.cc/
IRFB3507PbF
6www.irf.com
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temper ature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VGS(th) Gate threshold Voltage (V)
ID = 100µA
ID = 250µA
ID = 1.0mA
ID = 1.0A
100 200 300 400 500 600 700 800 900 1000
dif/dt (A/µs)
0
2
4
6
8
10
12
14
IRRM (A)
IF = 19A
VR = 64V
TJ = 25°C _____
TJ = 125°C ----------
100 200 300 400 500 600 700 800 900 1000
dif/dt (A/µs)
0
2
4
6
8
10
12
14
IRRM (A)
IF = 39A
VR = 64V
TJ = 25°C _____
TJ = 125°C ----------
100 200 300 400 500 600 700 800 900 1000
dif/dt (A/µs)
0
50
100
150
200
250
300
350
Qrr (nC)
IF = 19A
VR = 64V
TJ = 25°C _____
TJ = 12 5°C ----------
100 200 300 400 500 600 700 800 900 1000
dif/dt (A/µs)
0
50
100
150
200
250
300
Qrr (nC)
IF = 39A
VR = 64V
TJ = 25°C _____
TJ = 125°C ----------
http://store.iiic.cc/
IRFB3507PbF
www.irf.com 7
Fig 22a. Switching Time Test Circuit Fig 22b. Switching Time Waveforms
VGS
VDS
9
0%
10%
td(on) td(off)
trtf
VGS
Pulse W idth < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 23a. Gate Charge Test Circuit Fig 23b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
1K
VC
C
DUT
0
L
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
http://store.iiic.cc/
IRFB3507PbF
8www.irf.com
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 11/04
TO-220AB packages are not recommended for Surface Mount Application.
TO-220AB Part Marking Information
EXAMPLE:
IN THE ASSEMBLY LINE "C"
THIS IS AN IRF1 010
LOT CODE 1789
ASSEMBLED ON WW 19, 1997 PART NUMB E
R
ASSEMBLY
LOT CODE
DATE CODE
YEAR 7 = 1997
LINE C
WEEK 1 9
LOGO
RECTIFIER
INTERNATIONAL
Note: "P" in assembly line
position indicates "Lead-Free"
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
http://store.iiic.cc/
