Enpirion® Power Evaluation Board User Guide
EN6337QI/EN6347QI PowerSoC
Enpirion EN6337QI/EN6347QI DC-DC C onver ter
w/Integrated Inductor Eval uation Board
Introduction
Thank you for c hoosing Altera Enpirion pow er pr oduc ts !
This evaluation board us er guide applies to two products with identical pinouts: The
EN6337Q I is a 3A devic e, and the EN6347Q I is a 4A devic e. The term EN63x7Q I will
refer to both produc ts throughout this doc um ent. This evaluation board user guide
applies to the EN63x 7−03 engineering devic es . In addition to this doc um ent, you w ill
als o need the lates t devic e datas heet.
• The EN63x7QI features integrated induc tor , power MO SFE TS, controller , a bulk
of the c om pens ation network, and protection circuitry against system faults. This
level of integration delivers a substantial reduction in footprint and parts count
over c om peting s olutions . The evaluation board is optimized for engineering ease
of testing through pr ogram m ing options , c lip leads , tes t points etc .
• The EN63x7QI features a customer programmable output voltage by means of a
resistor divider. The res is tor divider allows the us er to s et the output voltage to
any value within the r ange 0.75V to (VIN-VDROPOUT). The evaluation board, as
shipped is populated with a 4 resistor divider option. The upper r es is tor is fixed
and has a phas e lead c apac itor in parallel. O ne of the 4 lower res is tor s is
s elec ted w ith the jum per option for different output voltages to change VOUT,
retain the upper res is tor and c apac itor values and c hange only the low er res is tor .
• This devic e has no over-voltage protec tion featur e. We s tr ongly rec om m end the
c us tom er to ens ure the feedbac k loop is truly c los ed befor e powering up the
devic e es pec ially if the load c an not w iths tand the input voltage.
• The input and output capacitors are X5R or X 7R multi-layer ceramic chip
capacitors. The Soft-start capacitor is a small 15nF X7R MLCC. Pads are
available to have m ultiple input and output capacitors. This allow s for evaluation
of perform anc e over a w ide range of input/output c apac itor c om binations .
• Clip-on term inals ar e provided for ENA, SS, PO K, and LLM pins.
• Banana jacks are provided for VIN and VOUT power term inals . Several signal and
GND clip-on tes t points are als o provided to m eas ure VIN, VOUT, and GND nodes .
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Enpirion® Power Evaluation Board User Guide
EN6337QI/EN6347QI PowerSoC
• A jum per is provided for controlling the Enable signal. E nable m ay als o be
c ontr olled us ing an external switching s ourc e by rem oving the jum per and
applying the enable signal to the ENA clip-on terminal.
• A jum per is also provided to connect the POK pull-up resistor to the input s upply.
This jum per is es pec ially us eful to m eas ur e the dis able c urrent and elim inates
having to s ubtrac t the c urrent dr awn by the P OK res is tor .
• A jum per is pr ovided for c ontrolling the LLM/SYNC pin. This pin c an be high for
autom atic LLM ( light-load mode) operation. If it is pulled low, the part will be in
PWM m ode only.
• Foot print is also provided for a SMA connector to LLM/SYNC input. A s witc hing
input to this pin allows the devic e clock to be phas e loc ked to an external s ignal.
This exter nal c loc k s ync hroniz ation allow s for m oving any offending beat
frequenc y to be m oved out-of-band. A s w ept fr equenc y applied to this pin res ults
in s pread s pec tr um operation and reduc es the peaks in the nois e s pec tr um of
em itted EMI.
• The board c om es w ith input dec oupling and revers e polar ity protec tion to guard
the devic e agains t c om m on s etup m is haps .
Quick Start Guide
STEP 1: Set the “ENABLE” jum per to the D is able Pos ition, as s how n in Figure 1.
Figure 1: Shows POK, Enable, and LLM Jumpers. POK PWR jumper
as shown connect s pull-up r esist or to VIN. E na bl e jum per shown in
D ISA BLE posit ion. LLM j umper as show n di sa bl es LLM ope ration.
STEP 2: C onnec t Pow er Supply to the input power c onnec tor s , VIN (+) and G ND (-) as
indicated in Figure 1 and s et the s upply to the des ired voltage. The devic e dis able
c urrent m ay be m eas ured in this c onfiguration.
CAUTION: be m indful of the polarity. Even though the evaluation board c om es
with revers e polar ity protec tion diodes , it may not protec t the devic e under all
conditions.
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Enpirion® Power Evaluation Board User Guide
EN6337QI/EN6347QI PowerSoC
STEP 3: C onnec t the load to the output c onnec tor s VO UT ( +) and GND ( -), as
indicated in Figure 1.
STEP 4: Selec t the output voltage s etting jumper. Figure 2 shows what output voltages
are ac hieved by s elec ting eac h jum per pos ition. P opulating m ultiple jum per pos itions
will allow you to s elec t higher output voltages. You c an populate up to all four jum per
pos itions for the highes t VOUT of approxim ately 3.73V w ith the res is tor s populated on the
board.
Fi gure 2: Output V ol tage se l ection j um pers
Jumper shown sel ects 1. 55V output
(Jumper positions from l eft to right are: 2.25V , 1.55V, 1.2V and 1.0V)
STEP 5: Set the PO K PWR and LLM jum pers to des ir ed pos itions (s ee Figur e 1). You
s hould dis able P OK w hen m eas uring low value input currents.
STEP 6: Apply VIN to the boar d and m ove the ENA jum per to the enabled pos ition. The
EN63x7QI is now powered up! Various measurements such as efficiency, line and load
regulation, input / output ripple, load transient, drop-out voltage measurements may be
conducted at this point. The over c ur rent trip level, s hor t c ircuit protec tion, under voltage
loc k out thr es holds , tem peratur e c oeffic ient of the output voltage m ay als o be m eas ured
in this configuration.
CAUTIO N: The maximum allowable VIN for this version of devices is 6.6V.
STEP 6A: Pow er Up/Down Behavior – Rem ove ENA jum per and c onnec t a puls e
generator (output disabled) signal to the clip-on test point below E NA and Ground. Set
the puls e am plitude to swing from 0 to 2.5 volts . Set the puls e period to 10msec. and
duty c yc le to 50%. Hook up os c illos c ope probes to E NA, SS, POK and VO UT w ith c lean
ground returns. Apply power to evaluation board. Enable pulse generator output.
O bs erve the S S c apac itor and VOUT voltage ramps as ENA goes high and again as
ENA goes low. The devic e when powered down ramps down the output voltage in a
controlled manner before fully shutting down. The output voltage level when POK is
as s erted /de-asserted as the dev ice is powered up / dow n m ay be obs erved as w ell as
the c lean output voltage ram p and POK signals.
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Enpirion® Power Evaluation Board User Guide
EN6337QI/EN6347QI PowerSoC
STEP 7: External Clock Synchronization / Spread Spec trum Modes : In order to
ac tivate this m ode, it m ay be nec es s ary to a s older a SMA c onnec tor at J8. Alternately
the input c loc k s ignal leads m ay be direc tly s oldered to the thr ough holes of J8 as
s hown below .
Figure 3: S MA Connector for Exte rna l Cl ock Input
Power dow n the devic e. Move ENA into dis able pos ition. C onnec t the c loc k s ignal as
jus t indic ated. The c loc k s ignal s hould be c lean and have a frequenc y in the r ange of
the nom inal frequenc y ±15%; am plitude 0 to 2.5 volts with a duty cy cle between 20 and
80%. With SYNC s ignal dis abled, pow er up the devic e and m ove ENA jum per to
Enabled position. The device is now powered up and outputting the desired voltage.
The device is switching at its free running frequency. The s w itc hing w avefor m may be
observed between test points SW and G ND. Now enabling the SYNC s ignal w ill
autom atic ally phas e loc k the internal s w itc hing fr equenc y to the exter nally applied
frequency as long as the external clock parameters are within the specified range. To
observe phase-loc k c onnec t os c illos c ope pr obes to the input c loc k as well as to the SW
test point. Phas e loc k range c an be determ ined by s w eeping the external c loc k
frequenc y up / down until the devic e jus t goes out of loc k at the tw o extr em es of its
range.
For s pread s pec trum operation the input c loc k fr equenc y m ay be s w ept betw een tw o
frequenc ies that ar e within the loc k range. The s w eep ( jitter ) repetition rate s hould be
limited to 10 kHz . The radiated EMI s pec trum m ay be now m eas ured in various s tates –
free running, phas e loc ked to a fixed frequenc y and s pread s pec tr um . Before m eas uring
radiated EMI, plac e a 10uF/0805, X7R c apac itor at the input and output edges of the
PCB (footprint already provided on the boar d), and c onnec t the input pow er and the
load to the board at or near thes e c apac itors . The added c apacitor at the input edge is
for high-frequenc y dec oupling of the input cables . The one added at the output edge is
m eant to repres ent a typic al load dec oupling c apac itor.
GND
Ext. Clock
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Enpirion® Power Evaluation Board User Guide
EN6337QI/EN6347QI PowerSoC
Figur e 4: Evaluat ion Board Layout Assembly Layer
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Enpirion® Power Evaluation Board User Guide
EN6337QI/EN6347QI PowerSoC
Figure 5: EN63x7 Evaluat ion Boar d Schemat ic
U1
EN63x7QI
NC(SW)1
1
NC(SW)2
2
NC3
3
NC4
4
VOUT
5
VOUT
6
VOUT
7
VOUT
8
VOUT
9
VOUT
10
VOUT
11
NC(SW)12
12
PGND
13
PGND
14
PGND
15
PGND
16
PGND
17
PGND
18
PVIN
19
BGND 25
VDDB 24
NC23 23
NC22 22
PVIN 21
PVIN 20
NC(SW)38 38
NC(SW)37 37
NC(SW)36 36
NC(SW)35 35
NC(SW)34 34
AVIN 33
AGND 32
VFB 31
SS 30
RLLM 29
POK 28
ENABLE 27
LLM/SYNC 26
C2 C6
C7
C3
R2
TP17
R3
R1
TP5
R5
TP15
R7
J9
1
3
5
2
4
6
87
RLLM
R8
C10
R6
J2
1
2
J3
1
2
TP7 TP6
C11
R4
R9
CW -->
R10
1 3
2
J1
1
2
3
J10
1
2
3
C12
J8
TP18
TP19
C9 TP14
TP4
TP13
TP21
FB1
C13
U2
6.5V D1 +C1 J13
1
2
J4
J6
PVIN
PVIN
TP1
TP2
J11
1
2
J12
1
2
J14
1
2
LLM
J7 J5
SS
ENA
POK
GND
VIN
PGND
VOUT
SYNC
ENA
POK
VIN
J15
1
2
3
TP12 TP3
TP16
TP20
TP8
TP10
TP9
TP25
TP11
TP26
0805
0805
0805
0805
0805
0805
0805
1206/0805
0402
0402
0805
0805
0805
0805
0805
1206/0805
1206/0805
1206/0805
Vout program m ing resistors:
R2 = 200kΩ
R7 = 100kΩ for VOUT = 2.25V
R5 = 187kΩ for VOUT = 1.55V
R1 = 332kΩ for VOUT = 1.20V
R3 = 604kΩ for VOUT = 1.00V
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Enpirion® Power Evaluation Board User Guide
EN6337QI/EN6347QI PowerSoC
Test Recommend atio ns
Recommendations
To guarantee m eas ur em ent ac c urac y, the follow ing prec autions s hould be obs erved:
1. Make all input and output voltage m eas ur em ents at the boar d us ing the tes t
points pr ovided (TP8 to TP11). This w ill elim inate voltage drop ac r os s the line
and load c ables that c an produc e fals e readings .
2. Meas ure input and output c ur rent w ith s eries am m eters or ac c urate s hunt
res is tor s . This is es pec ially im por tant w hen m eas uring effic ienc y.
3. Us e a low-loop-inductance scope probe tip shown below to measure
s witc hing s ignals and input / output ripple to avoid noise coupling into the
probe ground lead. Input ripple, output ripple, and load trans ient deviation ar e
bes t m eas ur ed near the r es pec tive input / output c apac itors . For more
ac c urate r ipple m eas urem ent, pleas e s ee E npirion App Note regarding this
subject.
4. The board inc ludes a pull-up resistor for the POK signal and ready to monitor
the power OK status at c lip lead m ar ked PO K.
5. A 15nF s oft-start capacitor is populated on the board for ~1m s ec s oft -start
time.
6. The over-current protection circuit typically limits the maximum load current to
approximately 1.5X the rated value.
Input and Output Capacitors
Pleas e refer to the BO M section for the value of input caps and output caps used on this
evaluation board, w hic h is the res ult of c om bination for better per form anc e and s m aller
footprints.
NOTE: C apac itors m us t be X5R or X7R dielec tric for m ulations to ens ure adequate
c apac itanc e over oper ating voltage and tem peratur e ranges.
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Enpirion® Power Evaluation Board User Guide
EN6337QI/EN6347QI PowerSoC
Bill of Materials
Designator
Qty
Description
C1
1
CAP, SMT ELECT R OLYT IC , 150UF, 20%, 10V
C2
1
CAP, CER 47UF 10V X5R 1206
C3, C1 3
2
CAP, 10UF 0805 X7R 10% 10V C ERAMIC
C6
1
CAP, CER 22UF 10V X5R 1206
C10 1
EN6337QI Evaluation Board
CAP, 15PF 50V CERM CHI P 0805 SM D
EN6347QI Evaluation Board
CAP, CERM 10PF 5% 50V NP0 0805
C11
1
15000PF 10% 50V SMD 0805 X7R CERAMIC CHI P CAPACI T OR
C7, C9, C12,
J2, J3, J8,
J11, J12, R6,
R10
10
NOT US ED
D1
1
S2A DIODE
FB1 1
MU L TI L AYER SM D FER RI TE BEAD 4000MA 0805 L=T YPIC AL (N OT
GUARANTED)
J1, J10, J15
3
CONN, VERT ICAL, 3 POSI T ION, SMT
J4-J7
4
BAN AN A JAC K
J9
1
CONNECT OR HEADER 8 POS .100" S T R T IN
R1
1
RES 332K OHM 1/8W 1% 0805 SMD
R2
1
RES 200K OHM 1/8W 0.1% 0805 SM D
R3
1
RES 604K OHM 1/8W 1% 0805 SMD
R4
1
RES 100K OHM 1/8W 1% 0805 SMD
R5
1
RES 187K OHM 1/8W 1% 0805 SMD
R7
1
RES 100K OHM 1/8W 0.1% 0805 SM D
R8 1
RES 75.0K OHM 1/8W 1% 0805 SMD
RES 60.4K OHM 1/8W 0.1% 0805 SMD
R9
1
T HICK FILM RESI SIT OR 0 OHM 1/8W 5% 0805 SMD
TP3, TP5,
TP8-TP12,
TP15-TP17
TP20, TP21,
TP25, TP 26
14
T EST POINT SURFACE MOUNT
U1 1
EN6337QI Evaluation Board
EN6337QI 3A GOOD T EST ED
PRODUCT USING 6337-06 DIE - FIX
IN T HE LLM FILT ER LOGIC (GOLD
WIRE)
EN6347QI Evaluation Board
EN6347QI 4A GOOD T EST ED
PRODUCT USING 6347-06 DIE -
SOFT-SHORT FIX (COPPER WIRE)
U2
1
TRAN SIEN T VOL TAGE SUPPR ESSO R , 6 .5 V, BID IR EC TI O N AL , SMT
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Enpirion® Power Evaluation Board User Guide
EN6337QI/EN6347QI PowerSoC
Contact Information
Altera Corporation
101 Innovation D rive
San Jos e, CA 95134
Phone: 408-544-7000
www.altera.com
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