10 MHz, 20 V/μs, G = 1, 10, 100, 1000 iCMOS
Programmable Gain Instrumentation Amplifier
AD8253
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
FEATURES
Small package: 10-lead MSOP
Programmable gains: 1, 10, 100, 1000
Digital or pin-programmable gain setting
Wide supply: ±5 V to ±15 V
Excellent dc performance
High CMRR: 100 dB (minimum), G = 100
Low gain drift: 10 ppm/°C (maximum)
Low offset drift: 1.2 V/°C (maximum), G = 1000
Excellent ac performance
Fast settling time: 780 ns to 0.001% (maximum)
High slew rate: 20 V/µs (minimum)
Low distortion: −110 dB THD at 1 kHz,10 V swing
High CMRR over frequency: 100 dB to 20 kHz (minimum)
Low noise: 10 nV/√Hz, G = 1000 (maximum)
Low power: 4 mA
APPLICATIONS
Data acquisition
Biomedical analysis
Test and measurement
GENERAL DESCRIPTION
The AD8253 is an instrumentation amplifier with digitally
programmable gains that has gigaohm (GΩ) input impedance,
low output noise, and low distortion, making it suitable for
interfacing with sensors and driving high sample rate analog-to-
digital converters (ADCs).
It has a high bandwidth of 10 MHz, low THD of −110 dB, and
fast settling time of 780 ns (maximum) to 0.001%. Offset drift and
gain drift are guaranteed to 1.2 V/°C and 10 ppm/°C, respectively,
for G = 1000. In addition to its wide input common voltage range,
it boasts a high common-mode rejection of 100 dB at G = 1000
from dc to 20 kHz. The combination of precision dc performance
coupled with high speed capabilities makes the AD8253 an
excellent candidate for data acquisition. Furthermore, this
monolithic solution simplifies design and manufacturing and
boosts performance of instrumentation by maintaining a tight
match of internal resistors and amplifiers.
The AD8253 user interface consists of a parallel port that allows
users to set the gain in one of two different ways (see Figure 1
for the functional block diagram). A 2-bit word sent via a bus
can be latched using the WR input. An alternative is to use
transparent gain mode, where the state of logic levels at the gain
port determines the gain.
FUNCTIONAL BLOCK DIAGRAM
A1 A0DGND WR
AD8253
+V
S
–V
S
REF
OUT
+IN
LOGIC
–IN
1
10
8 3
7
4562
9
06983-001
Figure 1.
80
70
60
50
40
30
20
10
0
–10
–20
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
GAIN (dB)
006983-023
G = 1000
G = 100
G = 10
G = 1
Figure 2. Gain vs. Frequency
Table 1. Instrumentation Amplifiers by Category
General
Purpose
Zero
Drift
Mil
Grade
Low
Power
High Speed
PGA
AD82201 AD82311 AD620 AD6271 AD8250
AD8221 AD85531 AD621 AD6231 AD8251
AD8222 AD85551 AD524 AD82231 AD8253
AD82241 AD85561 AD526
AD8228 AD85571 AD624
1 Rail-to-rail output.
The AD8253 is available in a 10-lead MSOP package and is
specified over the −40°C to +85°C temperature range, making it
an excellent solution for applications where size and packing
density are important considerations.
AD8253
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Maximum Power Dissipation ..................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 16
Gain Selection ............................................................................. 16
Power Supply Regulation and Bypassing ................................ 18
Input Bias Current Return Path ............................................... 18
Input Protection ......................................................................... 18
Reference Terminal .................................................................... 19
Common-Mode Input Voltage Range ..................................... 19
Layout .......................................................................................... 19
RF Interference ........................................................................... 19
Driving an Analog-to-Digital Converter ................................ 20
Applications Information .............................................................. 21
Differential Output .................................................................... 21
Setting Gains with a Microcontroller ...................................... 21
Data Acquisition ......................................................................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
8/08—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 23
7/08—Revision 0: Initial Version
AD8253
Rev. A | Page 3 of 24
SPECIFICATIONS
+VS = +15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V
G = 1 80 100 dB
G = 10 96 120 dB
G = 100 100 120 dB
G = 1000 100 120 dB
CMRR to 20 kHz1+IN = −IN = −10 V to +10 V
G = 1 80 dB
G = 10 96 dB
G = 100 100 dB
G = 1000 100 dB
NOISE
Voltage Noise, 1 kHz, RTI
G = 1 45 nV/√Hz
G = 10 12 nV/√Hz
G = 100 11 nV/√Hz
G = 1000 10 nV/√Hz
0.1 Hz to 10 Hz, RTI
G = 1 2.5 μV p-p
G = 10 1 μV p-p
G = 100 0.5 μV p-p
G = 1000 0.5 μV p-p
Current Noise, 1 kHz 5 pA/√Hz
Current Noise, 0.1 Hz to 10 Hz 60 pA p-p
VOLTAGE OFFSET
Offset RTI VOS G = 1, 10, 100, 1000 ±150 + 900/G μV
Over Temperature T = −40°C to +85°C ±210 + 900/G μV
Average TC T = −40°C to +85°C ±1.2 + 5/G μV/°C
Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±5 + 25/G μV/V
INPUT CURRENT
Input Bias Current 5 50 nA
Over Temperature2T = −40°C to +85°C 40 60 nA
Average TC T = −40°C to +85°C 400 pA/°C
Input Offset Current 5 40 nA
Over Temperature T = −40°C to +85°C 40 nA
Average TC T = −40°C to +85°C 160 pA/°C
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G = 1 10 MHz
G = 10 4 MHz
G = 100 550 kHz
G = 1000 60 kHz
Settling Time 0.01% ΔOUT = 10 V step
G = 1 700 ns
G = 10 680 ns
G = 100 1.5 μs
G = 1000 14 μs
AD8253
Rev. A | Page 4 of 24
Parameter Conditions Min Typ Max Unit
Settling Time 0.001% ΔOUT = 10 V step
G = 1 780 ns
G = 10 880 ns
G =100 1.8 μs
G = 1000 1.8 μs
Slew Rate
G = 1 20 V/μs
G = 10 20 V/μs
G = 100 12 V/μs
G = 1000 2 V/μs
Total Harmonic Distortion + Noise f = 1 kHz, RL = 10 kΩ, ±10 V,
G = 1, 10 Hz to 22 kHz band-
pass filter
−110 dB
GAIN
Gain Range G = 1, 10, 100, 1000 1 1000 V/V
Gain Error OUT = ±10 V
G = 1 0.03 %
G = 10, 100, 1000 0.04 %
Gain Nonlinearity OUT = −10 V to +10 V
G = 1 RL = 10 kΩ, 2 kΩ, 600 Ω 5 ppm
G = 10 RL = 10 kΩ, 2 kΩ, 600 Ω 3 ppm
G = 100 RL = 10 kΩ, 2 kΩ, 600 Ω 18 ppm
G = 1000 RL = 10 kΩ, 2 kΩ, 600 Ω 110 ppm
Gain vs. Temperature All gains 3 10 ppm/°C
INPUT
Input Impedance
Differential 4||1.25
GΩ||pF
Common Mode 1||5 GΩ||pF
Input Operating Voltage Range VS = ±5 V to ±15 V −VS + 1 +VS − 1.5 V
Over Temperature3T = −40°C to +85°C −VS + 1.2 +VS − 1.7 V
OUTPUT
Output Swing −13.7 +13.6 V
Over Temperature4T = −40°C to +85°C −13.7 +13.6 V
Short-Circuit Current 37 mA
REFERENCE INPUT
RIN 20 kΩ
IIN +IN, −IN, REF = 0 1 μA
Voltage Range −VS +VS V
Gain to Output 1 ± 0.0001 V/V
DIGITAL LOGIC
Digital Ground Voltage, DGND Referred to GND −VS + 4.25 0 +VS − 2.7 V
Digital Input Voltage Low Referred to GND DGND 1.2 V
Digital Input Voltage High Referred to GND 1.5 +VS V
Digital Input Current 1 μA
Gain Switching Time5 325 ns
tSU See Figure 3 timing diagram 15 ns
tHD 30 ns
tWR -LOW 20 ns
tWR -HIGH 15 ns
AD8253
Rev. A | Page 5 of 24
Parameter Conditions Min Typ Max Unit
POWER SUPPLY
Operating Range ±5 ±15 V
Quiescent Current, +IS 4.6 5.3 mA
Quiescent Current, −IS 4.5 5.3 mA
Over Temperature T = −40°C to +85°C 6 mA
TEMPERATURE RANGE
Specified Performance −40 +85 °C
1 See Figure 20 for CMRR vs. frequency for more information on typical performance over frequency.
2 Input bias current over temperature: minimum at hot and maximum at cold.
3 See Figure 30 for input voltage limit vs. supply voltage and temperature.
4 See Figure 32, Figure 33, and Figure 34 for output voltage swing vs. supply voltage and temperature for various loads.
5 Add time for the output to slew and settle to calculate the total time for a gain change.
TIMING DIAGRAM
A0, A1
WR
t
SU
t
HD
t
WR-HIGH
t
WR-LOW
0
6983-003
Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)
AD8253
Rev. A | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage ±17 V
Power Dissipation See Figure 4
Output Short-Circuit Current Indefinite1
Common-Mode Input Voltage ±VS
Differential Input Voltage ±VS
Digital Logic Inputs ±VS
Storage Temperature Range –65°C to +125°C
Operating Temperature Range2 –40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 140°C
θJA (4-Layer JEDEC Standard Board) 112°C/W
Package Glass Transition Temperature 140°C
1 Assumes the load is referenced to midsupply.
2 Temperature for specified performance is −40°C to +85°C. For performance
to +125°C, see the Typical Performance Characteristics section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8253 package is
limited by the associated rise in junction temperature (TJ) on
the die. The plastic encapsulating the die locally reaches the
junction temperature. At approximately 140°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8253. Exceeding
a junction temperature of 140°C for an extended period can
result in changes in silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature is calculated as
(
)
JA
D
A
JθPTT ×+=
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some of which is dissipated in the
load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power − Load Power)
()
L
2
OUT
L
OUTS
SS
DR
V
–
R
V
2
V
IVP ⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛×+×=
In single-supply operation with RL referenced to −VS, the worst
case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces through holes, ground, and power planes
reduces the θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a 4-layer JEDEC
standard board.
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
–40 –20 120100806040200
MAXIMUM POWER DISSIPATION (W)
AMBIENT TEMPERATURE (°C)
06983-004
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
AD8253
Rev. A | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN
DGND
–V
S
A0
A1
+IN
REF
+V
S
OUT
WR
AD8253
TOP VIEW
(Not to Scale)
1
2
3
4
5
10
9
8
7
6
06983-005
Figure 5. 10-Lead MSOP (RM-10) Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Inverting Input Terminal. True differential input.
2 DGND Digital Ground.
3 −VS Negative Supply Terminal.
4 A0 Gain Setting Pin (LSB).
5 A1 Gain Setting Pin (MSB).
6 WR Write Enable.
7 OUT Output Terminal.
8 +VS Positive Supply Terminal.
9 REF Reference Voltage Terminal.
10 +IN Noninverting Input Terminal. True differential input.
AD8253
Rev. A | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
TA @ 25°C, +VS = +15 V, −VS = −15 V, RL = 10 k, unless otherwise noted.
CMRR (µV/V)
210
0
06983-006
NUMBER OF UNITS
180
150
120
90
60
30
–60 –40 –20 0 20
INPUT OFFSET CURRENT (nA)
240
120
180
60
0
150
210
90
30
6040200
06983-009
NUMBER OF UNITS
–60 –20–40
Figure 6. Typical Distribution of CMRR, G = 1 Figure 9. Typical Distribution of Input Offset Current
INPUT OFFSET VOLTAGE, V
OSI
, RTI (µV)
180
120
60
30
150
90
0
2001000
06983-007
NUMBER OF UNITS
–200 –100
06983-010
90
0
1 100k
FREQUENCY (Hz)
NOISE (nV/Hz)
10 100 1k 10k
80
70
60
50
40
30
20
10
G = 10
G = 100
G = 1000
G = 1
Figure 10. Voltage Spectral Density Noise vs. Frequency
Figure 7. Typical Distribution of Offset Voltage, VOSI
06983-011
1s/DIV2µV/DIV
INPUT BIAS CURRENT (nA)
300
200
250
150
100
50
0
9060300
06983-008
NUMBER OF UNITS
–90 –30–60
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1
Figure 8. Typical Distribution of Input Bias Current
AD8253
Rev. A | Page 9 of 24
06983-012
1s/DIV
500nV/DIV
Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1000
06983-013
18
0
11
FREQUENCY (Hz)
NOISE (pA/Hz)
00k
10 100 1k 10k
16
14
12
10
8
6
4
2
Figure 13. Current Noise Spectral Density vs. Frequency
06983-014
1s/DIV140pA/DIV
Figure 14. 0.1 Hz to 10 Hz Current Noise
20
18
16
14
12
10
8
6
4
2
0
0.01 0.1 1 10
WARM-UP TIME (Minutes)
CHANGE IN INPUT OFFSET VOLTAGE (µV)
06983-015
Figure 15. Change in Input Offset Voltage vs. Warm-Up Time, G = 1000
140
120
100
80
40
60
0
10 1M
06983-016
FREQUENCY (Hz)
PSRR (dB)
100 1k 10k 100k
20
G = 1
G = 10
G = 100
G = 1000
Figure 16. Positive PSRR vs. Frequency, RTI
140
120
100
80
40
60
0
10 1M
06983-017
FREQUENCY (Hz)
PSRR (dB)
100 1k 10k 100k
20
G = 1
G = 1000
G = 10
G = 100
Figure 17. Negative PSRR vs. Frequency, RTI
AD8253
Rev. A | Page 10 of 24
20
10
0
–10
–20
–30
–40
–50
–60
12.0
I
B
+
10.5
9.0
7.5
6.0
4.5
3.0
1.5
0
–15 –10 –5 0 5 10 15
COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRENT (nA)
INPUT OFFSET CURRENT (nA)
06983-018
I
B
–
I
OS
Figure 18. Input Bias Current and Offset Current vs. Common-Mode Voltage
30
25
20
15
10
5
0
–10
–5
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
INPUT BIAS CURRENT AND
OFFSET CURRENT (nA)
06983-019
I
B
+
I
B
–
I
OS
Figure 19. Input Bias Current and Offset Current vs. Temperature
0
120
100
80
60
40
20
10
06983-020
FREQUENCY (Hz)
CMRR (dB)
100 1k 10k 100k 1M
G = 1
G = 1000
G = 10
G = 100
Figure 20. CMRR vs. Frequency
0
120
100
80
60
40
20
10
06983-021
FREQUENCY (Hz)
CMRR (dB)
100 1k 10k 100k 1M
G = 1
G = 1000
G = 10
G = 100
Figure 21. CMRR vs. Frequency, 1 kΩ Source Imbalance
–15
–50 130
06983-022
TEMPERATURE (°C)
CMRR (µV/V)
10
15
5
0
–5
–10
–30–101030507090110
Figure 22. CMRR vs. Temperature, G = 1
80
70
60
50
40
30
20
10
0
–10
–20
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
GAIN (dB)
006983-023
G = 1000
G = 100
G = 10
G = 1
Figure 23. Gain vs. Frequency
AD8253
Rev. A | Page 11 of 24
40
30
20
10
–10
–30
0
–20
–40
–10–8–6–4–20246810
06983-024
NONLINEARITY (10ppm/DIV)
OUTPUT VOLTAGE (V)
Figure 24. Gain Nonlinearity, G = 1, RL = 10 kΩ, 2 kΩ, 600 Ω
40
30
20
10
–10
–30
0
–20
–40
–10–8–6–4–20246810
06983-025
NONLINEARITY (10ppm/DIV)
OUTPUT VOLTAGE (V)
Figure 25. Gain Nonlinearity, G = 10, RL = 10 kΩ, 2 kΩ, 600 Ω
80
60
40
20
–20
–60
0
–40
–80
–10–8–6–4–20246810
06983-026
NONLINEARITY (10ppm/DIV)
OUTPUT VOLTAGE (V)
Figure 26. Gain Nonlinearity, G = 100, RL = 10 kΩ, 2 kΩ, 600 Ω
400
300
200
100
–100
–300
0
–200
–400
–10–8–6–4–20246810
06983-027
NONLINEARITY (10 ppm/DIV)
OUTPUT VOLTAGE (V)
Figure 27. Gain Nonlinearity, G = 1000, RL = 10 kΩ, 2 kΩ, 600 Ω
16
–16
–16 16
06983-028
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
12
8
4
0
–4
–8
–12
–12 –8 –4 0 4 8 12
VS= ±5V
0V, –4.2V
0V, –14.2V
0V, +13.9V
–14.1V, +7.3V
–14.1V, –7.3V +13.8V, –7.3V
+13.8V, +7.3V
–4V, –1.9V
–4V, +1.9V
+3.8V, –1.9V
+3.8V, +1.9V
0V, +3.8V
VS, ±15V
Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 1
16
–16
–16 16
06983-029
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
12
8
4
0
–4
–8
–12
–12 –8 –4 0 4 8 12
VS= ±5V
0V, –4.2V
0V, –14.1V
0V, +13.7V
–14.4V, +6V
–14.4V, –6V
+14.1V, +6V
+14.1V, –6V
–4.3V, –2V
–4.3V, +2V
+4.3V, –2V
+4.3V, +2V
0V, +3.8V
VS ±15V
Figure 29. Input Common-Mode Voltage Range vs. Output Voltage, G = 1000
AD8253
Rev. A | Page 12 of 24
+
V
S
–V
S
41
06983-030
SUPPLY VOLTAGE (±V
S
)
INPUT VOLTAGE (V)
REFERRED TO SUPPLY VOLTAGES
6
–1
–2
+2
+1
6 8 10 12 14
+125°C +85°C
+25°C
–40°C
+125°C +85°C
+25°C
–40°C
Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF = 0 V, RL = 10 kΩ
25
20
15
10
5
0
–5
–10
–15
–20
–25
–10
–1
–100m
–10m
–1m
–100µ
–10µ/
10µ
DIFFERENTIAL INPUT VOLTAGE (V)
CURRENT (mA)
06983-031
100µ
1m
10m
100m
1
10
FAULT
CONDITION
(OVER-DRIVEN
INPUT)
G=1000
FAULT
CONDITION
(OVER-DRIVEN
INPUT)
G=1000
–IN–IN
+IN +IN
+Vs
–Vs
Figure 31. Fault Current Draw vs. Input Voltage, G = 1000, RL = 10 kΩ
+
V
S
–V
S
41
06983-032
SUPPLY VOLTAGE (±V
S
)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
6
6 8 10 12 14
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
+1.0
+1.2
+0.8
+0.6
+0.4
+0.2
+125°C
+125°C
+25°C
–40°C
–40°C +85°C
+85°C
+25°C
Figure 32. Output Voltage Swing vs. Supply Voltage, G = 1000, RL = 2 kΩ
+
V
S
–V
S
41
06983-033
SUPPLY VOLTAGE (±V
S
)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
6
6 8 10 12 14
–0.2
–0.4
–0.6
–0.8
–1.0
+1.0
+0.8
+0.6
+0.4
+0.2
+125°C
+125°C
+25°C
–40°C
–40°C
+85°C
+85°C
+25°C
Figure 33. Output Voltage Swing vs. Supply Voltage, G =1000, RL = 10 kΩ
15
–15
100 10k
06983-034
LOAD RESISTANCE ()
1k
10
5
0
–5
–10
OUTPUT VOLTAGE SWING (V)
+125°C
+25°C
–40°C
+85°C
+25°C
+85°C
+125°C
–40°C
Figure 34. Output Voltage Swing vs. Load Resistance
+
V
S
–V
S
41
06983-035
OUTPUT CURRENT (mA)
6
6 8 10 12 14
–0.4
–0.8
–1.2
–1.6
–2.0
+2.0
+1.6
+1.2
+0.8
+0.4
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–40°C
+25°C
+85°C
+125°C
Figure 35. Output Voltage Swing vs. Output Current
AD8253
Rev. A | Page 13 of 24
2µs/DIV20mV/DIV
NO
LOAD 100pF
47pF
06983-036
Figure 36. Small-Signal Pulse Response for Various Capacitive Loads, G = 1
06983-037
5V/DIV
2µs/DIV
0.002%/DIV
664ns TO 0.01%
744ns TO 0.001%
TIME (µs)
Figure 37. Large-Signal Pulse Response and Settling Time, G = 1, RL = 10 kΩ
06983-038
5V/DIV
2µs/DIV
0.002%/DIV
656ns TO 0.01%
840ns TO 0.001%
TIME (µs)
Figure 38. Large-Signal Pulse Response and Settling Time,
G = 10, RL = 10 kΩ
06983-039
5V/DIV
2µs/DIV
0.002%/DIV
1392ns TO 0.01%
1712ns TO 0.001%
TIME (µs)
Figure 39. Large-Signal Pulse Response and Settling Time,
G = 100, RL = 10 kΩ
06983-040
5V/DIV
10µs/DIV
0.002%/DIV
12.88µs TO 0.01%
16.64µs TO 0.001%
TIME (µs)
Figure 40. Large-Signal Pulse Response and Settling Time,
G = 1000, RL = 10 kΩ
06983-041
20mV/DIV 2µs/DIV
Figure 41. Small-Signal Response,
G = 1, RL = 2 kΩ, CL = 100
AD8253
Rev. A | Page 14 of 24
06983-042
20mV/DIV 2µs/DIV
Figure 42. Small-Signal Response,
G = 10, RL = 2 kΩ, CL = 100 pF
06983-043
20mV/DIV 20µs/DIV
Figure 43. Small-Signal Response,
G = 100, RL = 2 kΩ, CL = 100 pF
06983-044
20mV/DIV 20µs/DIV
Figure 44. Small-Signal Response, G = 1000, RL = 2 kΩ, CL = 100 pF
06983-045
1200
1400
0
22
STEP SIZE (V)
TIME (ns)
1000
800
600
400
200
0
4 6 8 10 12 14 16 18
SETTLED TO 0.01%
SETTLED TO 0.001%
Figure 45. Settling Time vs. Step Size, G = 1, RL = 10 kΩ
06983-046
1200
1400
0
22
STEP SIZE (V)
TIME (ns)
1000
800
600
400
200
0
4 6 8 1012141618
SETTLED TO 0.01%
SETTLED TO 0.001%
Figure 46. Settling Time vs. Step Size, G = 10, RL = 10 kΩ
06983-047
1200
0
22
STEP SIZE (V)
TIME (ns)
1000
800
600
2000
1800
1600
1400
400
200
0
4 6 8 10 12 14 16 18
SETTLED TO 0.01%
SETTLED TO 0.001%
Figure 47. Settling Time vs. Step Size, G = 100, RL = 10 kΩ
AD8253
Rev. A | Page 15 of 24
06983-048
12
0
22
STEP SIZE (V)
TIME (µs)
10
8
6
20
18
16
14
4
2
0
4 6 8 1012141618
SETTLED TO 0.01%
SETTLED TO 0.001%
Figure 48. Settling Time vs. Step Size, G = 1000, RL = 10 kΩ
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–120
–110
–100
10 1M
06983-049
FREQUENCY (Hz)
THD + N (dB)
100 1k 10k 100k
G = 1
G = 1000
G = 10
G = 100
Figure 49. Total Harmonic Distortion vs. Frequency,
10 Hz to 22 kHz Band-Pass Filter, 2 kΩ Load
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–120
–110
–100
10 1M
06983-050
FREQUENCY (Hz)
THD + N (dB)
100 1k 10k 100k
G = 1
G = 1000
G = 10
G = 100
Figure 50. Total Harmonic Distortion vs. Frequency,
10 Hz to 500 kHz Band-Pass Filter, 2 kΩ Load
AD8253
Rev. A | Page 16 of 24
THEORY OF OPERATION
10k
10k10k
10k
REF
OUT
A3
–
IN
+IN
WR
1.2k
1.2k
+
V
S+
V
S
–VS–VS
+VS
–VS
+VS
–VS
A1A0
2.2k
DGND
A1
A2
DIGITAL
GAIN
CONTROL
2.2k
+VS
–VS
+VS
–VS
+VS
–VS
+VS
–VS
0
6983-061
Figure 51. Simplified Schematic
Transparent Gain Mode
The AD8253 is a monolithic instrumentation amplifier based
on the classic 3-op-amp topology, as shown in Figure 51. It is
fabricated on the Analog Devices, Inc., proprietary iCMOS®
process that provides precision linear performance and a robust
digital interface. A parallel interface allows users to digitally
program gains of 1, 10, 100, and 1000. Gain control is achieved
by switching resistors in an internal precision resistor array (as
shown in Figure 51).
The easiest way to set the gain is to program it directly via a
logic high or logic low voltage applied to A0 and A1. Figure 52
shows an example of this gain setting method, referred to through-
out the data sheet as transparent gain mode. Tie WR to the
negative supply to engage transparent gain mode. In this mode,
any change in voltage applied to A0 and A1 from logic low to
logic high, or vice versa, immediately results in a gain change.
is the truth table for transparent gain mode, and
shows the AD8253 configured in transparent gain mode.
Table 5 Figure 52
All internal amplifiers employ distortion cancellation circuitry
and achieve high linearity and ultralow THD. Laser-trimmed
resistors allow for a maximum gain error of less than 0.03% for
G = 1 and a minimum CMRR of 100 dB for G = 1000. A pinout
optimized for high CMRR over frequency enables the AD8253
to offer a guaranteed minimum CMRR over frequency of 80 dB
at 20 kHz (G = 1). The balanced input reduces the parasitics
that in the past had adversely affected CMRR performance.
+15
V
–15V
–15V
A0
A1
WR
+IN
+5V
+5V
–IN
10F0.1µF
10F0.1µF
G = 1000
DGND DGND
REF
AD8253
NOTE:
1. IN TRANSPARENT GAIN MODE, WR IS TIED TO
V
S
.
THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE
THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE
SET TO LOGIC HIGH, RESULTING IN A GAIN OF 1000.
0
6983-051
GAIN SELECTION
This section describes how to configure the AD8253 for basic
operation. Logic low and logic high voltage limits are listed in
the Specifications section. Typically, logic low is 0 V and logic
high is 5 V; both voltages are measured with respect to DGND.
Refer to the specifications table (Tabl e 2) for the permissible
voltage range of DGND. The gain of the AD8253 can be set
using two methods: transparent gain mode and latched gain
mode. Regardless of the mode, pull-up or pull-down resistors
should be used to provide a well-defined voltage at the A0 and
A1 pins. Figure 52. Transparent Gain Mode, A0 and A1 = High, G = 1000
AD8253
Rev. A | Page 17 of 24
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR A1 A0 Gain
−VS Low Low 1
−VS Low High 10
−VS High Low 100
−VS High High 1000
Latched Gain Mode
Some applications have multiple programmable devices such
as multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8253 can be set using WR as a latch,
allowing other devices to share A0 and A1. shows a
schematic using this method, known as latched gain mode. The
AD8253 is in this mode when
Figure 53
WR is held at logic high or logic
low, typically 5 V and 0 V, respectively. The voltages on A0 and A1
are read on the downward edge of the WR signal as it transitions
from logic high to logic low. This latches in the logic levels on
A0 and A1, resulting in a gain change. See the truth table listing
in for more on these gain changes. Table 6
+15
V
–15V
A0
A1
WR
+IN
–IN
10F0.1µF
10F0.1µF
DGND DGND
REF
AD8253
A0
A1
WR
+5V
+5V
+5V
0V
0V
0V
G = PREVIOUS
STATE
G = 1000
+
–
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 1000.
06983-052
Figure 53. Latched Gain Mode, G = 1000
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR A1 A0 Gain
High to Low Low Low Change to 1
High to Low Low High Change to 10
High to Low High Low Change to 100
High to Low High High Change to 1000
Low to Low X1 X
1 No change
Low to High X1 X
1 No change
High to High X1 X
1 No change
1 X = don’t care.
On power-up, the AD8253 defaults to a gain of 1 when in
latched gain mode. In contrast, if the AD8253 is configured in
transparent gain mode, it starts at the gain indicated by the
voltage levels on A0 and A1 on power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 must be held for
a minimum setup time, tSU, before the downward edge of WR
latches in the gain. Similarly, they must be held for a minimum
hold time, tHD, after the downward edge of WR to ensure that
the gain is latched in correctly. After tHD, A0 and A1 may change
logic levels, but the gain does not change until the next downward
edge of WR. The minimum duration that WR can be held high
is t WR-HIGH, and t WR-LOW is the minimum duration that WR can
be held low. Digital timing specifications are listed in
The time required for a gain change is dominated by the settling
time of the amplifier. A timing diagram is shown in .
Table 2.
Figure 54
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8253. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog
portions of the board.
A0, A1
WR
t
SU
t
HD
t
WR-HIGH
t
WR-LOW
0
6983-053
Figure 54. Timing Diagram for Latched Gain Mode
AD8253
Rev. A | Page 18 of 24
POWER SUPPLY REGULATION AND BYPASSING
The AD8253 has high PSRR. However, for optimal performance,
a stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect per-
formance. As in all linear circuits, bypass capacitors must be
used to decouple the amplifier.
Place a 0.1 µF capacitor close to each supply pin. A 10 µF tantalum
capacitor can be used farther away from the part (see Figure 55)
and, in most cases, it can be shared by other precision integrated
circuits.
AD8253
+
V
S
+IN
–IN
LOAD
REF
0.1µF 10µF
0.1µF 10µF
–V
S
DGND
V
OUT
DGND
A0
A1
WR
06983-054
Figure 55. Supply Decoupling, REF, and Output Referred to Ground
INPUT BIAS CURRENT RETURN PATH
The AD8253 input bias current must have a return path to its
local analog ground. When the source, such as a thermocouple,
cannot provide a return current path, one should be created
(see Figure 56).
THERMOCOUPLE
+V
S
REF
–V
S
AD8253
CAPACITIVELY COUPLED
+V
S
REF
C
C
–V
S
AD8253
TRANSFORMER
+V
S
REF
–V
S
AD8253
INCORRECT
CAPACITIVELY COUPLED
+V
S
REF
C
R
R
C
–V
S
AD8253
1
f
HIGH-PASS
= 2RC
THERMOCOUPLE
+V
S
REF
–V
S
10M
AD8253
TRANSFORMER
+V
S
REF
–V
S
AD8253
CORRECT
06983-055
Figure 56. Creating an IBIAS Path
INPUT PROTECTION
All terminals of the AD8253 are protected against ESD. An external
resistor should be used in series with each of the inputs to limit
current for voltages greater than 0.5 V beyond either supply rail.
In such a case, the AD8253 safely handles a continuous 6 mA
current at room temperature. For applications where the AD8253
encounters extreme overload voltages, external series resistors
and low leakage diode clamps such as BAV199Ls, FJH1100s, or
SP720s should be used.
AD8253
Rev. A | Page 19 of 24
REFERENCE TERMINAL
The reference terminal, REF, is at one end of a 10 k resistor
(see Figure 51). The instrumentation amplifier output is
referenced to the voltage on the REF terminal; this is useful
when the output signal needs to be offset to voltages other than
its local analog ground. For example, a voltage source can be
tied to the REF pin to level shift the output so that the AD8253
can interface with a single-supply ADC. The allowable reference
voltage range is a function of the gain, common-mode input,
and supply voltages. The REF pin should not exceed either +VS
or −VS by more than 0.5 V.
For best performance, especially in cases where the output is
not measured with respect to the REF terminal, source imped-
ance to the REF terminal should be kept low because parasitic
resistance can adversely affect CMRR and gain accuracy.
INCORRECT
AD8253
VREF
CORRECT
AD8253
OP1177
+
–
VREF
0
6983-056
Figure 57. Driving the Reference Pin
COMMON-MODE INPUT VOLTAGE RANGE
The 3-op-amp architecture of the AD8253 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8253 experience a combination of both the gained
signal and the common-mode signal. This combined signal can
be limited by the voltage supplies even when the individual
input and output signals are not. Figure 28 and Figure 29 show
the allowable common-mode input voltage ranges for various
output voltages, supply voltages, and gains.
LAYOUT
Grounding
In mixed-signal circuits, low level analog signals need to be
isolated from the noisy digital environment. Designing with the
AD8253 is no exception. Its supply voltages are referenced to an
analog ground. Its digital circuit is referenced to a digital ground.
Although it is convenient to tie both grounds to a single ground
plane, the current traveling through the ground wires and PC
board can cause an error. Therefore, use separate analog and
digital ground planes. Only at one point, star ground, should
analog and digital ground meet.
The output voltage of the AD8253 develops with respect to the
potential on the reference terminal. Take care to tie REF to the
appropriate local analog ground or to connect it to a voltage that
is referenced to the local analog ground.
Coupling Noise
To prevent coupling noise onto the AD8253, follow these
guidelines:
• Do not run digital lines under the device.
• Run the analog ground plane under the AD8253.
• Shield fast-switching signals with digital ground to avoid
radiating noise to other sections of the board, and never
run them near analog signal paths.
• Avoid crossover of digital and analog signals.
• Connect digital and analog ground at one point only
(typically under the ADC).
• Power supply lines should use large traces to ensure a low
impedance path. Decoupling is necessary; follow the
guidelines listed in the Power Supply Regulation and
Bypassing section.
Common-Mode Rejection
The AD8253 has high CMRR over frequency, giving it greater
immunity to disturbances, such as line noise and its associated
harmonics, in contrast to typical in amps whose CMRR falls off
around 200 Hz. They often need common-mode filters at the
inputs to compensate for this shortcoming. The AD8253 is able
to reject CMRR over a greater frequency range, reducing the
need for input common-mode filtering.
Careful board layout maximizes system performance. To maintain
high CMRR over frequency, lay out the input traces symmetrically.
Ensure that the traces maintain resistive and capacitive balance;
this holds for additional PCB metal layers under the input pins
and traces. Source resistance and capacitance should be placed
as close to the inputs as possible. Should a trace cross the inputs
(from another layer), it should be routed perpendicular to the
input traces.
RF INTERFERENCE
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass RC network placed at the input
of the instrumentation amplifier, as shown in Figure 58. The
filter limits the input signal bandwidth according to the following
relationship:
)CC(R
1
FilterFreq
C
D
DIFF +
=2π2
C
CM RC
1
FilterFreq π2
=
where CD ≥ 10 CC.
AD8253
Rev. A | Page 20 of 24
R
R
AD8253
+15
V
+IN
–IN
0.1µF 10µF
10µF
0.1µF
REF
V
OUT
–15V
C
D
C
C
C
C
0
6983-057
In this example, a 1 nF capacitor and a 49.9 Ω resistor create an
antialiasing filter for the AD7612. The 1 nF capacitor also serves
to store and deliver necessary charge to the switched capacitor
input of the ADC. The 49.9 series resistor reduces the burden
of the 1 nF load from the amplifier and isolates it from the kickback
current injected from the switched capacitor input of the AD7612.
Selecting too small a resistor improves the correlation between
the voltage at the output of the AD8253 and the voltage at the
input of the AD7612 but may destabilize the AD8253. A trade-
off must be made between selecting a resistor small enough to
maintain accuracy and large enough to maintain stability.
0.1F
0.1F
1nF
49.9
AD7612
ADR435
+12V –12V
+5V
+15
V
–15V
A0
A1
WR
+IN
–
IN
10F0.1µF
10F0.1µF
REF
AD8253
DGNDDGND
06983-058
Figure 58. RFI Suppression
Values of R and C C should be chosen to minimize RFI.
Mismatch between the R × CC at the positive input and the
R × CC at negative input degrades the CMRR of the AD8253.
By using a value of CD that is 10 times larger than the value of
CC, the effect of the mismatch is reduced and performance is
improved.
DRIVING AN ANALOG-TO-DIGITAL CONVERTER
An instrumentation amplifier is often used in front of an analog-
to-digital converter to provide CMRR. Usually, instrumentation
amplifiers require a buffer to drive an ADC. However, the low
output noise, low distortion, and low settle time of the AD8253
make it an excellent ADC driver.
Figure 59. Driving an ADC
AD8253
Rev. A | Page 21 of 24
APPLICATIONS INFORMATION
DIFFERENTIAL OUTPUT
In certain applications, it is necessary to create a differential
signal. High resolution analog-to-digital converters often require a
differential input. In other cases, transmission over a long distance
can require differential signals for better immunity to interference.
Figure 61 shows how to configure the AD8253 to output a
differential signal. An op amp, the AD8675, is used in an
inverting topology to create a differential voltage. VREF sets the
output midpoint according to the equation shown in the figure.
Errors from the op amp are common to both outputs and are
thus common mode. Likewise, errors from using mismatched
resistors cause a common-mode dc offset error. Such errors are
rejected in differential signal processing by differential input
ADCs or instrumentation amplifiers.
When using this circuit to drive a differential ADC, VREF can be
set using a resistor divider from the ADC reference to make the
output ratiometric with the ADC.
SETTING GAINS WITH A MICROCONTROLLER
+15
V
MICRO-
CONTROLLER
–15V
A0
A1
WR
+IN
–
IN
10F0.1µF
10F0.1µF
REF
AD8253
+
–
DGNDDGND
06983-059
Figure 60. Programming Gain Using a Microcontroller
+15
V
–15V
A0
A1
WR
+IN
10F
0.1F
10F
0.1F
AD8253
REF
G = 1
0.1µF
4.99k
4.99k
AD8675
0.1µF
+15V
–15V
V
REF
0V
V
OUT
A = V
IN
+ V
REF
2
2
V
OUT
B = –V
IN
+ V
REF
+2.5V
–2.5V
0V
+2.5V
–2.5V
0V
TIME
AMPLITUDE
0V
TIME
AMPLITUDE
+5
V
–5V
AMPLITUDE
56pF
+15V –15V
V
IN
+
–
+–
DGND
DGND
06983-060
Figure 61. Differential Output with Level Shift
AD8253
Rev. A | Page 22 of 24
DATA ACQUISITION
The AD8253 makes an excellent instrumentation amplifier
for use in data acquisition systems. Its wide bandwidth, low
distortion, low settling time, and low noise enable it to
condition signals in front of a variety of 16-bit ADCs.
Figure 63 shows the AD825x as part of a total data acquisition
system. The quick slew rate of the AD8253 allows it to condition
rapidly changing signals from the multiplexed inputs. An FPGA
controls the AD7612, AD8253, and ADG1209. In addition,
mechanical switches and jumpers allow users to pin strap the
gains when in transparent gain mode.
This system achieved −116 dB of THD at 1 kHz and a signal-to-
noise ratio of 91 dB during testing, as shown in Figure 62.
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–60
–10
–20
–30
–40
–50
0
05
06983-062
FREQUENCY (kHz)
AMPLITUDE (dB)
0
5 1015202530354045
Figure 62. FFT of the AD825x in a Total Data Acquisition System
Using the AD8253 1 kHz Signal
AD8253
2
+IN
–IN
A1
A0 VOUT
REF
–V
S
+V
S
DGND
5
3
4
9
1
7
10
11
12
13
14
15
16
6
2
S1A EN
DA
DB
GND
S2A
S3A
S4A
S1B
S2B
S3B
S4B
A0
A1
V
SS
V
DD
JMP
JMP
JMP
+12V –12V
+12V
–12V
JMP
JMP
–V
S
+5V
+5V
DGND
806
806
806
806
806
806
806
806
0
049.9
0
–CH1
+CH1
+CH2
–CH2
+CH3
–CH3
+CH4
–CH4
1nF
2k
2k
0.1µF
GND
+12V –12V
++
10µF 10µF
0.1µF
C
D
C
C
C
C
C3
0.1µF
C4
0.1µF
+5V
+5V
DGND
DGND
R8
2k
+IN AD7612
ADR435
ADG1209
DGND
ALTERA
EPF6010ATC144-3
8
0
0
1
10
6
WR
9
4
5
8
3
7
+
–
DGND
2k
DGND
06983-067
Figure 63. Schematic of ADG1209, AD8253, and AD7612 Used with the AD825x in a Total Data Acquisition System
AD8253
Rev. A | Page 23 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
0.23
0.08
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10 6
5
1
0.50 BSC
PIN 1
COPLANARITY
0.10
3.10
3.00
2.90
3.10
3.00
2.90
5.15
4.90
4.65
Figure 64. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8253ARMZ1–40°C to +85°C 10-Lead MSOP RM-10 Y0K
AD8253ARMZ-RL1
–40°C to +85°C 10-Lead MSOP RM-10 Y0K
AD8253ARMZ-R71
–40°C to +85°C 10-Lead MSOP RM-10 Y0K
AD8253-EVALZ1
Evaluation Board
1 Z = RoHS Compliant Part.
AD8253
Rev. A | Page 24 of 24
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06983-0-8/08(A)
