04/07/08
Benefits
lImproved Gate, Avalanche and Dynamic dv/dt
Ruggedness
lFully Characterized Capacitance and Avalanche
SOA
lEnhanced body diode dV/dt and dI/dt Capability
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IRFB4110PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
S
D
G
TO-220AB
D
GDS
Gate Drain Source
S
D
G
VDSS 100V
RDS
(
on
)
typ. 3.7m:
max. 4.5m:
ID
(
Silicon Limited
)
180A c
ID
(
Packa
g
e Limited
)
120A
Absolute Maximum Ratings
Symbol Parameter Units
I
D
@ T
C
= 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) A
I
D
@ T
C
= 100°C Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
I
DM
Pulsed Drain Current d
P
D
@T
C
= 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
V
GS
Gate-to-Source Voltage V
dv/dt Peak Diode Recovery fV/ns
T
J
Operating Junction and °C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
E
AS (Thermally limited)
Single Pulse Avalanche Energy emJ
I
AR
Avalanche Currentd A
E
AR
Repetitive Avalanche Energy gmJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
R
θJC
Junction-to-Case k––– 0.402
R
θCS
Case-to-Sink, Flat Greased Surface 0.50 ––– °C/W
R
θJA
Junction-to-Ambient j––– 62
300
Max.
180c
130c
670
120
190
See Fig. 14, 15, 22a, 22b
370
5.3
-55 to + 175
± 20
2.5
10lbxin (1.1Nxm)
PD - 97061C
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Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.033mH
RG = 25Ω, IAS = 108A, VGS =10V. Part not recommended for use
above this value.
S
D
G
ISD ≤ 75A, di/dt ≤ 630A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V
∆V(BR)DSS
/
∆TJ Breakdown Voltage Temp. Coefficient ––– 0.108 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 3.7 4.5 mΩ
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
gfs Forward Transconductance 160 ––– ––– S
QgTotal Gate Charge ––– 150 210 nC
Qgs Gate-to-Source Charge ––– 35 –––
Qgd Gate-to-Drain ("Miller") Charge ––– 43 –––
RGGate Resistance ––– 1.3 ––– Ω
td(on) Turn-On Delay Time ––– 25 ––– ns
trRise Time ––– 67 –––
td(off) Turn-Off Delay Time ––– 78 –––
tfFall Time ––– 88 –––
Ciss Input Capacitance ––– 9620 ––– pF
Coss Output Capacitance ––– 670 –––
Crss Reverse Transfer Capacitance ––– 250 –––
Coss eff. (ER) Effective Output Capacitance (Energy Related)
i
––– 820 –––
Coss eff. (TR) Effective Output Capacitance (Time Related)h––– 950 –––
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units
ISContinuous Source Current ––– ––– 170cA
(Body Diode)
ISM Pulsed Source Current ––– ––– 670
(Body Diode)di
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time ––– 50 75 ns TJ = 25°C VR = 85V,
––– 60 90 TJ = 125°C IF = 75A
Qrr Reverse Recovery Charge ––– 94 140 nC TJ = 25°C di
/
dt = 100A
/
µs
g
––– 140 210 TJ = 125°C
IRRM Reverse Recovery Current ––– 3.5 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
ID = 75A
RG = 2.6Ω
VGS = 10V g
VDD = 65V
TJ = 25°C, IS = 75A, VGS = 0V g
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 5mAd
VGS = 10V, ID = 75A g
VDS = VGS, ID = 250µA
VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125°C
MOSFET symbol
showing the
VDS = 50V
Conditions
VGS = 10V g
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 80V j
VGS = 0V, VDS = 0V to 80V h
Conditions
VDS = 50V, ID = 75A
ID = 75A
VGS = 20V
VGS = -20V
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
≤60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
1234567
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 25V
≤60µs PULSE WIDTH
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
-60 -40 -20 020 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 75A
VGS = 10V
0 50 100 150 200
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VGS, Gate-to-Source Voltage (V)
VDS= 80V
VDS= 50V
ID= 75A
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Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
0.0 0.5 1.0 1.5 2.0
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
-60 -40 -20 020 40 60 80 100120140160180
TJ , Temperature ( °C )
90
95
100
105
110
115
120
125
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5mA
0 20406080100120
VDS, Drain-to-Source Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Energy (µJ)
0 1 10 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100µsec
1msec
10msec
DC
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
20
40
60
80
100
120
140
160
180
ID, Drain Current (A)
Limited By Package
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
800
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 17A
27A
BOTTOM 108A
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) τi (sec)
0.09876251 0.000111
0.2066697 0.001743
0.09510464 0.012269
τJ
τJ
τ1
τ1
τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
τC
τC
Ci= τi/Ri
Ci= τi/Ri
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
250
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 108A
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
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Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VGS(th), Gate threshold Voltage (V)
ID = 250µA
ID = 1.0mA
ID = 1.0A
0200 400 600 800 1000
diF /dt (A/µs)
0
5
10
15
20
25
IRR (A)
IF = 30A
VR = 85V
TJ = 25°C
TJ = 125°C
0200 400 600 800 1000
diF /dt (A/µs)
0
5
10
15
20
25
IRR (A)
IF = 45A
VR = 85V
TJ = 25°C
TJ = 125°C
0200 400 600 800 1000
diF /dt (A/µs)
80
160
240
320
400
480
560
QRR (A)
IF = 30A
VR = 85V
TJ = 25°C
TJ = 125°C
0200 400 600 800 1000
diF /dt (A/µs)
80
160
240
320
400
480
560
QRR (A)
IF = 45A
VR = 85V
TJ = 25°C
TJ = 125°C
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Fig 22a. Switching Time Test Circuit Fig 22b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
15V
20V
VGS
Fig 23a. Gate Charge Test Circuit Fig 23b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
1K
VCC
DUT
0
L
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/08
TO-220AB packages are not recommended for Surface Mount Application.
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
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Note: "P" in assembly line
position indicates "Lead-Free"
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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