06/29/09
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HEXFET® Power MOSFET
Benefits
lImproved Gate, Avalanche and Dynamic dV/dt
Ruggedness
lFully Characterized Capacitance and Avalanche
SOA
lEnhanced body diode dV/dt and dI/dt Capability
l Lead-Free
l Halogen-Free
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
S
D
G
GDS
Gate Drain Source
PD - 96237
IRFB3004GPbF
TO-220AB
IRFB3004GPbF
V
DSS
40V
R
DS
(
on
)
typ. 1.4mΩ
max. 1.75mΩ
I
D
(Silicon Limited)
340A
c
I
D
(Package Limited)
195A
S
D
G
D
Absolute Maximum Ratings
Symbol Parameter Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
IDM Pulsed Drain Current
d
PD @TC = 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
VGS Gate-to-Source Voltage V
dv/dt Peak Diode Recovery
f
V/ns
TJ Operating Junction and
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited) Sin
g
le Pulse Avalanche Ener
g
y
e
mJ
IAR Avalanche Current
d
A
EAR Repetitive Avalanche Ener
g
y
d
mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case
jk
––– 0.40
RθCS Case-to-Sink, Flat Greased Surface, TO-220 0.50 –––
RθJA Junction-to-Ambient, TO-220 ––– 62
°C/W
-55 to + 175
± 20
2.5
10lbf
x
in (1.1N
x
m)
Max.
340
c
240
c
1310
195 A
°C
300
300
See Fig. 14, 15, 22a, 22b
380
4.4
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Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.016mH
RG = 25Ω, IAS = 195A, VGS =10V. Part not recommended for use
above this value .
S
D
G
ISD ≤ 195A, di/dt ≤ 930A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
Rθ is measured at TJ approximately 90°C.
RθJC value shown is at time zero
Static @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Volta
g
e 40 ––– ––– V
∆V
(BR)DSS
/
∆T
J
Breakdown Volta
g
e Temp. Coefficient ––– 0.037 ––– V/°C
R
DS(on)
Static Drain-to-Source On-Resistance ––– 1.4 1.75 mΩ
V
GS(th)
Gate Threshold Volta
g
e 2.0 ––– 4.0 V
I
DSS
Drain-to-Source Leaka
g
e Current ––– ––– 20 µA
––– ––– 250
I
GSS
Gate-to-Source Forward Leaka
e ––– ––– 100 nA
Gate-to-Source Reverse Leaka
g
e ––– ––– -100
R
G
Internal Gate Resistance ––– 2.2 ––– Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
g
fs Forward Transconductance 1170 ––– ––– S
Q
g
Total Gate Char
g
e ––– 160 240 nC
Q
gs
Gate-to-Source Char
g
e ––– 40 –––
Q
gd
Gate-to-Drain ("Miller") Char
g
e ––– 68 –––
Q
sync
Total Gate Char
g
e Sync. (Q
g
- Q
gd
)––– 92 –––
t
d(on)
Turn-On Delay Time ––– 23 ––– ns
t
r
Rise Time ––– 220 –––
t
d(off)
Turn-Off Delay Time ––– 90 –––
t
f
Fall Time ––– 130 –––
C
iss
Input Capacitance ––– 9200 ––– pF
C
oss
Output Capacitance ––– 2020 –––
C
rss
Reverse Transfer Capacitance ––– 1340 –––
C
oss
eff. (ER) Effective Output Capacitance (Energy Related)
i
––– 2440 –––
C
oss
eff. (TR) Effective Output Capacitance (Time Related)
h
––– 2690 –––
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units
I
S
Continuous Source Current ––– ––– 340
c
A
(Body Diode)
I
SM
Pulsed Source Current ––– ––– 1310 A
(Body Diode)
d
V
SD
Diode Forward Volta
g
e ––– ––– 1.3 V
t
rr
Reverse Recovery Time ––– 27 ––– ns T
J
= 25°C V
R
= 34V,
––– 31 ––– T
J
= 125°C I
F
= 195A
Q
rr
Reverse Recovery Char
g
e ––– 18 ––– nC T
J
= 25°C di/dt = 100A/µs
g
––– 41 ––– T
J
= 125°C
I
RRM
Reverse Recovery Current ––– 1.2 ––– A T
J
= 25°C
t
on
Forward Turn-On Time Intrinsic turn-on time is ne
g
li
g
ible (turn-on is dominated by LS+LD)
I
D
= 195A
R
G
= 2.7Ω
V
GS
= 10V
g
V
DD
= 26V
I
D
= 187A, V
DS
=0V, V
GS
= 10V
T
J
= 25°C, I
S
= 195A, V
GS
= 0V
g
integral reverse
p-n junction diode.
Conditions
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 5mA
d
V
GS
= 10V, I
D
= 195A
g
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 40V, V
GS
= 0V
V
DS
= 40V, V
GS
= 0V, T
J
= 125°C
MOSFET symbol
showing the
V
DS
=20V
Conditions
V
GS
= 10V
g
V
GS
= 0V
V
DS
= 25V
ƒ = 1.0 MHz, See Fig. 5
V
GS
= 0V, V
DS
= 0V to 32V
i
, See Fig. 11
V
GS
= 0V, V
DS
= 0V to 32V
h
Conditions
V
DS
= 10V, I
D
= 195A
I
D
= 187A
V
GS
= 20V
V
GS
= -20V
IRFB3004GPbF
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
4.8V
BOTTOM 4.5V
≤60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
ID, Drain-to-Source Current (A)
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
4.8V
BOTTOM 4.5V
1 2 3 4 5 6 7 8
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 25V
≤60µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 195A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 50 100 150 200
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
VGS, Gate-to-Source Voltage (V)
VDS= 32V
VDS= 20V
ID= 187A
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Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
0.0 0.5 1.0 1.5 2.0
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
-60 -40 -20 020 40 60 80 100120140160180
TJ , Temperature ( °C )
40
42
44
46
48
50
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5mA
-5 0 5 10 15 20 25 30 35 40 45
VDS, Drain-to-Source Voltage (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Energy (µJ)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
200
400
600
800
1000
1200
1400
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 30A
54A
BOTTOM 195A
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
50
100
150
200
250
300
350
ID, Drain Current (A)
Limited By Package
1 10 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100µsec
1msec
10msec
DC
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
Thermal Response ( Z thJC ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
τJ
τJ
τ1
τ1
τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
Ci i/Ri
Ci= τi/Ri
τ
τC
τ4
τ4
R4
R4Ri (°C/W) τi (sec)
0.00646 0.000005
0.10020 0.000124
0.18747 0.001374
0.10667 0.008465
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Tj = 150°C and
Tstart =25°C (Single Pulse)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
40
80
120
160
200
240
280
320
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 195A
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Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VGS(th), Gate threshold Voltage (V)
ID = 250µA
ID = 1.0mA
ID = 1.0A
100 200 300 400 500
diF /dt (A/µs)
50
100
150
200
250
300
350
QRR (nC)
IF = 78A
VR = 34V
TJ = 25°C
TJ = 125°C
100 200 300 400 500
diF /dt (A/µs)
0
50
100
150
200
250
300
350
400
QRR (nC)
IF = 117A
VR = 34V
TJ = 25°C
TJ = 125°C
100 200 300 400 500
diF /dt (A/µs)
2
3
4
5
6
7
8
9
10
IRRM (A)
IF = 78A
VR = 34V
TJ = 25°C
TJ = 125°C
100 200 300 400 500
diF /dt (A/µs)
1
2
3
4
5
6
7
8
9
10
11
IRRM (A)
IF = 117A
VR = 34V
TJ = 25°C
TJ = 125°C
IRFB3004GPbF
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Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
D.U.T. VDS
ID
IG
3mA
VGS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
VDS
90%
10%
VGS
t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
VGS
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
TO-220AB Part Marking Information
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/2009
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