CY62146EV30 MoBL®
4-Mbit (256K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05567 Rev. *G Revised July 14, 2011
Features
■Very high speed: 45 ns
■Temperature ranges
❐Industrial: –40 °C to +85 °C
❐Automotive-A: –40 °C to +85 °C
■Wide voltage range: 2.20 V to 3.60 V
■Pin compatible with CY62146DV30
■Ultra low standby power
❐Typical standby current: 1 A
❐Maximum standby current: 7 A
■Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■Easy memory expansion with CE and OE features
■Automatic power down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Available in a Pb-free 48-ball very fine ball grid array (VFBGA)
and 44-pin TSOP II Packages
Functional Description
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features an
advanced circuit design designed to provide an ultra low active
current. Ultra low active current is ideal for providing More
Battery Life (MoBL®) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that significantly reduces power consumption by 80
percent when addresses are not toggling.The device can also be
put into standby mode reducing power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from the I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the “Truth Table” on page 10 for a
complete description of read and write modes.
Logic Block Diagram
256K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
CE
WE
BHE
A16
A0
A1
A9
A10
BLE
A17
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 2 of 17
Contents
Pin Configuration .............................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 5
Data Retention Characteristics ....................................... 5
Switching Characteristics ................................................6
Switching Waveforms ......................................................7
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Documentation Conventions ......................................... 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ....................................................... 17
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 3 of 17
Pin Configuration
Figure 1. 48-Ball VFBGA Pinout [1, 2] Figure 2. 44-Pin TSOP II [1]
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA)
Standby ISB2 (A)
f = 1 MHz f = fmax
Min Typ [3] Max Typ [3] Max Typ [3] Max Typ [3] Max
CY62146EV30LL Ind’l/Auto-A 2.2 3.0 3.6 45 ns 2 2.5 15 20 1 7
WE
A11
A10
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
A7
I/O0
BHE
NC
A2
A1
BLE
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
326
5
41
D
E
B
A
C
F
G
H
A16
NC
VCC
VCC VSS
A17
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
15
A
16
A
8
A
9
A
10
A
11
A
13
A
14
A
12
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
17
Notes
1. NC pins are not connected on the die.
2. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 4 of 17
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage to ground
potential .......................... –0.3 V to + 3.9 V (VCCmax + 0.3 V)
DC voltage applied to outputs
in High-Z state [4, 5]............. –0.3 V to 3.9 V (VCCmax + 0.3 V)
DC input voltage [4, 5] ........ –0.3 V to 3.9 V (VCC max + 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Static Discharge Voltage ......................................... >2001 V
(per MIL-STD-883, Method 3015)
Latch-up Current ..................................................... >200 mA
Operating Range
Device Range
Ambient
Temperature VCC [6]
CY62146EV30 Industrial/
Auto-A
–40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
45 ns (Ind’l/Auto-A)
UnitMin Typ [7] Max
VOH Output high voltage IOH = –0.1 mA 2.0 – – V
IOH = –1.0 mA, VCC > 2.70 V 2.4 – – V
VOL Output low voltage IOL = 0.1 mA – – 0.4 V
IOL = 2.1 mA, VCC > 2.70 V – – 0.4 V
VIH Input high voltage VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 V
VCC= 2.7 V to 3.6 V 2.2 – VCC + 0.3 V
VIL Input LOW Voltage VCC = 2.2 V to 2.7 V –0.3 – 0.6 V
VCC= 2.7 V to 3.6 V –0.3 – 0.8 V
IIX Input leakage current GND < VI < VCC –1 – +1 A
IOZ Output leakage current GND < VO < VCC, Output disabled –1 – +1 A
ICC VCC operating supply current f = fmax = 1/tRC VCC = VCC(max),
IOUT = 0 mA
CMOS levels
–15 20mA
f = 1 MHz – 2 2.5
ISB1 Automatic CE power down
current — CMOS inputs CE > VCC0.2 V,
VIN > VCC–0.2 V or VIN < 0.2 V
f = fmax (Address and data only),
f = 0 (OE, BHE, BLE and WE), VCC = 3.60 V
–1 7A
ISB2 [8] Automatic CE power down
current — CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–1 7A
Capacitance
Parameter[9] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 5 of 17
Thermal Resistance
Parameter[10] Description Test Conditions VFBGA TSOP II Unit
JA Thermal resistance
(Junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
75 77 C/W
JC Thermal resistance
(Junction to case)
10 13 C/W
Figure 3. AC Test Loads and Waveforms
Parameters 2.50 V 3.0 V Unit
R1 16667 1103
R2 15385 1554
RTH 8000 645
VTH 1.20 1.75 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [11] Max Unit
VDR VCC for data retention 1.5 – – V
ICCDR [12] Data retention current VCC = 1.5 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Industrial/Auto-A – 0.8 7 A
tCDR [10] Chip deselect to data
retention time
–0––ns
tR [13] Operation recovery time – 45 – – ns
Figure 4. Data Retention Waveform
VCC
VCC
Output
R2
30 pF
Including
JIG and
Scope
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
Output V
All Input Pulses
RTH
R1
Equivalent to: Thevenin Equivalent
VCC(min)
VCC(min)
tCDR
VDR >1.5 V
DATA RETENTION MODE
tR
VCC
CE
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
12. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR spec. Other inputs can be left floating.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 6 of 17
Switching Characteristics
Over the Operating Range
Parameter[14,15] Description
45 ns (Industrial/Auto-A)
UnitMin Max
Read Cycle
tRC Read cycle time 45 – ns
tAA Address to data valid – 45 ns
tOHA Data hold from address change 10 – ns
tACE CE LOW to data valid –45ns
tDOE OE LOW to data valid –22ns
tLZOE OE LOW to Low-Z [16] 5–ns
tHZOE OE HIGH to High-Z [16, 17] –18ns
tLZCE CE LOW to Low-Z [16] 10 – ns
tHZCE CE HIGH to High-Z [16, 17] –18ns
tPU CE LOW to power up 0–ns
tPD CE HIGH to power down –45ns
tDBE BLE / BHE LOW to data valid –22ns
tLZBE BLE / BHE LOW to Low-Z [16] 5–ns
tHZBE BLE / BHE HIGH to High-Z [16, 17] –18ns
Write Cycle [18]
tWC Write cycle time 45 – ns
tSCE CE LOW to write end 35 – ns
tAW Address setup to write end 35 – ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 35 – ns
tBW BLE / BHE LOW to write end 35 – ns
tSD Data setup to write end 25 – ns
tHD Data hold from write end 0 – ns
tHZWE WE LOW to High-Z [16, 17] –18ns
tLZWE WE HIGH to Low-Z [16] 10 – ns
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5.
15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 7 of 17
Switching Waveforms
Figure 5. Read Cycle 1 (Address Transition Controlled) [19, 20]
Figure 6. Read Cycle No. 2 (OE Controlled) [20, 21]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
19. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE and BHE, BLE transition LOW.
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 8 of 17
Figure 7. Write Cycle No. 1 (WE Controlled) [22, 23, 24]
Figure 8. Write Cycle No. 2 (CE Controlled) [22, 23, 24]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN
NOTE 25
tBW
tSCE
DATA IO
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA IO
OE
BHE/BLE
NOTE 25
Notes:
22. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
23. Data I/O is high impedance if OE = VIH.
24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
25. During this period, the I/Os are in output state and input signals must not be applied.
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 9 of 17
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [26]
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [26]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 27
CE
ADDRESS
WE
DATA IO
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 27
DATA I/O
ADDRESS
CE
WE
BHE/BLE
Notes
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state and input signals must not be applied.
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 10 of 17
Truth Table
CE[28] WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High-Z Deselect/power-down Standby (ISB)
L X X H H High-Z Output disabled Active (ICC)
L H L L L Data out (I/O0–I/O15) Read Active (ICC)
L H L H L Data out (I/O0–I/O7);
I/O8–I/O15 in High-Z
Read Active (ICC)
L H L L H Data out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read Active (ICC)
L H H L L High-Z Output disabled Active (ICC)
L H H H L High-Z Output disabled Active (ICC)
L H H L H High-Z Output disabled Active (ICC)
L L X L L Data in (I/O0–I/O15) Write Active (ICC)
L L X H L Data in (I/O0–I/O7);
I/O8–I/O15 in High-Z
Write Active (ICC)
L L X L H Data in (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write Active (ICC)
Note
28. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 11 of 17
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
45 CY62146EV30LL-45BVXI 51-85150 48-ball VFBGA (Pb-free) Industrial
CY62146EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free)
CY62146EV30LL-45ZSXA 51-85087 44-pin TSOP II (Pb-free) Automotive-A
Please contact your local Cypress sales representative for availability of other parts
Ordering Code Definitions
Temperature Grade: I = Industrial, A = Automotive
Package Type: BVX / ZSX = VFBGA (Pb-free) / TSOP II (Pb-free)
xx = Speed Grade
LL = Low Power
Voltage Range = 3 V typical
E = Process Technology 90 nm
Buswidth = × 16
Density = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY -xx xxx
621 46EV30 LL I/A
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 12 of 17
Package Diagrams
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
51-85150 *F
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 13 of 17
Figure 12. 44-Pin TSOP II, 51-85087
Package Diagrams (continued)
MAX
MIN.
DIMENSION IN MM (INCH)
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
EJECTOR MARK
Z
A
Z
Z
Z
Z
X
A
10.058 (0.396)
10.262 (0.404)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
TOP VIEW BOTTOM VIEW
PLANE
SEATING
18.517 (0.729)
0.800 BSC
0°-5°
0.400(0.016)
0.300 (0.012)
1.194 (0.047)
0.991 (0.039)
0.150 (0.0059)
0.050 (0.0020)
(0.0315)
18.313 (0.721)
BASE PLANE
0.10 (.004)
11.938 (0.470)
PIN 1 I.D.
44
1
11.735 (0.462)
10.058 (0.396)
10.262 (0.404)
22
23
51-85087-*C
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 14 of 17
Acronyms Documentation Conventions
Units of Measure
Acronym Description
BHE byte high enable
BLE byte low enable
CMOS complementary metal oxide semiconductor
CE chip enable
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
VFBGA very fine ball gird array
WE write enable
Symbol Unit of Measure
°C degrees Celsius
Amicroamperes
mA milliampere
MHz megahertz
ns nanoseconds
pF picofarads
Vvolts
ohms
Wwatts
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 15 of 17
Document History Page
Document Title: CY62146EV30 MoBL®, 4-Mbit (256K x 16) Static RAM
Document Number: 38-05567
REV. ECN NO. Orig. of
Change
Submission
Date Description of Change
** 223225 AJU See ECN New Data Sheet
*A 247373 SYT See ECN Changed Advance Information to Preliminary
Moved Product Portfolio to Page 2
Changed VCC stabilization time in footnote #8 from 100 s to 200 s
Removed Footnote #14(tLZBE) from Previous revision
Changed ICCDR from 2.0 A to 2.5 A
Changed typo in Data Retention Characteristics (tR) from 100 s to tRC ns
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18
ns for 45 ns Speed Bin
Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for
45 ns Speed Bin
Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns
Speed Bin
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
45 ns Speed Bin
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Changed tDBE from 15 to 18 ns for 35 ns Speed Bin
Changed Ordering Information to include Pb-Free Packages
*B 414807 ZSD See ECN Changed from Preliminary information to Final
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62146EV30
Changed ball E3 from DNU to NC
Removed the redundant foot note on DNU.
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ values from 0.7 A to 1 A and Max values from 2.5
A to 7 A.
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed ICCDR from 2.5 A to 7 A.
Added ICCDR typical value.
Changed tLZOE from 3 ns to 5 ns
Changed tLZCE and tLZWE from 6 ns to 10 ns
Changed tLZBE from 6 ns to 5 ns
Changed tHZCE from 22 ns to 18 ns
Changed tPWE from 30 ns to 35 ns.
Changed tSD from 22 ns to 25 ns.
Updated the package diagram 48-ball VFBGA from *B to *D
Updated the ordering information table and replaced the Package Name column
with Package Diagram.
*C 925501 VKN See ECN Added footnote #8 related to ISB2 and ICCDR
Added footnote #12 related AC timing parameters
*D 2678796 VKN/PYRS 03/25/2009 Added Automotive-A information
*E 2944332 06/04/2010 VKN Added Contents
Removed byte enable from footnote #2 in Electrical Characteristics
Added footnote related to chip enable in Truth Table
Updated Package Diagrams
Updated links in Sales, Solutions, and Legal Information
*F 3109050 12/13/2010 PRAS Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
CY62146EV30 MoBL®
Document Number: 38-05567 Rev. *G Page 16 of 17
*G 3302915 07/14/2011 RAME Updated as per template. Added Units of Measure table.
Updated all the notes.
Ordering Code Definition updated.
Removed the references of AN1064 SRAM system guidelines from the
datasheet.
Document Title: CY62146EV30 MoBL®, 4-Mbit (256K x 16) Static RAM
Document Number: 38-05567
REV. ECN NO. Orig. of
Change
Submission
Date Description of Change
Document Number: 38-05567 Rev. *G Revised July 14, 2011 Page 17 of 17
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
CY62146EV30 MoBL®
© Cypress Semiconductor Corporation, 2004–2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive cypress.com/go/automotive
Clocks & Buffers cypress.com/go/clocks
Interface cypress.com/go/interface
Lighting & Power Control cypress.com/go/powerpsoc
cypress.com/go/plc
Memory cypress.com/go/memory
Optical & Image Sensing cypress.com/go/image
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC® Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
