03/06/06
Benefits
lWorldwide Best RDS(on) in TO-220
lImproved Gate, Avalanche and Dynamic dV/dt
Ruggedness
lFully Characterized Capacitance and Avalanche
SOA
lEnhanced body diode dV/dt and dI/dt Capability
www.irf.com 1
D2Pak
IRFS3207
TO-220AB
IRFB3207 TO-262
IRFSL3207
IRFB3207
IRFS3207
IRFSL3207
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
S
D
G
SDG SDG SDG
V
DSS
75V
R
DS(on)
typ.
3.6m
:
max. 4.5m
:
ID180A
Absolute Maximum Ratings
Symbol Parameter Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V A
ID @ TC = 100°C Continuous Drain Current , VGS @ 10V
IDM Pulsed Drai n Current
d
PD @TC = 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
VGS Gate-to-Sour ce Voltage V
dV/dt Peak Diode Recovery
f
V/ns
TJ Operating Junction and °C
TSTG Storage Temperat ure Range
Soldering Temperature, for 10 seconds
( 1 .6 m m fro m case )
Mounting torque, 6-32 or M3 screw
Avalanche Char acteri sti cs
EAS (Thermally limited) Single Pulse Avalanche Energy
e
mJ
IAR Aval anche Curr ent
c
A
EAR Repetitive Avalanche Energy
g
mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case
k
––– 0.45
RθCS Case- to-Sink, Flat Greased Surface , TO-220 0.50 ––– °C/W
RθJA Junction-to-Ambient, TO-220
k
––– 62
RθJA Junction-to-Ambient (PCB Mount) , D2Pak
jk
––– 40
910
See Fig. 14, 15, 16a, 16b,
330
5.8
-55 to + 175
± 20
2.2
10lb
x
in (1.1N
x
m)
300
Max.
180
c
130
c
720
PD - 96893C
IRF/B/S/SL3207
2www.irf.com
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.33mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 75A, di/dt ≤ 500A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
S
D
G
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
Stat ic @ TJ = 25°C (unless otherwis e specified)
Symbol Parameter Min. Typ. Max. Units
V
(BR)DSS Drain-to-S ourc e Breakdown Voltage 75 ––– ––– V
∆
V
(BR)DSS
∆
T
J Breakdown Voltage Temp. Coefficient ––– 0.069 ––– V/°C
R
DS(on) Static D rain-to-Sourc e On-Resistance ––– 3.6 4. 5 mΩ
V
GS(th) Gate Threshold Voltage 2.0 ––– 4.0 V
DSS Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
GSS Gate-to-Source Forward Leakage ––– ––– 200 nA
Gate-to- Source Rever se Leakage ––– ––– -200
R
GGate Input Resistance ––– 1.2 ––– Ωf = 1MHz, open drain
Dynamic @ TJ = 25°C (unles s ot herwise specified)
Symbol Parameter Min. Typ. Max. Units
gfs Forward Trans conduct ance 150 ––– ––– S
Q
gTotal Gate Charge ––– 180 260 nC
Q
gs Gate-to- Source Charge ––– 48 –––
Q
gd Gate-t o-Dr ain ("Miller") Charge ––– 68 –––
d(on) Turn-On Delay Time ––– 29 ––– ns
rRise Time ––– 120 –––
d(off) Turn-Off Delay Time ––– 68 –––
fFall Time ––– 74 –––
C
iss I nput Capaci tance ––– 7600 ––– pF
C
oss Output Capacitance ––– 710 –––
C
rss Reverse Transfer Capacitance ––– 390 –––
C
oss
eff. (ER)
Effecti ve Output Capacitanc e (Energy Related)
––– 920 –––
C
oss
eff. (TR)
Effecti ve Output Capacitanc e (Time Related)
h
––– 1010 –––
Diode Charac teristi cs
Symbol Parameter Min. Typ. Max. Units
SContinuous Sour ce Curr ent ––– ––– 180
c
A
(Body D iode)
SM Pulsed Source Current ––– ––– 720
(Body D iode)
di
V
SD Diode Forward Voltage ––– ––– 1.3 V
rr Reverse Recovery Time –– – 42 63 n s
T
J
= 25°C
V
R
= 64V,
––– 49 74
T
J
= 125°C
F
= 75A
Q
rr Rever se Recovery Charge ––– 65 98 nC
T
J
= 25°C
di/dt = 100A/µs
g
––– 92 140
T
J
= 125°C
RRM Rever se Recovery Curr ent ––– 2.6 ––– A
T
J
= 25°C
on Forward Turn-On Time Intrinsic turn-on tim e is negligible (turn- on is dominated by LS+LD)
ID = 75A
RG = 2.6Ω
VGS = 10V
g
VDD = 48V
TJ = 25°C, IS = 75A, VGS = 0V
g
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
d
VGS = 10V, ID = 75A
g
VDS = VGS, ID = 250µA
VDS = 75V, VGS = 0V
VDS = 75V, VGS = 0V, TJ = 125°C
MOSFET symbol
showing t he
VDS = 60V
Conditions
VGS = 10V
g
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V
j
, See Fig.11
VGS = 0V, VDS = 0V to 60V
h
, See Fig. 5
Conditions
VDS = 50V, ID = 75A
ID = 75A
VGS = 20V
VGS = -20V
IRF/B/S/SL3207
www.irf.com 3
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1 110 100
VDS, Drain-t o-Source Volt age (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60µs PULSE WID TH
Tj = 25°C
4.5V
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
0.1 110 100
VDS, Drain-t o-Source Volt age (V)
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60µs PULSE WID TH
Tj = 175°C
4.5V
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
4.0 5.0 6.0 7.0 8.0 9.0
VGS, Gate-to-Source Voltage (V)
1.0
10.0
100.0
1000.0
ID, Drain-to-Source Current
(Α)
VDS = 50V
≤ 60µs PULSE WID TH
TJ = 25°C
TJ = 175°C
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temper ature (°C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 75A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage ( V)
0
2000
4000
6000
8000
10000
12000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 40 80 120 160 200 240 280
QG T otal G ate Charge (nC)
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
VDS= 60V
VDS= 38V
ID= 75A
IRF/B/S/SL3207
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
25 50 75 100 125 150 175
TC , Case T em perature ( °C)
0
50
100
150
200
ID , Drain Current (A)
LIMITED BY PACKAGE
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Juncti on Temperature (°C)
70
80
90
100
V(BR)DSS , Drain-to-Source Breakdown Voltage
20 30 40 50 60 70 80
VDS, Drain-t o-Source Volt age (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Energy (µJ)
25 50 75 100 125 150 175
Starting TJ, Junct ion Temperature (°C)
0
1000
2000
3000
4000
EAS, Single Pulse Avalanche Energy (mJ)
I D
TOP 12A
16A
BOTTOM 75A
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
VSD, Source- to-Drain V oltage (V)
0.1
1.0
10.0
100.0
1000.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
1 10 100 1000
VDS , D rain- toSource Volt age (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single P ulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
DC
IRF/B/S/SL3207
www.irf.com 5
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse D ur ation ( sec)
0.0001
0.001
0.01
0.1
1
Thermal Response ( Z
thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthj c + Tc
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Ri (°C/W) τi (sec)
0.2151 0.001175
0.2350 0.017994
τJ
τJ
τ1
τ1τ2
τ2
R1
R1R2
R2
τ
τ
C
Ci= i/Ri
Ci= τi/Ri
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neitherTjmax nor Iav (max)
is exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
25 50 75 100 125 150 175
Starting TJ , Junction T em perature (°C)
0
200
400
600
800
1000
EAR , Avalanche Energy (mJ)
TOP Singl e Pulse
BOTTOM 1% Duty Cy cle
ID = 75A
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
Avalanche Current (A)
0.05
Dut y Cycle = Single Puls e
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C .
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Si ngle Pulse)
IRF/B/S/SL3207
6www.irf.com
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperat ure ( ° C )
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VGS(th) Gate threshold Voltage (V)
ID = 1.0A
ID = 1.0mA
ID = 250µA
Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / µs)
0
100
200
300
400
QRR - (nC)
IF = 30A
VR = 64V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / µs)
2
4
6
8
10
12
14
16
IRRM - (A)
IF = 30A
VR = 64V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / µs)
0
100
200
300
400
QRR - (nC)
IF = 45A
VR = 64V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / µs)
2
4
6
8
10
12
14
16
IRRM - (A)
IF = 45A
VR = 64V
TJ = 125°C
TJ = 25°C
IRF/B/S/SL3207
www.irf.com 7
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
VGS
VDS
9
0%
10%
td(on) td(off)
trtf
VGS
Pulse W idth < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
1K
VC
C
DUT
0
L
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
IRF/B/S/SL3207
8www.irf.com
TO-220AB packages are not recommended for Surface Mount Application.
TO-220AB Part Marking Information
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
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IRF/B/S/SL3207
www.irf.com 9
TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
/2*2
5(&7,),(5
,17(51$7,21$/
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IRF/B/S/SL3207
10 www.irf.com
D2Pak (TO-263AB) Part Marking Information
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
'$7(&2'(
<($5
:((.
$ $66(0%/<6,7(&2'(
5(&7,),(5
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)6
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IRF/B/S/SL3207
www.irf.com 11
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/06
D2Pak (TO-263AB) Tape & Reel Information
3
4
4
TRR
F
EED DIRECTION
1.85 (.073)
1.65 (.065)
1.6 0 ( . 06 3)
1.5 0 ( . 05 9)
4.10 (.161)
3.90 (.153)
TRL
F
E E D DIRE C TION
10.9 0 (.429)
10.7 0 (.421) 16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (. 957
)
23.90 (. 941
)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13. 5 0 (. 5 32)
12. 8 0 (. 5 04)
330.00
(14.173)
MAX.
27. 40 (1.079)
23. 90 (.941)
60.00 (2.362
)
MIN.
30.40 (1.197)
MAX.
26.4 0 (1. 039 )
24.4 0 (.9 61)
NO TES :
1. COMFORMS TO E IA-418.
2. CONTR OLLING DIME NS I O N: MI LL I M ETE R.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/