Rev. 4243G–8051–05/03
1
Features
•80C52 Compatible
– 8051 Pin and Instru ction Compatible
– Four 8-bit I/O Ports (or 6 in 64/68 Pins Packages)
– Three 16-bit T ime r/ Counte rs
– 256 bytes Scratch Pad RAM
– 7 Interrupt Sources With 4 Priority Levels
•ISP (In-System Programming) Using Standard VCC Power Supply
•Boot Flash Contains Low Level Flash Programming Routines and a Default Serial
Loader
•High-Sp eed Architecture
–40 MHz in Standard Mode
–20 MHz in X2 Mode (6 Clocks/Machine Cycle)
•64K bytes On-chip Flash Program/Data Memory
–Byte and Page (128 bytes) Erase and Write
–100K W rite Cycles
•On-chip 1024 Bytes Expanded RAM (XRAM)
–Software Selectable Size (0, 256, 512, 768, 1024 bytes)
–768 Bytes Selected at Reset for T87C51RD2 Compatibility
•Dual Data Pointer
Variable Length MOVX for Slow RAM/Peripherals
•Improved X2 Mode with Independant Selection for CPU and Each Peripheral
•2K bytes EEPROM Block for Data Storage
–100K W rite Cycl e
•Programmable Counter Array with
–High Speed Output
–Compare/Capture
–Pulse Width Modulator
Watchdog Timer Capabilities
Asynchronous Port Reset
Full-duplex Enhanced UART
Low EMI (Inhibit ALE)
–Hardware Watchdog Timer (One-time Enabled with Reset-out)
•Power Control Modes :
–Idle Mode
–Power-down Mode
•Power Supply:
–M version: Commercial and Industrial
4.5V to 5 .5V: 40 MHz (X1 Mode), 20 MHz (X2 Mode)
3V to 5.5V: 33 MHz (X1 Mode), 16 MHz (X2 Mode)
–L version: Commercial and industrial
2.7V to 3 .6V: 25 MHz (X1 Mode), 12 MHz (X2 Mode)
•Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40 to +85°C)
•Packages: PDIL40, PLCC44, VQFP44, PLCC68, VQFP64
0 to 40 MHz
Flash
Programmab le
8-bit
Microcontroller
T89C51RD2
2T89C51RD2 4243G–8051–05/03
Description T89C51RD2 i s hig h perfor mance CM OS Flash versio n of th e 80C51 CMOS s ingle c hip
8-bit microcontr oller. It contains a 64 Kbytes Flash memory block for program and for
data.
The 64 Kbytes Flash memory can be pr ogrammed either in paral lel mode or in serial
mode with the ISP capability or with software. The programming voltage is internally
generated from the standard VCC pin.
The T89C51RD2 retains all features of the ATMEL 80C52 with 256 bytes of internal
RAM, a 7-source 4-level interrupt controller and three timer/counters.
In addition, the T89C51RD2 has a Pr ogrammable Counter Array, an XRAM of 1024
bytes, an E EPRO M of 2 048 b yte s, a Hardwar e W atchdog Timer , a mor e ver satil e s eria l
channel that facilitates multiprocessor c ommunication (EUART) and a speed improve-
ment mechanism (X2 mode). Pinout is either the standard 40/44 pins of the C52 or an
extended version with 6 ports in a 64/68 pins package.
The fully static design of the T89C51RD2 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
The T89C 51RD2 has 2 software- selec table mo des of reduc ed activ ity for furthe r reduc-
tion in power consumption. In the idle mode the CPU is frozen while the peripherals and
the inte rrupt syst em are sti ll operati ng. I n the po wer-down mode the RAM i s saved an d
all other functions are inoperative.
The added features of the T89C51RD2 makes it more powerful for applications that
need pulse widt h m odu lation, h igh s pe ed I/O an d cou nti ng ca pab il iti es s uc h as al arms ,
motor control, corded phones, smart card readers.
Table 1. Memory Size
PDIL40
PLCC44
VQFP44 1.4 Flash (bytes) EEPROM
(bytes) XRAM (bytes) TOTAL RAM
(bytes) I/O
T89C51RD2 64K 2K 1024 1280 32
PLCC68
VQFP64 1.4 Flash (bytes) EEPROM
(bytes) XRAM (bytes) TOTAL RAM
(bytes) I/O
T89C51RD2 64K 2K 1024 1280 48
3
T89C51RD2
4243G–8051–05/03
Block Diagram
Notes: 1. Alternate function of Port 1.
2. Only available on high pin count packages.
3. Alternate function of P ort 3.
Timer 0 INT
RAM
256x8
T0
T1 RxD
TxD
WR
RD
EA
PSEN
ALE/
XTAL2
XTAL1
EUART
CPU
Timer 1
INT1
Ctrl
INT0
(3)
(3)
C51
CORE
(3) (3) (3) (3)
Port 0
P0
Port 1 Port 2 Port 3
Parallel I/O Ports & Ext. Bus
P1
P2
P3
XRAM
1Kx8
IB-bus
PCA
RESET
PROG
Watch
Dog
PCA
ECI
Vss
VCC
(3)(3) (1)
(1)
Timer2
T2EX
T2
(1) (1)
Port 5Port 4
P5
P4
(2)(2)
Flash
64Kx8 EEPROM
2Kx8
4T89C51RD2 4243G–8051–05/03
Pin Configuration
Note: NIC = No Internal Connection
P1.7CEX4
P1.4/CEX1
RST
P3.0/RxD
P3.1/TxD
P1.3CEX0
1
P1.5/CEX2
P1.6/CEX3
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS P2.0/AD8
P2.1/AD9
P2.2/AD10
P2.3/AD11
P2.4/AD12
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/AD15
P2.5/AD13
P2.6/AD14
P1.0/T2
P1.2/ECI
P1.1/T2EX VC C
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
PDIL
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
18 19 23222120 262524 27 28
5 4 3 2 1 6 44 43 42 41 40
P1.4/CEX1
P1.0/T2
P1.1/T2EX
P1.3/CEX0
P1.2/ECI
NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
NIC*
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
43 42 41 40 3944 38 37 36 35 34
P1.4/CEX1
P1.0/T2
P1.1/T2EX
P1.3/CEX0
P1.2/ECI
NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
NIC*
P2.7/A15
P2.5/A13
P2.6/A14
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5/CEX2
P1.6/CEX3
P1.7/CEx4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
NIC*
NIC*
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
PLCC
1213 17161514 201918 2122
33
32
31
30
29
28
27
26
25
24
23
VQFP44 1.4
1
2
3
4
5
6
7
8
9
10
11
5
T89C51RD2
4243G–8051–05/03
12
10
15
14
13
11
16
17
18
19
20
21
22
23
24
25
26
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
VSS1
P1.0/T2
P4.0
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
P4.2
23567 4 1 686766656463
60
59
58
57
56
55
36 37 38 39 40 4129 30 31 32 33 34 3527 28 42 43
48
49
50
51
52
53
54
PSEN
P5.3
P0.5/AD5
P0.6/AD6
NIC
P0.7/AD7
EA
NIC
ALE/PROG
NIC
P2.7/A15
P2.6/A14
P5.2
P0.4/AD4
P5.4
P5.1
P2.5/A13
NIC
P1.7/CEX4
RST
NIC
NIC
NIC
P3.0/RxD
NIC
NIC
NIC
P3.1/TxD
P3.3/INT1
P5.0
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
P2.0/A8
VSS
P4.6
P4.5
XTAL1
XTAL2
NIC
PLCC 68
89 62 61
P1.5/CEX2
P1.6/CEX3
P3.4/T0
P3.5/T1
44
45
46
47
P4.4
P3.6/WR
P4.3
P3.7/RD
P3.2/INT0
PSEN
P5.4
P5.3
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC
ALE/PROG
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
P5.0
P0.4/AD4
58 5051525354555657596061626364 49
VSS
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
P2.0/A8
P4.6
P4.5
NIC
XTAL1
XTAL2
P3.7/RD
P4.4
P4.3
P2.4/A12
P3.6/WR
42
34
35
36
37
38
39
40
41
43
44
45
46
47
48
33
P1.0/T2
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
VSS1
P4.0
P1.1/T2EX
P1.2/EC1
P1.3/CEX0
P4.1
P1.4/CEX1
P5.5
7
15
14
13
12
11
10
9
8
6
5
4
3
2
1
16
NIC
P3.4/T0
P3.2/INT0
P3.1/TxD
NIC
NIC
P3.0/RxD
NIC
NIC
RST
P1.7/CEX4
P1.6/CEX3
P1.5/CEX2
P4.2
P3.5/T1
2618 19 20 21 22 23 24 25 27 28 29 30 31 3217
VQFP64 1.4
P3.3/INT1
PLCC68
VQFP64 1.4
6T89C51RD2 4243G–8051–05/03
Table 2. Pin Description
Mnemonic
Pin Num b e r
Type Name and FunctionDIL LCC VQFP 1.4
VSS 20 22 16 I Ground: 0V reference
Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection.
VCC 40 44 38 I Power Supply: This is the power supply voltage for nor mal, idle and power-down
operation
P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I /O port. Port 0 pins that have 1s written to
them float and can be used as high impedance inputs. Port 0 must be polarized to VCC
or VSS in order to prevent any parasitic current consumption. Port 0 is also the
multiplexed low-order address and data bus during access to ext ernal program and
data memory . In this application, it uses strong internal pull-up when emitting 1s. Port 0
also inputs the code bytes during EPROM programming. External pull-ups are required
during program verification during which P0 outputs th e code bytes.
P1.0-P1.7 1-8 2-9 40-44
1-3 I/O Por t 1: Port 1 is an 8-bit bidirec tional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can b e used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current because
of the internal pull-ups. Port 1 also receives the low-order address byte during memory
programming and verification.
Alternate functions for TSC8x54/58 Port 1 include:
12 40 I/OT2 (P1. 0): Timer/Counter 2 external count input/Clockout
23 41 IT2EX (P1.1): Ti mer/Counter 2 Reload/Capture/Direction Control
34 42 IECI (P1.2): External Clock for the PCA
45 43 I/OCEX0 (P1.3): Capture/Compare External I/O for PCA module 0
56 44 I/OCEX1 (P1.4): Capture/Compare External I/O for PCA module 1
67 1 I/OCEX2 (P1.5): Capture/Compare External I/O for PCA module 2
78 2 I/OCEX3 (P1.6): Capture/Compare External I/O for PCA module 3
89 3 I/OCEX4 (P1.7): Capture/Compare External I/O for PCA module 4
P2.0-P2.7 21-28 24-31 18-25 I/O Po r t 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can b e used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current because
of the internal pull-ups. Port 2 emits the high-order address byte during fetches from
external program memory and during accesses to external data memory that use 16-
bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups
emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX
@Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order
address bits during EPROM programming and verification:
P2.0 to P2.5 for RB devices
P2.0 to P2.6 for RC devices
P2.0 to P2.7 for RD devices.
P3.0-P3.7 10-17 11,
13-19 5,
7-13 I/O Por t 3: Port 3 is an 8-bit bidirec tional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can b e used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current because
of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as
listed below.
10 11 5 I RXD (P3.0): Serial input port
11 13 7 O TXD (P3.1): Serial output port
7
T89C51RD2
4243G–8051–05/03
12 14 8 I INT0 (P3.2): External interrupt 0
13 15 9 I INT1 (P3.3): External interrupt 1
14 16 10 I T0 (P3. 4): Timer 0 external input
15 17 11 I T1 (P3. 5): Timer 1 external input
16 18 12 O WR (P3.6): External data memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe
Reset 9 10 4 I/O Reset: A high on this pin for two machine cycles while the oscillator is running, resets
the device. An internal diffused resistor to VSS permits a power-on reset using only an
external capacitor to VCC. This pin is an output when the hardware watchdog forces a
system reset .
ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory . In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for
external timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory. This pin is also the program pulse input ( P RO G) during Flash
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE
will be inactive during internal fetches.
PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, P SE N is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSE N is not activated during fetches from internal program
memory.
EA 31 35 29 I External Access Enable: EA must be externally held low to enable the device to fetch
code from external program memory locations 0000H to FFFFH (RD). If sec urity level
1 is programmed, EA will be internally latched on Reset.
XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillat or amplifier
Table 2. Pin Description (Continued)
Mnemonic
Pin Num b e r
Type Name and FunctionDIL LCC VQFP 1.4
8T89C51RD2 4243G–8051–05/03
SFR Mapping The Special Function Registers (SFRs) of the T89C51RD2 fall into the following
categories:
•C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
•I/O port registers: P0, P1, P2, P3, P4, P5
•Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
•Serial I/O port registers: SADDR, SADEN, SBUF, SCON
•Power and clock control registers: PCON
•Hardwar e Watchdog Timer regis te r: WDTRS T, WD T PRG
•Interrupt system registers: IE, IP, IPH
•Flash and EEPROM registers: FCON, EECON, EETIM
•Others: AUXR, AUXR1, CKCON
9
T89C51RD2
4243G–8051–05/03
Table 3 below shows all SFRs with their address and their reset value.
Table 3. SFR Table
Bit
Addressable Non Bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h CH
0000 0000 CCAP0H
XXXX XXXX CCAP1H
XXXX XXXX CCAP2H
XXXX XXXX CCAP3H
XXXX XXXX CCAP4H
XXXX XXXX FFh
F0h B
0000 0000 F7h
E8h P5
1111 1111 CL
0000 0000 CCAP0L
XXXX XXXX CCAP1L
XXXX XXXX CCAP2L
XXXX XXXX CCAP3L
XXXX XXXX CCAP4L
XXXX XXXX EFh
E0h ACC
0000 0000 E7h
D8h CCON
00X0 0000 CMOD
00XX X000 CCAPM0
X000 0000 CCAPM1
X000 0000 CCAPM2
X000 0000 CCAPM3
X000 0000 CCAPM4
X000 0000 DFh
D0h PSW
0000 0000 FCON
XXXX 0000 EECON
XXXX XX00 EETIM
0000 0000 D7h
C8h T2CON
0000 0000 T2MOD
XXXX XX00 RCAP2L
0000 0000 RCAP2H
0000 0000 TL2
0000 0000 TH2
0000 0000 CFh
C0h P4
1111 1111 P5
1111 1111 C7h
B8h IP
X000 000 SADEN
0000 0000 BFh
B0h P3
1111 1111 IPH
X000 0000 B7h
A8h IE
0000 0000 SADDR
0000 0000 AFh
A0h P2
1111 1111 AUXR1
XXXX 00X0 WDTRST
XXXX XXXX WDTPRG
XXXX X000 A7h
98h SCON
0000 0000 SBUF
XXXX XXXX 9Fh
90h P1
1111 1111 97h
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 AUXR
XX0X 1000 CKCON
X000 0000 8Fh
80h P0
1111 1111 SP
0000 0111 DPL
0000 0000 DPH
0000 0000 PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
reserved
10 T89C51RD2 4243G–8051–05/03
Enhanced Features In comparison to the original 80C52, the T89C51RD2 implements some new features,
which are:
•The X2 option
•The Dual Data Pointer
•The extended RAM
•The Programmable Counter Array (PCA)
•The Watchdog
•The 4 level interrupt priority system
•The power-off flag
•The ONCE mode
•The ALE disabling
•Some enhanced features are also located in the UART and the Timer 2
X2 Feature and Clock
Generation The T89C51RD2 core needs only 6 clock periods per machine cycle. This feature called
”X2” provides the following advantages:
•Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
•Save power consumption while keeping same CPU power (oscillator power saving).
•Save power consumption by dividing dynamically operating frequency by 2 in
operating and idle modes.
•Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the ori ginal C51 com patibili ty, a divider by 2 is inser ted between th e
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1
input. In X2 mod e, as thi s div id er is by pas s ed, t he s ignal s o n XT A L1 m us t hav e a cycl ic
ratio between 40 to 60%. Figure 1 shows the clock generation block diagram. X2 bit is
validated on XT AL1÷2 rising edge to avoid glit ches when switching from X2 to STD
mode. Figure 2 shows the mode switching waveforms.
Figure 1. Clock Generation Diagram
XTAL1 2
CK CON re g
X2
State Machine: 6 clock cycles.
CPU control.
FOSC
FXTAL
0
1
XTAL1:2
11
T89C51RD2
4243G–8051–05/03
Figure 2. Mode Switching Waveforms
The X2 bit in the CKCON register (Table 4) allows to switch from 12 clock periods per
instruction to 6 clock periods and vice versa. At reset, the standard speed is activated
(STD mode). Setting this bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, SiX2, PcaX2 and WdX2 bits in the CKCON register (Table 4)
allow to s witch from s tandard pe ripheral speed (12 clock periods pe r peripher al clock
cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bi ts
are active only in X2 mode.
More information about the X2 mode can be found in the application note ANM072 "How
to take advantage of the X2 features in TS80C51 microcontroller".
Table 4. CKCON Register
CKCON - Clock Control Register (8Fh)
XTA L1:2
XTAL1
CPU clock
X2 bit
X2 ModeSTD Mode STD Mode
76543210
- WdX2 PcaX2 SiX2 T2X2 T1X2 T0X2 X2
Bit
Number Bit
Mnemonic Description
7-Reserved
6WdX2
Watchdog clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5PcaX2
Programmable Counter Array clock (This control bit is validated when the CPU
clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4SiX2
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3T2X2
Timer2 clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
12 T89C51RD2 4243G–8051–05/03
Reset Value = X000 0000b
Not bit address ab le
2T1X2
Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
1T0X2
Timer0 clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
0X2
CPU clock
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the
peripherals.
Set to select 6clock periods per machine cycle (X2 mode) and to enable the
individual peripherals "X2" bits.
Bit
Number Bit
Mnemonic Description
13
T89C51RD2
4243G–8051–05/03
Dual Data Pointer
Register Ddptr The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an exter-
nal data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them
(Refer to Figure 3).
Figure 3. Use of Dual Pointe r
Table 5. AUXR1: Auxiliary Register 1
Extern al Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
AUXR1
Address 0A2H ----GF30-DPS
Reset value X X X X 0 0 X 0
Symbol Function
- Not implemented, reserved for future use. (1)
1. User sof tware sh ould no t write 1s to res erved b its . These bit s may be us ed in fu ture 805 1
family products to invoke new feature. In that case, the reset value of the new bit will
be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
2. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
DPS Data Pointer Selection.
DPS Operating Mode
0DPTR0 Selected
1DPTR1 Selected
GF3 This bit is a general purpose user flag(2).
14 T89C51RD2 4243G–8051–05/03
Application Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare, search ...) are well
served by u sing one data poin ter a s a ’source’ poin ter and the oth er one as a "des tina-
tion" pointer.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a par-
ticul ar state, bu t simply to ggles it. In simple routin es, such as the block move examp le,
only the fa ct t hat DP S i s togg led in th e pr op er se quence matt er s, n ot i ts a ctu al value. In
other words, th e block m ove rout ine wor ks the sa me wheth er DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
15
T89C51RD2
4243G–8051–05/03
Expanded RAM (XRAM) The T89C51RD2 provide additional Bytes of random access memory (RAM) space for
increased data parameter handling and high level language usage.
T89C51RD2 devices have expanded RAM in external data spac e; Maximum size and
location are described in Table 6.
The T89C51RD2 has internal data memory that is mapped into four separate segments.
The four segments are:
•1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly
addressable.
•2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable
only.
•3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly
addressable only.
•4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and
with the EXTRAM bit cleared in the AUXR register. (See Table 7.)
The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes ca n be access ed by indirect ad dressing only. T he Upper 128 bytes occupy
the same add r ess space as th e S FR. T ha t m eans t hey ha ve the s ame ad dres s, but ar e
physically separate from SFR space.
Figure 4. Internal and External Data Memory Address
When an instr uction acce sses an interna l location above address 7FH, the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
•Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data ,accesses the SFR at location 0A0H (which is P2).
Table 6. Description of Expanded RAM
Port XRAM size
Address
Start End
T89C51RD2 1024 00h 3FFh
XRAM
Upper
128 bytes
Internal
Ram
Lower
128 bytes
Internal
Ram
Special
Function
Register
80 80
00
FF or 3FF FF
00
FF
External
Data
Memory
0000
0100 or 0400
FFFF
indirect accesses direct accesses
direct or indirect
accesses
16 T89C51RD2 4243G–8051–05/03
•Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # dat a where R0 contains 0A0H, accesses the data byte
at address 0A0H, rather than P2 (whose address is 0A0H).
•The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first bytes of external data memory. The bits XRS0 and XRS1
are used to hide a part of the available XRAM as explained in Table 7. This can be
useful if external peripherals are mapped at addresses already used by the internal
XRAM.
•With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An
access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For
example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to
external data memory locations higher than the accessible size of the XRAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, so with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to XRAM above 0FFH can only be done thanks to the
use of DPT R.
•With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0
and any output port pins can be used to output higher order address bits. This is to
provide the external paging capability. MOVX @DPTR will generate a sixteen-bit
address. Port2 outputs the high-order eight address bits (the contents of DPH) while
Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and
MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7
(RD).
The s tack point er (SP) ma y be loc ated any where in the 256 byt es RAM (l ower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
17
T89C51RD2
4243G–8051–05/03
Table 7. Auxiliary Register (08EH)
AUXR
Address 08EH - - M0 - XRS1 XRS0 EXTRA
MAO
Reset value X X 0 X 1 0 0 0
Symbol Function
- Not implemented, reserved for future use. (1)
1. User sof tware sh ould no t write 1s to res erved b its . These bit s may be us ed in fu ture 805 1
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
AO Disable/Enable ALE
AO Operating Mode
0ALE is emitted at a constant rate of 1/6 t he oscillator frequency (or 1/3 if X2
mode is used)
1 ALE is active only during a MOVX or MOVC instruct ion
EXTRAM Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR
EXTRAM Operating Mode
0 Internal XRAM access using MO V X @ Ri/ @ DPTR
1 Ext ernal data memory access
XRS0
XRS1 XRAM size: Accessible size of the XRAM
XRS1 :0 XRAM size
0 0 256 bytes
0 1 512 bytes
1 0 768 bytes (default)
1 1 1024 bytes
M0 Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the
value of M0
M0 Pulse length in clock period
06
130
18 T89C51RD2 4243G–8051–05/03
Timer 2 The timer 2 in the T89C51RD2 is compatible with the timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2
and TL2, c onnected in cascade. It is control led by T2CON regi ster (See Table 8) and
T2MOD register (See Table 9). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2
selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer
clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These
modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON ), as
described in the ATMEL Wireless and Micrcontrollers 8-bit Microcontroller Hardware
description.
Refer to the ATMEL Wireless and Micrcontrollers 8-bit Microcontroller Hardware
description for the description of Capture and Baud Rate Generator Modes.
In T89C51RD2 Timer 2 includes the following enhancements:
•Auto-reload mode with up or down counter
•Programmable clock-output
Auto-Reload Mode The auto-reload mode configures timer 2 as a 16- bit timer or event counter with auto-
matic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the
ATMEL Wireless and Micrcontrollers 8-bit Microcontroller Hardware description). If
DCEN bit is set, timer 2 ac ts as a n Up/do wn t imer/co unter as show n in Fi gure 5. In t his
mode the T2EX pin controls the direction of count.
When T2EX is high, timer 2 counts up. Timer overflow occurs a t FFFFh which sets th e
TF2 fl ag a nd g ener ates a n interr upt reques t. T he overfl ow a lso c ause s the 16 -bit v alu e
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2 EX is low , tim er 2 count s down. T imer un derflow oc curs wh en the c ount in th e
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direc-
tion of the c oun t. E XF2 does n ot g ene ra te a ny int er ru pt. This bi t can be used to pr ovid e
17-bit resolution.
19
T89C51RD2
4243G–8051–05/03
Figure 5. Auto-Reload Mode Up/Down Counter (DCEN = 1)
Programmable Clock-Output In the clo ck-out m ode, tim er 2 op erates as a 50%-dut y-c ycle, pr ogramma ble cl ock g en-
erator (See Figure 6) . The input clock increments TL2 at frequency FOSC/2. The timer
repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H
and R CAP 2L regi s ter s are lo aded into T H2 a nd T L2. In th is m ode , t ime r 2 over fl ows d o
not generate interrupts. The formula gives the clock-out frequency as a function of the
system oscill ato r freque nc y and the value in the RCAP2H and RCAP2L registe rs :
For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz
(FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
•Set T2OE bit in T2MOD register.
•Clear C/T2 bit in T2CON register.
•Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
•Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depending on the application.
•To start the timer, set TR2 run control bit in T2CON register.
It is possible to use timer 2 as a baud rate generator and a c lock generator simulta-
neously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
(DOWN COUNTING RELOAD
C/T2
TF2
TR2
T2
EXF2
TH2
(8-bit)
TL2
(8-bit)
RCAP2H
(8-bit)
RCAP2L
(8-bit)
FFh
(8-bit) FFh
(8-bit)
TOGGL
(UP COUNTING RELOAD VALUE)
TIMER 2
INTERRUPT
XTAL1 :12
FOSC
FXTAL
0
1
T2CONreg T2CONreg
T2CONreg
T2CONreg
T2EX:
if DCEN=1, 1=UP
if DCEN=1, 0=DOWN
if DCEN = 0, up
Clock OutFrequency–Fosc
4 65536 RCAP2H
–RCAP2L⁄()×
--------------------------------------------------------------------------------------------
=
20 T89C51RD2 4243G–8051–05/03
Figure 6. Clock-Out Mode C/T2 = 0
:2
EXF2
TR2
OVEFLOW
T2EX
TH2
(8-bit)
TL2
(8-bit)
TIMER 2
RCAP2H
(8-bit)
RCAP2L
(8-bit)
T2OE
T2
XTAL1
T2CON reg
T2CON reg
T2CON reg
T2MOD reg
INTERRUPT
QD
Toggle
EXEN2
21
T89C51RD2
4243G–8051–05/03
Table 8. T2C ON Regi ster
T2CON - Timer 2 Control Register (C8h)
Reset Value = 0000 0000b
Bit addressable
76543210
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number Bit
Mnemonic Description
7TF2
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter
mode (DCEN = 1)
5RCLK
Receive Clock bit
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4TCLK
Transmi t Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as tra n smit clock for serial port in mode 1 or 3.
3EXEN2
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected,
if timer 2 is not us ed to clock the serial port.
2TR2
Timer 2 Run control bit
Clear to turn off timer 2.
Set to tur n on timer 2.
1C/T2#
Tim e r /Counter 2 select bi t
Clear for timer operation (input from internal clock system: FOSC).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for
clock out mode.
0 CP/RL2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if
EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
22 T89C51RD2 4243G–8051–05/03
Table 9. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
Reset Val ue = XXXX XX00 b
Not bit address ab le
76543210
------T2OE DCEN
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1T2OE
Ti m e r 2 Output Enable bit
Clear to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
0 DCEN Down Counter Enable bit
Clear to disable timer 2 as up/down counter.
Set to enable timer 2 as up/down count er.
23
T89C51RD2
4243G–8051–05/03
Programmable Counter
Array PCA The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accu-
racy. T he PCA co nsists of a dedic ated timer /counte r which se rves as the time ba se for
an arra y of fiv e com pare/ ca pture m odule s. I ts clock inpu t can be program med to count
any one of the following signals:
•Oscillator frequency ÷ 12 (÷ 6 in X2 mode)
•Oscillator frequency ÷ 4 (÷ 2 in X2 mode)
•Timer 0 overflow
•External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
•rising and/or falling edg e captu re,
•software timer,
•high-speed output, or
•pulse width modulator.
Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog
Timer", page 32).
When the compare/capture modules are programmed in the capture mode, software
timer, or hig h speed ou tpu t mode, an in terrupt c an be gene rated when the modu le exe-
cutes it s function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
Thes e pins ar e liste d belo w. If one or seve ral bit s in the port are not use d for th e PCA,
they can still be used for standard I/O.
The PCA timer is a common time base for all five modules (See F igure 7). The tim er
count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (See
Table 10) and can be programmed to run at:
•1/12 the oscillator frequency. (Or 1/6 in X2 Mode)
•1/4 the oscillator frequency. (Or 1/2 in X2 Mode)
•The Timer 0 overflow
•The input on the ECI pin (P1.2)
PCA component External I/O Pin
16-bit Counter P1.2 / ECI
16-bit Module 0 P1.3 / CEX0
16-bit Module 1 P1.4 / CEX1
16-bit Module 2 P1.5 / CEX2
16-bit Module 3 P1.6 / CEX3
16-bit Module 4 P1.7 / CEX4
24 T89C51RD2 4243G–8051–05/03
Figure 7. PCA Timer/Counter
Table 10. CMOD: PCA Counter Mode Register
CIDL CPS1 CPS0 ECF
It
CH CL
16 bit up/down co unter
To PCA
modules
Fosc /12
Fosc / 4
T0 OVF
P1.2
Idle
CMOD
0xD9
WDTE
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
overflow
CMOD
Address 0D9H CIDL WDT
E- - - CPS1 CPS0 ECF
Reset value 0 0 X X X 0 0 0
Symbol Function
CIDL Counter Idle control: CIDL = 0 program s the PCA Counter to continue functioning during
idle Mode. CIDL = 1 programs it to be gated off during idle.
WDTE Watchdo g Timer E nable: WDT E = 0 disables Watchdog Timer function on PCA Module 4.
WDTE = 1 enables it.
- Not implemented, reserved for future use. (1)
1. User sof tware sh ould no t write 1s to res erved b its . These bit s may be us ed in fu ture 805 1
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
CPS1 PCA Count Pulse Select bit 1.
CPS0 PCA Count Pulse Select bit 0.
CPS
1CPS
0Selected PCA input. (2)
2. fosc = oscillator frequency
0 0 Internal clock fosc/12 ( Or fosc/6 in X2 Mode).
0 1 Internal clock fosc/4 ( Or fosc/2 in X2 Mode).
1 0 Timer 0 Overflow
1 1 External clock at ECI/P1.2 pin (max rate = fosc/ 8)
ECF PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an
interrupt. ECF = 0 disables that function of CF.
25
T89C51RD2
4243G–8051–05/03
The CMOD SFR includes three additional bits associated with the PCA (See Figure 7
and Table 10).
•The CIDL bit which allows the PCA to stop during idle mode.
•The WDTE bit which enables or disables the watchdog function on module 4.
•The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer
(CF) and each modu le (Ref er to Table 11).
•Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by
clearing this bit.
•Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
•Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc.) and are set by hardware when either a match or a capture occurs. These flags
also can only be cleared by software.
Table 11. CCON: PCA Counter Control Register
The watchdog timer function is implemented in module 4 (See Figure 10).
CCON
Address 0D8H CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
Reset value 0 0 X 0 0 0 0 0
Symbol Function
CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags
an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but
can only be cleared by software.
CR PCA Counter Run control bit. Set by soft ware to turn the PCA counter on. Must be cleared
by software to turn the PCA counter off.
- Not implemented, reserved for future use. (1)
1. User sof tware sh ould no t write 1s to res erved b its . These bit s may be us ed in fu ture 805 1
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
26 T89C51RD2 4243G–8051–05/03
The PCA interrupt system is shown in Figure 8.
Figure 8. PCA Interrupt System
PCA Modules: each one of t he five compa re/captur e modul es has si x poss ible fun c-
tions. It can perform:
•16-bit Capture, positive-edge triggered,
•16-bit Capture, negative-edge triggered,
•16-bit Capture, both positive and negative-edge triggered,
•16-bit Software Timer,
•16-bit High Speed Output,
•8-bit Pulse Width Modulator.
In addition, module 4 can be used as a Watchdog Timer.
Each mod ule in the PCA has a s pecial function r egis ter ass ociated wi th it. The se r egis-
ters are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 12). The
registers contain the bits that control the mode that each module will operate in.
•The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt when a match or
compare occurs in the associated module.
•PWM (CCAPMn.1) enables the pulse width modulation mode.
•The TOG bit (CCAPMn.2) when set causes the CEX output associated with the
module to toggle when there is a match between the PCA counter and the module's
capture/compare register.
•The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter and the module's
capture/compare register.
•The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge
that a capture input will be active on. The CAPN bit enables the negative edge, and
the CAPP bit enables the positive edge. If both bits are set both edges will be
enabled and a capture will occur for either transition.
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
Module 4
Module 3
Module 2
Module 1
Module 0
ECF
PCA Timer/Counter
ECCFn CCAPMn.0CMOD.0 IE.6 IE.7
To Interrupt
priority decoder
EC EA
27
T89C51RD2
4243G–8051–05/03
•The last bit in the register ECOM (CCAPMn.6) when set enables the comparator
function.
Table 13 shows the CCAPMn settings for the various PCA functions.
.
Table 12. CCAPMn: PCA Modules Compare/Capture Control Registers
Table 13. PCA Module Modes (CCAPMn Registers)
CCAPMn
Address
n = 0 - 4
CCAPM0=0DAH
CCAPM1=0DBH
CCAPM2=0DCH
CCAPM3=0DDH
CCAPM4=0DEH
-ECO
Mn CAPP
nCAPN
nMATn TOGn PWM
mECCF
n
Reset value X 0 0 0 0 0 0 0
Symbol Function
- Not implemented, reserved for future use. (1)
1. User sof tware sh ould no t write 1s to res erved b its . These bit s may be us ed in fu ture 805 1
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
ECOMn Enable Comparator. ECOMn = 1 enables the comparator function.
CAPPn Capture Posit ive, CAPPn = 1 enables positive edge capture.
CAPNn Capture Negative, CAPNn = 1 enables negative edge capture.
MATn Match. When MATn = 1, a match of the PCA counter with this module’s compare/capture
register causes the CCFn bit in CCON to be set, flagging an interrupt.
TOGn Toggle. When TOGn = 1, a match of the PCA count er with this module’s compare/capture
register causes the CEXn pin to toggle.
PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse
width modulated output.
ECCFn E nable CCF interrupt. Enables compare/capture flag CCFn in the CCON register t o
generate an interrupt.
ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function
0000000 No Operation
X10000X
16-bit capture by a positive-edge
trigger on CEXn
X01000X
16-bit capture by a negative trigger
on CEXn
X11000X
16-bit capture by a transition on
CEXn
100100X
16-bit Software Timer / Compare
mode.
1 0 0 1 1 0 X 16-bit High Speed Output
1000010 8-bit PWM
28 T89C51RD2 4243G–8051–05/03
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and thes e a re the re gisters that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output (See Table 14 &
Table 15)
Table 14. CCAPnH: PCA Modules Capture/Compare Registers High
Table 15. CCAPnL: PCA Modules Capture/Compare Registers Low
Table 16. CH: PCA Counter High
Table 17. CL: PCA Counter Low
1 0 0 1 X 0 X Watchdog Timer (module 4 only)
CCAPnH
Address
n = 0 - 4
CCAP0H=0FAH
CCAP1H=0FBH
CCAP2H=0FCH
CCAP3H=0FDH
CCAP4H=0FEH
76543210
Reset value 0 0 0 0 0 0 0 0
CCAPnL
Address
n = 0 - 4
CCAP0L=0EAH
CCAP1L=0EBH
CCAP2L=0ECH
CCAP3L=0EDH
CCAP4L=0EEH
76543210
Reset value 0 0 0 0 0 0 0 0
CH
Address 0F9H
76543210
Reset value 0 0 0 0 0 0 0 0
CL
Address 0E9H
76543210
Reset value 0 0 0 0 0 0 0 0
ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function
29
T89C51RD2
4243G–8051–05/03
PCA Capture Mode To use on e of the PC A module s in the cap ture mo de eithe r one or bo th of the CCA PM
bits CAP N a nd CAPP f or tha t mo dul e m us t be s et. Th e ex te rn al CEX input for th e m od-
ule (on port 1) is sampled for a transition. When a valid transition occurs the PCA
hardware loads the value of the PCA counter registers (CH and CL) into the module’s
capture r egi ster s (CCAP nL an d CCAPnH) . I f th e CCFn bi t f or the m odu le in the CCO N-
SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated
(Refer to Figure 9).
Figure 9. PCA Capture Mode
16-bit Software Timer/
Compare Mode The PCA mod ules can be used as software tim ers by settin g both the ECOM and MAT
bits in the mod ules CCAPMn regi ster. The PCA timer will be compar ed to the module’s
capture registers and when a match occurs an interrupt will occur if the CCFn (CCON
SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 10).
CF CR CCON
0xD8
CH CL
CCAPnH CCAPnL
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
PCA Counter/Timer
ECOMn CCAPMn, n= 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
Cex.n
Capture
30 T89C51RD2 4243G–8051–05/03
Figure 10. PCA Compare Mode and PCA Watchdog Timer
Before e nab li ng E CO M bi t, CCAP nL a nd CCAPnH s hou ld be s et wi th a non ze ro va lu e,
otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while mo difying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
High Speed Output Mode In this mode the CEX output (on port 1) as sociated with the PCA module will toggle
each time a match occurs between the PCA counter and the module's capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR
must be set (See Figu re 11).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
CH CL
CCAPnH CCAPnL
ECOMn CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16 bit comparator Match
CCON
0xD8
PCA IT
Enable
PCA counter/timer
RESET *
CIDL CPS1 CPS0 ECF CMOD
0xD9
WDTE
* Only for Module 4
Reset
Write to
CCAPnL
Write to
CCAPnH
CF CCF2 CCF1 CCF0
CR CCF3
CCF4
10
31
T89C51RD2
4243G–8051–05/03
Figure 11. PCA High Speed Output Mode
Before e nab li ng E CO M bi t, CCAP nL a nd CCAPnH s hou ld be s et wi th a non ze ro va lu e,
otherwise an unwanted match could happen.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while mo difying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
Pulse Width Modulator Mode Al l of the PCA module s can b e used a s PWM out puts. F igure 12 sh ows the PW M func-
tion. T he frequen cy of t he output depends on the source for the P CA time r. All o f the
module s will h ave the sam e freque ncy of ou tput beca use they all shar e the PCA ti mer.
The duty cycle of each module is independently variable using the module's capture
register CCAPLn. When the value of the PCA CL SFR is less than the value in the mod-
ule's CCAPL n SFR the outpu t w ill be low, when it is equal to or gr eater t han the outpu t
will be high. Whe n CL overflows from FF to 00, CCAP Ln is reloaded with the v alue in
CCAPHn. T his allows upd ating the PWM wi thout glit ches. The P WM and ECOM bi ts in
the module's CCAPMn register must be set to enable the PWM mode.
CH CL
CCAPnH CCAPnL
ECOMn CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16 bit comparator Match
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
Enable
CEXn
PCA counter/timer
Write to
CCAPnH
Reset
Write to
CCAPnL
10
32 T89C51RD2 4243G–8051–05/03
Figure 12. PCA PWM Mode
PCA Watchdog Timer An on-boa rd watchdog ti mer is avai lable with the PCA to imp rove the rel iability of the
system without increasing chip count. Watchdog timers are useful for systems that are
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only
PCA module that can be programmed as a watchdog. However, this module can still be
used for othe r mode s i f the watc hd og i s n ot ne eded . Fig ur e 10 shows a diagr am of h ow
the watchdog works. The user pre-load s a 16-bit v alue in the compare registers. Jus t
like the other compare modes, this 16-bit value is compared to the PCA timer value. If a
match is allowed to occu r, an internal r eset will be genera ted. This will n ot cause the
RST pin to be driven hi gh.
In order to hold off the reset, the user has three options:
•1. periodically change the compare value so it will never match the PCA timer,
•2. periodically change the PCA timer value so it will never match the compare
values, or
•3. disable the watchdog by clearing the WDTE bit before a match occurs and then
re-enable it.
The first two options ar e more r el iable bec aus e the watc hdog timer is neve r di sabl ed as
in option #3. If the program c ounter ever goes astray, a mat ch will eve ntually occu r and
cause an in ter nal r es et. The second o pti on i s a lso n ot r ec omm end ed i f ot her P CA m od-
ules are being used. Remember, the PCA timer is the time base for all modules;
changing the time base for other modules would not be a good idea. Thus, in most appli-
cations the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
CL
CCAPnH
CCAPnL
ECOMn CCAPMn, n= 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
8 bit comparator CEXn
“0”
“1”
Š
<
Enable
PCA counter/timer
Overflow
33
T89C51RD2
4243G–8051–05/03
Serial I/O Port The serial I/O port in the T89C51RD2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as
an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex
modes (Mode s 1, 2 and 3 ). As ynch rono us tr ansm iss ion and re cep tion can o ccu r simu l-
taneously and at different baud rates
Serial I/O port includes the following enhancements:
•Framing error detection
•Automatic address recognition
Framing Er ror D etect ion Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framin g bi t erro r de tec tio n feat ur e, se t SMOD 0 bit in PCO N regi s-
ter (See Figure 13).
Figure 13. Framing Error Block Diagram
When thi s feat ur e is ena ble d , t he re cei v er chec ks e ac h inc om in g da ta f ra me for a va li d
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 20.) bit is set.
Software may examine F E bit after each reception to c heck for data errors. Once s et,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits c annot clear FE bit. When FE feature is enable d, RI r ise s on stop bit i nstead of th e
last data bit (See Figure 14. and Figure 15.).
Figure 14. UART Timings in Mode 1
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART framing error cont rol
SM0 to UART mode control (SMOD0 = 0)
Set FE bit if stop bit is 0 (framing error) (SMO D0 = 1)
SCON (98h)
PCON (87h)
Data byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD D7D6D5D4D3D2D1D0
FE
SMOD0=1
34 T89C51RD2 4243G–8051–05/03
Figure 15. UART Timings in Modes 2 and 3
Automatic Address
Recognition The aut oma tic addres s r ec ogn iti on feat ure i s en abl ed when th e m ul tiproce ss or c om mu-
nication feature is enabled (SM2 bit in SCON register is set).
Imple mente d in hard ware, automati c addre ss rec ogniti on enha nces th e multip roces sor
communication feature by allowing the serial port to examine the address of each
inco ming command fram e. Only when the se rial port reco gnizes it s own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired , you may enabl e the automat ic address recogniti on feature in mode 1. In this
configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the
received command frame address matches the device’s address and is ter min ate d by a
valid stop bit.
To supp ort automatic a ddr es s reco gni tio n , a devic e i s ide nti fie d by a giv en add re ss and
a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Given Address Each devi ce has an i ndiv idua l ad dress that is specif ie d in SADD R regis ter; t he SADEN
register is a mask byte that contains don’t-care bits (defined by zeros) to form the
device’s given address. The don’t-care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
RI
SMOD0=0
Data byte Ninth
bit Stop
bit
Start
bit
RXD D8D7D6D5D4D3D2D1D0
RI
SMOD0=1
FE
SMOD0=1
35
T89C51RD2
4243G–8051–05/03
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bi t; for slav es B and C, bit 0 is a 1. To com-
munic ate with slave A o nly, the ma ster must send an addre ss wher e bit 0 is clea r (e.g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e.g. 1111 0011b).
To communicate with slaves A , B and C, the master must send an address with bi t 0
set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t-care bits, e.g.:
SADDR 0101 0110b
SADEN 1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR=1111 0010b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the s lave s, the ma ster mus t send a n add ress F Fh. To com mun icate with slav es A
and B, but not slave C, the master can send and address FBh.
Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and
broadc ast addr esses are XXXX XXXXb (all don’t-care bits). This ensures that the serial
port will reply to any ad dress, and so, that it is backwards c ompatible with the 80C51
microcontrollers that do not support automatic address recognition.
Table 18. SADEN - Slave Address Mask Register (B9h)
Reset Value = 0000 0000b
Not bit address ab le
76543210
36 T89C51RD2 4243G–8051–05/03
Table 19. SADDR - Slave Address Register (A9h)
Reset Value = 0000 0000b
Not bit address ab le
Table 20. SCON Register
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
76543210
76543210
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number Bit
Mnemonic Description
7FE
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0 Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
6SM1
Serial port Mode bit 1
SM0 SM1 Mode Description Baud Rate
0 0 0 Shift Register FXTAL/12 (/6 in X2 mode)
0 1 1 8-bit UART Variable
1 0 2 9-bit UART FXTAL/64 or FXTAL/32 (/32 or 16 in X2 mode)
1 1 3 9-bit UART Variable
5SM2
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
4REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2RB8
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of
the stop bit in the other modes.
0RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 14. and
Figure 15. in the other mod e s.
37
T89C51RD2
4243G–8051–05/03
Table 21. PCON Register
PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit address ab le
Power-off flag reset value will be 1 only after a power on (cold r eset). A warm reset
doesn’t affect the value of this bit.
76543210
SMOD1 SMOD0 -POF GF1 GF0 PD IDL
Bit
Number
Bit
Mnemoni
c Description
7SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
5-
Reserved
The value read from this b it is indeterminate. Do not set this bit.
4POF
Power-Off Fla g
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
3GF1
Gener a l pur pose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2GF0
Gener a l pur pose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0IDL
Idle m o de bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
38 T89C51RD2 4243G–8051–05/03
Interrupt System The T89C51RD2 has a total of 7 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA glo-
bal interrupt. These interrupts are shown in Figure 16.
Figure 16. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enab le register (See T able 23.). This register also contai ns a
global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority lev-
els by se ttin g or c le arin g a bit in the Interrupt Pri ority re g ister ( See Tab le 24.) a nd i n th e
Interrupt Priority High register ( See Table 22). shows the bit values and priority levels
associated with each combination.
Table 22. Priority Level Bit Values
IE1
0
3
High priority
interrupt
Interrupt
polling
sequence, decreasing from
high to low priority
Low priority
interrupt
Global Disable
Individual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IP
IE0
0
3
0
3
0
3
0
3
0
3
0
3
PCA IT
IPH.x IP.x Interrupt Level Priority
0 0 0 (Lowest)
01 1
10 2
1 1 3 (Highest)
39
T89C51RD2
4243G–8051–05/03
A low-pr iori ty inte rrupt can be int errupt ed by a high priori ty inte rrupt, but not b y an other
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
reques t of high er prio rity lev el is s ervic ed. If in terrupt r eques ts of th e same priori ty leve l
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 23. IE Register
IE - Interrupt Enable Register (A8h)
Reset Value = 0000 0000b
Bit addressable
76543210
EA EC ET2 ES ET1 EX1 ET0 EX0
Bit
Number Bit
Mnemonic Description
7EA
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or
clearing its own interrupt enable bit.
6EC
PCA in te r r upt en a b le bit
Clear to disable . Set to enable.
5ET2
Timer 2 overflow interrupt Enable bit
Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4ES
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interr upt.
3ET1
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2 EX1 External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
1ET0
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0 EX0 External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
40 T89C51RD2 4243G–8051–05/03
Table 24. IP Register
IP - Interrupt Priority Register (B8h)
Reset Value = X000 0000b
Bit addressable
76543210
-PPC PT2 PS PT1 PX1 PT0 PX0
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6PPC
PCA interrupt pr iority bit
Refer to PPCH for priority level.
5PT2
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4PS
Serial port Priority bit
Refer to PSH for priority level.
3PT1
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2 PX1 External interrupt 1 Priority bit
Refer to PX1H for priority level.
1PT0
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0 PX0 External interrupt 0 Priority bit
Refer to PX0H for priority level.
41
T89C51RD2
4243G–8051–05/03
Table 25. IPH Regist er
IPH - Interrupt Priority High Register (B7h)
Reset Value = X000 0000b
Not bit address ab le
76543210
-PPCH PT2H PSH PT1H PX1H PT0H PX0H
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6PPCH
PCA interrupt priority bit high.
PPCH PPC Priority Level
0 0 Lowest
01
10
1 1 Highest
5PT2H
Timer 2 overflow interrupt Priority High bit
PT2H PT2 Priority Level
0 0 Lowest
01
10
1 1 Highest
4PSH
Serial port Priority High bit
PSH PS Priority Level
0 0 Lowest
01
10
1 1 Highest
3PT1H
Timer 1 overflow interrupt Priority High bit
PT1H PT1 Priority Level
0 0 Lowest
01
10
1 1 Highest
2 PX1H
External interrupt 1 Priority High bit
PX1H PX1 Priority Level
0 0 Lowest
01
10
1 1 Highest
1PT0H
Timer 0 overflow interrupt Priority High bit
PT0H PT0 Priority Level
0 0 Lowest
01
10
1 1 Highest
0 PX0H
External interrupt 0 Priority High bit
PX0H PX0 Priority Level
0 0 Lowest
01
10
1 1 Highest
42 T89C51RD2 4243G–8051–05/03
Power Management Two power reduction modes are implemented in the T89C51RD2: the Idle mode and the
Power-down mode. T hese modes a re detailed in the following sections. In addition to
these power reduction modes, the clocks of the core and peripherals can be dynamically
divided by 2 using the X2 mode detailed in Section “X2 Featu re ”.
Reset In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an
high level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the inte rnal regi sters lik e SFRs, Program Counter… and to unpre dictable beha vior of
the mic rocontrol ler. A prop er device res et initia lizes the T89C51RD2 an d vectors the
CPU to ad dress 0000h. RST inpu t has a pull -down r esisto r allowin g power -on rese t by
simply connecting an external capacitor to VDD as shown in Figure 17. A warm reset can
be applied either directly on the RST pin or indirectly by an internal reset source such as
the watchdog timer. Resistor value and input characteristics are discussed in the Sec-
tion “DC Characteristics” of the T89C51RD2 datasheet.
Figure 17. Reset Circuitry and Power-On Reset
Cold Reset 2 conditions are required before enabling a CPU start-up:
•VDD must reach the specified VDD range
•The level on X1 input pin must be outside the specification (VIH, VIL)
If one of thes e 2 cond itions ar e not me t, the mic rocontr oller does no t start cor rectl y and
can execute an ins truction fetch from anywhere in the program space. An activ e level
applied on the RST pin must be maintained till both of the above conditions are met. A
reset is active when the level VIH1 is reached and when the pulse width covers the
period of time wh ere VDD and the oscillator are not stabilized. 2 parameters have to be
taken into account to determine the reset pulse width:
•VDD rise time,
•Oscillator startup time.
To determine the capacitor value to implement, the highest value of these 2 parameters
has to be chos en. Tabl e 26 give s some capacitor value s exampl es for a mini mum R RST
of 50 KΩ and different oscillator startup and VDD rise times.
RRST
RST
VSS
To CPU Core
and Peripherals
RST
VDD
+
Power-on Re se tRST input circuitry
P
VDD From Internal
Reset Source
43
T89C51RD2
4243G–8051–05/03
Table 26. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1)
Note: These values assume VDD starts from 0V to the nominal value. If the time between 2
on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully
discharged, leading to a bad reset sequence.
Warm Reset To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the osc illator is running. The number of clock
periods is mode independent (X2 or X1).
Watchdog Reset As detailed in Section “Watchdog Timer”, the WDT gen erates a 96-clock period pulse
on the RST pin . In orde r to pr operl y p ropag ate th is pul se to the re st o f the a ppl ic ation i n
case of e xternal capac itor or power -supply s upervisor circ uit, a 1 kΩ resistor must be
added as shown Figu re 18.
Figure 18. Reset Circuitry for WDT Reset-out Usage
Oscillator
Start-Up Time
VDD Rise Time
1 ms 10 ms 100 ms
5 ms 820 nF 1.2 µF 12 µF
20 ms 2.7 µF 3.9 µF 12 µF
RRST
RST
VSS
To CPU Core
and Peripherals
VDD
+
P
VDD From WDT
Reset Source
VSS
VDD
RST
1K
To Other
On-board
Circuitry
44 T89C51RD2 4243G–8051–05/03
Reset Re commendation
to Prevent Flash
Corruption
Since the product includes a software area (booloader) where the C51 core can operate
Flash wr ite o perat ions, if th e value of the Pr ogram Co unter is acciden tly i n the range of
the boot memor y add ress es th en a Fl as h a cces s (w rite or e rase ) ma y co rrup t th e F las h
on-chip memory.
It is recommended to use an external reset circuitry featuring power supply monitoring to
prevent system malfunction during periods of insufficient power supply voltage (power
supply failure, power supply switched off).
Idle Mode An ins tructi on that sets P CON.0 indica tes that it is the las t inst ructio n to b e execute d
before going into Id le mode. In Idle mode, the inte rnal clock s ignal is gated of f to the
CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is pre-
served in its entirety: the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during idle. The port pins hold the
logica l states they had at the time Idl e was activ ated. ALE and PSEN hold at log ic high
level.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will
cause PCON.0 to be cleared by ha rdware, ter minat ing the Idl e mode. Th e interru pt will
be serviced, and following RETI the next instruction to be executed will be the one fol-
lowing the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred dur-
ing normal operation or during idle. For example, an instruction that activates idle can
also set one or both flag bits. When idle is terminated by an interrupt, the interrupt ser-
vice routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode To sav e maximum powe r, a Powe r-down mod e can be inv oked by so ftware (see Table
14, PCON register).
In Power-down mode, the oscillator is stopped and the instruction that invoked Power-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the Power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from Power-
down. To properly terminate Power-down, the reset or external interrupt should not be
executed befor e VCC i s restored to its normal operating level an d must be h eld activ e
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0, INT1 and Key board Interr upts are useful to exit f ro m
Power-down. For that, i nter rupt m ust be en abl ed an d co nfi gur ed as lev el or ed ge sens i-
tive interrupt input. When Keyboard Interrupt occurs after a power down mode, 1024
clocks are necessary to exit to power down mode and enter in operating mode.
Holding th e pi n low r es tarts the o scil la tor bu t br in gin g the pi n hi gh completes the e xit as
detailed in Figure 19. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and power down exit will be completed when the first
inpu t w ill be released . In this case , the higher prio rity interrup t s ervice routi ne is exe-
cuted. On ce the inter rupt is servi ced, the next instructio n to be execute d after RETI wil l
be the one following the instruction that puts the T89C51RD2 into Power-down mode.
45
T89C51RD2
4243G–8051–05/03
Figure 19. Pow er -d ow n Ex it Wa vef or m
Exit from Po wer-do wn by res et redef ines all the SF Rs, exi t from P ower-d own by e xter-
nal interrupt does no affect the SFRs.
Exit fr om Power-down by either res et or external interrupt do es not affec t the interna l
RAM content.
Note: If idle mode is activated with Power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Table 27 shows the state of ports during idle and power-down modes.
Port 0 can force a 0 level. A "one" will leave port floating.
INT1
INT0
XTALA
Power-down Phase Oscillator Restart Phase Active PhaseActive Phase
or
XTALB
Table 27. State of Ports
Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Port Data(1) Port Data Port Data Port Data
Idle External 1 1 Floating Port Data Address Port Data
Power Down Internal 0 0 Port Data(1) Port Data Port Data Port Data
Power Down External 0 0 Floating Port Data Port Data Port Data
46 T89C51RD2 4243G–8051–05/03
Hardware Watchdog
Timer The WDT is intended as a recovery method in situations where the CPU may be sub-
jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer
ReSeT (WDT RST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H . When WDT is enable d, it will incremen t every mac hine cyc le whil e the oscil lator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH
pulse at the RST-pin.
Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When W DT is enabled, it will
increment every machine cycle while the oscillator is running. This means the user must
reset the WDT at least every 16383 machine cycle. To reset the WDT the user must
write 01 EH and 0 E1H to WDTRST . WDTRS T is a wri te only r egi st er. T he W DT c oun ter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. T he RESET pulse dur ation is 96 x TOSC , where TOSC = 1/FOSC . To
make the best use of the WDT, it should be serviced in those sections of code that will
periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 coun ter has been add ed to extend the Tim e-out
capability, ranking from 16ms to 2s @ FOSC = 12MHz. To manage this feature, refer to
WDTPRG register description, Table 29. (SFR0A7h).
Table 28. WDTRST Register
WDTRST Address (0A6h)
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
Table 29. WDTPRG Register
WDTPRG Address (0A7h)
7 6 5 4 3 2 1
Reset value X X X X X X X
76543210
T4 T3 T2 T1 T0 S2 S1 S0
Bit
Number Bit
Mnemonic Description
7T4
Reserved
The value read from this bit is undeterminated. Do not try to set this bit..
6T3
5T2
4T1
3T0
2 S2 WDT Time-out select bit 2
1 S1 WDT Time-out select bit 1
47
T89C51RD2
4243G–8051–05/03
Reset value XXXX X000
WDT During Power Down and
Idle In Power Down mode the osci llator stops, which means the WDT also stops. W hile in
Power Down mode the user does not need to service the WDT. There are 2 methods of
exi tin g Po w er Dow n m ode : b y a h a rd war e r es et or vi a a le vel activat ed externa l in terrupt
which is ena ble d p rior t o e nter ing Power Dow n m ode . W hen P ower Down is e xi ted with
hardware reset, servicing the WDT should occur as it normally should whenever the
T89C51RD2 is r eset. Ex i ting P ower Do wn wi th an i nte rrupt i s signi fican tly d iffe rent. Th e
interrupt is held low long enough for the oscillator to stabiliz e. When the interrupt is
brough t high, the inter rupt is service d. To prevent th e WDT from reset ting the devic e
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is best to reset the WDT just before entering powerdown.
In the Idle mo de, the oscill ator con tin ues to r un. To pr even t the W DT from rese tting th e
T89C51RD2 while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.
If the WDT is a ctivated, the power consumption in stand-by mode will be above the
specified value.
0 S0 WDT Time-out select bit 0
S2 S1 S0Selected Time-out
000(2
14 - 1) machine cycles, 16.3 ms @ 12 MHz
001(2
15 - 1) machine cycles, 32.7 ms @ 12 MHz
010(2
16 - 1) machine cycles, 65.5 ms @ 12 MHz
011(2
17 - 1) machine cycles, 131 ms @ 12 MHz
100(2
18 - 1) machine cycles, 262 ms @ 12 MHz
101(2
19 - 1) machine cycles, 542 ms @ 12 MHz
110(2
20 - 1) machine cycles, 1.05 s @ 12 MHz
111(2
21 - 1) machine cycles, 2.09 s @ 12 MHz
Bit
Number Bit
Mnemonic Description
48 T89C51RD2 4243G–8051–05/03
ONCE(TM) Mode (ON Chip
Emulation) The ONCE mode facilitates testing and debugging of systems using T89C51RD2 with-
out removing the circuit from the board. The ONCE mode is invoked by driving certain
pins of the T89C51RD2; the following sequence must be exercised:
•Pull ALE low while the device is in reset (RST high) and PSEN is high.
•Hold ALE low as RST is deactivated.
While th e T89C51RD2 is in O NCE mo de, an emula tor or tes t CP U ca n be us ed to dr ive
the circuit. Table 30. shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 30. External Pin Status during ONCE Mode
(a) "Once" is a registered trademark of Intel Corporation.
ALE PSEN Port 0 Port 1 Port 2 Por t 3 XTAL1/2
Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up Active
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T89C51RD2
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Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with
external progr am o r data memo ry. Nev ertheless, during interna l code ex ecution, ALE
signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting
AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no
longer output but remains active during MOVX and MOV C instructions and external
fetches. During ALE disabling, ALE pin is weakly pulled high.
Table 31. AUXR Register
AUXR - Auxiliary Register (8Eh)
Reset Value = XX0X 100 0b
Not bit address ab le
76543210
- - M0 -XRS1 XRS0 EXTRAM AO
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5M0
M0 bit: Pulse length in clo c k period
Stretch MOVX control: the RD/ and the WR/ pulse length is increased
according to the value of M0. see table 6
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3XRS1
XRS1 bit
XRAM size: Ac cess ible size of the XRAM. See Table 6.
2XRS0
XRS0 bit
XRAM size: Ac cess ible size of the XRAM . Table 6.
1EXTRAM
EXTRAM bit
See Table 6.
0AO
ALE Output bit
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
50 T89C51RD2 4243G–8051–05/03
EEPROM Data Memory
General Description The EE PROM memory block conta ins 2048 b ytes and i s organized in 32 pages (or
rows) of 6 4 by te s. Th e n ece ss ary hi gh pr ogram mi ng v ol tag e i s g ene rated on- c hip us in g
the standard Vcc pin of the microcontroller.
The E EPROM memor y b lock is loc ated a t the addres ses 0000h to 0 7FFh of the XRA M
memory space and is selected by setting control bits in the EECON register.
A read in the EEPROM memory is done with a MOVX instruction.
A physic al write in t he EE PR OM memo r y is don e in two s tep s : wri te da ta in the co lum n
latches and transfer of all data latches in a EEPROM memory row (programming).
The num ber of data writte n in th e page may vary f rom 1 to 64 (the page s ize). When
progra mming , only th e data wri tten in th e column latch a re progra mmed. T his pro vides
the capa bilit y to pro gram the who le me mory by b ytes, by p age or by a n umb er of by tes
in a page.
W rite Dat a in the Colu mn
Latches Data is written by byte to the column latc hes as if it was in an external RAM m emory.
Out of the 16 address bits of the data pointer, the 10 MSB are used for page selection
and 6 are used for byte selection. Between two EEPROM programming, all addresses in
the column latches must remain in the same page, thus the 10MSB must be unchanged.
The following procedure is used to write in the colums latches :
•Map the program space (Set bit EEE of EECON register)
•Load DPTR with the address to write
•Load A register with the data to be written
•Execute a MOVX @DPTR, A
•If needed loop the three last instructions until the end of a 64bytes page
Programming The EEPROM programming consists on the following actions :
•write one or more bytes in a page in the column latches. Normally, all bytes must
belong to the same page; if this is not the case, the first page address is latched and
the others are discarded.
•Set EETIM with the value corresponding to the XTAL frequency.
•Launch the programming by writing the control sequence (52h or 50h followed by
A2h or A0h) to the EECON register (see Table 32).
•EEBUSY flag in EECON is then set by hardware to indicate that programming is in
progress and that EEPROM segment is not available for read.
•The end of programming is signaled by a hardware clear of the EEBUSY flag.
Example : ..... ; DPTR = EEPROM data pointer, A = Data to write
Wait : MOV A,EECON
ANL A,#01h
JNZ Wait
MOV EETIM,#3Ch ; 12MHz*5 = 3Ch
MOV EECON,#02h ; EEE=1 EEPROM mapped
MOVX @DPTR,A ; Write data to EEPROM
MOV EECON,#50h or 52h ; Write Sequence
MOV EECON,#A0h or A2h
....
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T89C51RD2
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Read Data The following procedure is used to read the data store in the EEPROM memory:
•Map the program space (Set bit EEE of EECON register)
•Load DPTR with the address to read
•Execute a MOVX A, @DPTR
Example : ... ; DPTR = EEPROM data pointer
MOV EECON,#02h ; EEE=1 EEPROM mapped
MOVX A,@DPTR ; Read data from EEPROM
... ; A = Data
Registers Table 32. EECON Register
EECON (S:0D2h)
EEPROM Control Register
Reset Val ue = XXXX XX00 b
76543210
EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY
Bit Number Bit
Mnemonic Description
7-4 EEPL3-0 Programming Launch command bits
Write 5Xh followed by AXh to EECON to launch the programming.
3 - Not implemented, reserved for future use. (1)
1. User sof tware sh ould no t write 1s to res erved b its . These bit s may be us ed in fu ture 805 1
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
2 - Not implemented, reserved for future use. (2)
2. User sof tware sh ould no t write 1s to res erved b its . These bit s may be us ed in fu ture 805 1
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
1EEE
Enable EEPROM Space bit
Set to map the EEPROM space during MOVX instructions (Write in the column
latches)
Clear to map the data space during MOVX.
0EEBUSY
Programming Busy flag
Set by hardware when programming is in progress.
Cleared by hardware when programming is done.
Can not be set or cleared by software.
52 T89C51RD2 4243G–8051–05/03
Table 33. EETIM Register
EETIM (S:0D3h)
EEPROM timing Control Register
Reset Value = 0000 0000b
76543210
EETIM
Bit Number Bit
Mnemonic Description
7-0 EETIM
Write Timer Register
The write timer register value is required to adapt the write time t o the oscillator
frequency
Value = 5 * Fxtal (MHz) in normal mode, 10 * Fxtal in X2 mode.
Example : Fxtal = 33 MHZ, EETIM = 0A5h
53
T89C51RD2
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Flash EEPROM Memory
General Description The Fl ash memo ry increa ses EP ROM and RO M functi onality wi th in-ci rcuit ele ctrical
erasure and programming. It contains 64K bytes of program memory organized in 512
pages of 128 bytes. This memory is both parallel and s erial In-System Programmable
(ISP). ISP allows devices to alter their own program memory in the actual end product
under software c ontrol. A d efault serial lo ader (bootloader) program allows ISP of the
Flash.
The programming does not r equire 12v exter nal progr amming voltage. The necessary
high programming voltage is generated on-chip using the standard VCC pins of the
microcontroller.
Features •Flash E2PROM inter nal program memory.
•The last 1K bytes of the Flash is used to store the low-level in-system programming
routines and a default serial loader. If the application does not need to use the ISP
and does not expect to modify the Flash content, the Boot Flash sector can be
erased to provide access to the full 64K byte Flash memory.
•Boot vector allows user provided Flash loader code to reside anywhere in the Flash
memory space. This configuration provides flexibility to the user.
•Default loader in Boot Flash allows programming via the serial port without the need
of a user provided loader.
•Up to 64K byte external program memory if the internal program memory is disabled
(EA = 0).
•Programming and erase voltage with standard 5V or 3V VCC supply.
•Read/Programming/Erase:
•Byte-wise read (without wait state).
•Byte or page erase and programming (10 ms).
•Typical programming time (63K bytes) in 20 s.
•Parallel programming with 87C51 compatible hardware interface to programmer.
•Programmable security for the code in the Flash.
•100k write cycles
•10 years data retention
Flash Programming and
Erasure T he 64K bytes Flash is prog ramme d by byte s or by page s of 128 by tes. It is not nece s-
sary to erase a byte or a page before programming. The programming of a byte or a
page includes a self erase before programming.
There are three methods to program the F l ash memory:
•First, the on-chip ISP bootloader may be invoked which will use low level routines to
program the pages. The interface used for serial downloading of Flash is the UART.
•Second, the Flash may be programmed or erased in the end-user application by
calling low-level routines through a common entry point in the Boot loader.
•Third, the Flash may be programmed using the parallel method by using a
conventional EPROM programmer. The parallel programming method used by
54 T89C51RD2 4243G–8051–05/03
these devices is similar to that used by EPROM 87C51 but it is not identical and the
commercially available programmers need to have support for the T89C51RD2.
The bootloader and the In Application Programming (IAP) routines are located in the last
kilobyte of the Flash, leaving 63k bytes available for the application with ISP.
Flash Registers and
Memory Map The T89C51RD2 Flash memory uses several registers for his management:
•Flash control register is used to select the Flash memory spaces and launch the
Flash programming sequence.
•Hardware registers can only be accessed through the parallel programming modes
which ar e handl ed by the parallel prog ramme r.
•Software registers are in a special page of the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called "Extra Flash Memory", is not in the internal Flash program memory
addressing space.
Flash Reg ister F igu re 20. FCON register
FCON (S:D1h) Flash control register
Reset Value = xxxx 0000b
The Flash programming application note and API source code are available on request.
Hardwa re reg is te r The only hardwar e regis ter of t he T89C 51RD2 is called Hardwa re Secur ity By te (HS B).
After full Flash erasure, the content of this byte is FFh; each bit is active at low level.
76543210
FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY
Bit
Number Bit
Mnemonic Description
7-4 FPL3:0 Programming Launch command bits
Write 5h followed by Ah to launch the programming.
3FPS
Flash Map Program Space
Clear to map the data space during MOVX
Set to map the Flash space during MOVX (write) or MOVC (read) instructions
(Write in the column latches)
2-1 FMOD1:0
Flash Mode
Select the addressed space
00: User (0000h-FFFFh)
01: XAF
10: Hardware byte
11: reserved
0FBUSY
Flash Busy
Set by hardware when programming is in progress.
Clear by hardware when programming is done.
Can not be cleared by software
55
T89C51RD2
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Boot Loader Lock Bit (BLLB) One bit of the HSB is used to secure by hardware the internal boot loader sector against
software reprogramming.
When the BLLB is cleared, any attempt to write in the boot loader segment (Address
FC00h to FFFFh) will have no effect. This protection applies for software writing only.
Boot Loader Jump Bit (BLJB)
One bit of the HSB, the BLJB bit, is used to force the boot address:
•When this bit is set the boot address is 0000h.
•When this bit is reset the boot address is FC03h. By default, this bit is cleared and
the ISP is enabled.
Flash memory lock bits The three lock bits provide different levels of protection for the on-chip code and data,
when programmed according to Table 29.
76543210
SB BLJB BLLB - - LB2 LB1 LB0
Bit
Number Bit
Mnemonic Description
7SB
Safe Bit
This bit must be cleared t o secure the content of the HSB. Only security level can
be increased.
6BLJB
Boot loader Jump Bit
Set to force hardware boot address at 0000h. (unless previously force by hardware
conditions as described in the chapter 9.6).
Clear to force hardware boot address at FC03h (default).
5 BLLB
Boot loader Lock Bit
Set to allow programming and writing of the boot loader segment.
Clear to forbid software progr amm ing and writing of the boot loader segment
(default). This protection protect only ISP or IAP access; protection through parallel
access is done globally by the lock bits LB2-0.
4-
Reserved
Do not clear this bit.
3-
Reserved
Do not clear this bit.
2-0 LB2-0 User Memory Lock Bits
See Table 29
56 T89C51RD2 4243G–8051–05/03
Table 34. Program Lock bits
Note: U: unprogrammed or "one" level.
Note: P: programmed or "zero" level.
Note: X:do not care
Note: WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
These se curity bits protect the co de access through the parallel pr ogrammi ng interf ace.
They are se t by defau lt to lev el 4. The cod e acce ss throug h the ISP i s stil l possib le and
is cont rolle d by the "s oftware s ecurit y bits" which are store d in the ext ra Flash memory
accessed by the ISP firmware.
To load a new application with the parallel programmer, a chip erase must first be done.
This will s et the HSB in it s inact ive sta te and will erase the F las h memory, incl uding the
boot load er an d t he " E xtra F lash Memory" ( X AF) . I f ne eded, the 1K boot load er an d th e
XAF content must be programmed in the Flash; the code is provided by ATMEL Wire-
less and Microc ontrollers (see section 8.7. ); the part reference can alway s be read
using Flash parallel programming modes.
Default Values The default value of the HSB provides parts ready to be programmed with ISP:
•SB: Cleared to secure the content of the HSB.
•BLJB: Cleared to force ISP operation.
•BLLB: Clear to protect the default boot loader.
•LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Software Registers Several registers are used, i n factory and by parallel programmers, to make copies of
hardwar e regis ter s contents. These values are us ed by ATME L Wirel es s and M icr ocon-
trollers ISP (see section 8.7. ).
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:
•Commands issued by the parallel memory programmer.
•Commands issued by the ISP software.
Calls of API issued by the application software.
They are several software registers described in Table 35
Program Lock Bits Protection Description
Security
level LB0 LB1 LB2
1UUU
No program lock features enabled. MOVC instruction executed from
external program memory returns non encrypted data.
2PUU
MOVC instruction executed from external program memory are disabled
from fetching code bytes from internal memory, EA is sampled and
latched on reset, and further parallel programming of the Flash is
disabled.ISP and software programming with API are still allowed.
3XPU
Same as 2, also verify through parallel programming interface is
disabled.
4 X X P Same as 3, also external execution is disabled.
57
T89C51RD2
4243G–8051–05/03
Table 35. Default Value s
After pr ogramming the part by ISP , the BSB must be reset (00h) in order to allow the
application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 30 and Table 31
To assu re co de protec tion from a pa ra ll el ac ce ss, the H SB must al so be at t he r e qui re d
level.
The three lock bits provide different levels of protection for the on-chip code and data,
when programmed according to Table 31.
Table 36. Program Lock bits of the SSB
Note: U: unprogrammed or "one" level.
Note: P: programmed or "zero" level.
Note: X:do not care
Note: WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
Mnemonic Default Value
BSB Boot Status Byte FFh
SBV Software Boot Vec tor FCh
HSB Copy of the Hardware security byte 18h or 1Bh
SSB Software Security Byte FFh
Copy of the Manufacturer Code 58h ATMEL Wireless and
Microcontrollers
Copy of the Device ID #1: Family Code D7h C51 X2, Electrically Erasable
Copy of the Device ID #2: memories size
and type FCh T89C51RD2 memories
size
Copy of the Device ID # 3: name and
revision FFh T89C51RD2, revision 0
Program Lock Bits Protection Description
Security
level LB0 LB1
1 U U N o program lock features enabled.
2PU
following commands are disabled:
- program byte
- program status byte and boot vector
- erase status byte and boot vector
3XP
Same as 2 and following commands also disabled:
- read byte
- read status byte and boot vector
- blank check
- program SSB level2
58 T89C51RD2 4243G–8051–05/03
Flash Memory Status T89C51RD2 parts are delivered in standard with the ISP boot in the Flash memory.
After IS P or paralle l pro gramm ing, th e poss ible conte nts of the Flas h mem ory are sum-
marized on the figure below:
Figure 21. Flash Memory Possible Contents
0000h
Boot
Virgin
FC00h
Default
Boot Boot
Virgin
Boot
Virgin
After ISP After parallel
programming After parallel
programming After parallel
programming
ApplicationApplication
Boot
Virgin
After ISP
or appli or appli or appli
Dedicated
ISP Dedicated
ISP
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Bootloader Architecture
Introduction
The bootloader manages a communication acc ording to a speci fic defined protocol to
provid e the whol e ac ce ss and se rvic e on F lash me mor y . Fur the rm or e, all ac c es se s and
routines can be called from the user application.
Figure 22. Diagram Context Description
Acronyms ISP: In-system Programming
SBV: Software Boot Vector
BSB: Boot Status Byte
SSB: Software Security Bit
Bootloader Flash Memory
Access via
Specific
Protocol
Access From
User
Application
60 T89C51RD2 4243G–8051–05/03
Functional Description
Figure 23. Boo tlo ade r Func tio nal Descripti on
On the above diagram, the on-chip bootloader processes are:
•ISP Communication Management
The purpose of this process is to manage the communication and its protocol between
the on-chip bootl oad er and a external dev ice. The on- chip RO M i mplem ent a s eria l pro-
tocol (see section Bootloader Protocol). This process translate serial communication
frame (UART) into Flash memory acess (read, write, erase ...).
•User Call Management
Several Application Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
through a co mmon in terface (A PI calls) , included in the ROM boo tloade r. The progr am-
ming functions are selected by setting up the microcontroller’s registers before making a
call to a common entry point (0xFFF0). Results are returned in the registers. The pur-
pose on this process is to translate the registers values into internal Flash Memory
Management.
•Flash Memory Management
This process manages low level access to Flash memory (performs read and write
access).
ISP Communication
Management
User
Application
Specific Protocol
Communication
Management
Flash
Memory
Exernal Host with
Flash Memory
User Call
Management (API )
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Bootloader Func tionality
Introduction The bootloader can be activated by two means: Hardware conditions or regular boot
process.
The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the
on-chip bootloader execution. This allows an application to be built that will normally
execute the end user’s code but can be manually forced into default ISP operation.
As PSE N is an outpu t port in nor mal opera ting mode ( runnin g user appl icatio n or boor-
loader code) after reset, it is recommended to release PSEN after falling edge of reset
signal . The hardware c ondition s are sampl ed at reset sig nal falling ed ge, thus they ca n
be released at any time when reset input is low.
The on-chip bootloader boot process is shown in Figure 24.
Purpose
Hardware Conditions The Hardware Conditions force the bootloader execution whatever BLJB, BSB
and SBV values.
BLJB
The Boot Loader Jump Bit forces the application execution.
BLJB = 0 => Boot loader execution.
BLJB = 1 => Application execution.
The BLJB is a fuse bit in the Hardware Byte.
That can be modified by hardware (programmer) or by software (API).
Note:
The BLJB test is perform by hardware to prevent any program execution.
SBV
The Software Boot Vector contains the high address of custumer bootloader
stored in the application.
SBV = FCh (default value) if no custumer bootloader in user Flas h.
Note:
The custumer bootloader is called by LJMP [SBV]00h instruction.
62 T89C51RD2 4243G–8051–05/03
Boot Process
Figure 24. Boo tlo ade r Pr oces s
RESET
Hardware
Condition?
BLJB = 1
?
Hardware
Software
BSB = 00h
?
SBV = FCh
?
Yes (PSEN = 0, EA = 1,
JUMP to FC00h
User Boot LoaderUser Application Default Boot Loader
JUMP to FC 03h
JUMP to XX00hJUMP to 0000h
and ALE = 1 or not connected)
Yes
BSB=0
SBV=FCh
SBV=XXh
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ISP Protocol Description
Physical Layer The UART used to transmit information has the following configuration:
•Character: 8-bit data
•Parity: none
•Stop: 1 bit
•Flow control: none
•Baud rate: autobaud is performed by the bootloader to compute the baud rate
choos en by the host.
Frame Description The Serial Protocol is based on the Intel Hex-type records.
Intel Hex records consist of ASCII characters used to represent hexadecimal values and
are summarized below.
Table 37. Intel Hex Type Frame
•Record Mark:
–Record Mark is the start of frame. This field must contain ’:’.
•Reclen:
–Reclen specifies the number of Bytes of information or data which follows
the Record Type field of the record.
•Load Offset:
–Load Offset specifies the 16-bit starting load offset of the data Bytes,
therefore this field is used only for
–Data Program Record (see Section “ISP Commands Summary”).
•Record Type:
–Record Type specifies the command type. This field is used to interpret the
remaining information within the frame. The encoding for all the current
record types i s described in Section “ISP Commands Summary”.
•Data/Info:
–Data/Info is a variable length field. It consists of zero or more Bytes encoded
as pairs of hexadecimal digits. The meaning of data depends on the Record
Type.
•Checksum:
–The two’s complement of the 8-bit Bytes that result from converting each pair
of ASCII hexadecimal digits to one Byte of binary, and including the Reclen
field to and including the last Byte of the Data/Info field. Therefore, the sum
of all the ASCII pairs in a record after converting to binary, from the Reclen
field to and including the Checksum field, is zero.
Record Mark ‘:’Reclen Load Offset Record Type Data or Info Checksum
1 byte 1 byte 2 bytes 1 bytes n byte 1 byte
64 T89C51RD2 4243G–8051–05/03
Functional Description
Configuration and
Manufacturer Information The table below lists Configuration and Manufacturer byte information used by the boot-
loader. This information can be accessed through a set of API or ISP commands.
Software Security Bits (SSB) The SSB protects any Flash access from ISP command.
The command "Program Software Security bit" can only write a higher priority level.
There are three levels of security:
•level 0 : NO_SECURITY (FFh)
This is the default level.
From level 0, one can write level 1 or level 2.
•level 1 : WRITE_SECURITY (10h )
For this level it is impossible to write in the Flash memory, BSB and SBV.
The Bootlo ade r re turns ’P’ on write access.
From level 1, one can write only level 2.
•level 2 : RD_WR_SECURITY (00h
The level 2 forbids all read and write accesses to/from the Flash/EEPROM memory.
The Bootlo ade r re turns ’L’ on read or write access.
Only a full chip erase in parallel mode (using a programmer) or ISP command can reset
the software security bits.
From level 2, one cannot read and write anything.
Table 38. Software Security Byte Behavior
Mnemonic Description Default Value
BSB Boot Status Byte FFh
SBV Software Boot Vect or FCh
SSB Software Security Byte FFh
Manufacturer Id 58h
Id1 : Fa mily co d e D7h
Id2: Product Name FCh
Id3: Product Revision FFh
Level 0 Level 1 Level 2
Flash/EEPRO M Any access allowed Read only acces s allowed Any access not allowed
Fuse Bit Any access allowed Read only access allowed Any access not allowed
BSB & SBV Any access allowed Read only access allowed Any access not allowed
SSB Any access allowed Write level 2 allowed Read only access allowed
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Manufacturer
Info Read only access allowed Read only access allowed Read only access allowed
Bootloader Info Read only access allowed Read only access allowed Read only access allowed
Erase Block Allowed Not allowed Not allowed
Full-chip Erase Allowed Allowed Allowed
Blank Check Allowed Allowed Allowed
Level 0 Level 1 Level 2
66 T89C51RD2 4243G–8051–05/03
Full Chip Erase The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and
sets some Bytes used by the bootloader at their default values:
•BSB = FFh
•SBV = FCh
•SSB = FFh and finally erase the Software Security Bits
The Full Chip Erase does not affect the bootloader.
Checksum Error When a checksum error is detected send ‘X’ followed with CR&LF.
Flow Description
Overview An initial ization st ep must b e perfor med after e ach Rese t. After microcontrol ler rese t,
the bootloader waits for an autobaud sequence ( see section ‘autobaud per for m ance’).
When the communication is initialized the protocol depends on the record type
requested by the host.
FLIP, a software utility to implement ISP programming with a PC, is available from the
Atmel the web site.
Communication Initialization The host initiali ze s the comm uni ca tio n by se ndi ng a ’U’ character to help the bootloader
to compute the baudrate (autobaud).
Figure 25. Initialization
Host Bootloader
"U" Performs Autobaud
Init Communication
If (not received "U") "U"
Communication Opened
Else Sends Back ‘U’ Character
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Autobaud Performances The ISP feature al lows a wide range of b aud rates in the user application. It is also
adapta ble to a wide rang e of o scilla tor freq uenci es. Thi s is accom plis hed by measur ing
the bit-time of a single bit in a received character. This information is then used to pro-
gram the ba ud rate in term s of timer coun ts based on the oscillat or frequenc y. The ISP
feature r equ ires that an ini tia l ch ar ac ter (a n upp ercase U) be sent to the T89 C 51RD 2 to
establish the baud rate. Table 39 shows the autobaud capability.
Table 39. Autobaud Performances (Bootloader Revision 2.4)
Frequency (MHz)
Baudrate (bit/s) 1. 8432 2 2.4576 3 3.6864 4 5 6 7.3728 8
4800 OK OK OK OK OK OK OK OK OK -
9600 OK OK OK OK OK OK - OK OK OK
19200 OK OK OK OK OK OK OK OK OK OK
38400 - OK - - OK OK OK OK OK OK
57600 - - - - OK - - - OK -
115200 - -------OK-
Frequency (MHz)
Baudrate (bit/s) 10 11.0592 12 14.318 14.746 16 20 24 26.6 32
4800 OK OK OK OK OK - - - - -
9600 OK OK OK OK OK OK OK OK OK -
19200 - OK OK OK OK OK OK OK OK OK
38400 OK OK OK OK OK OK OK OK
57600 - OK - OK OK OK OK OK OK
115200 - OK - OK - - - - OK
68 T89C51RD2 4243G–8051–05/03
Command Data Stream Protocol
All comma nds are sent using the same flow. E ach frame se nt by the hos t is echoed by
the bootloader.
Figure 26. Command Flow
Wr ite/Program Commands This flow is common to the following frames:
•Flash/EEPROM Programming Data Frame
•EOF or Atmel Frame (only Programming Atmel Frame)
•Config Byte Programming Data Frame
•Baud Rate Frame
Bootloader
":"
Sends first character of the
Frame If (not received ":")
Sends frame (made of 2 ASCII Gets frame, and sends back ec
for each received Byte
Host
Else
":" Sends echo and start
reception
charac ters per Byte )
Echo analy sis
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Description
Figure 27. Write/Pro gr am Flow
Example
Host Bootloader
Write Command
’X’ & twice (CR & LF)
NO_SECURITY
Wait Write Co m mand
Checksum error
Wait Programming
Send Security error
Send COMMAND_OK
Send Write Command
Wait Checksum Error
Wait COMMAND_OK
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum error
COMMAND ABORTED
’P’ & CR & LF
OR
’.’ & CR & LF
HOST : 01 0010 00 55 9A
BOOTLOADER : 01 0010 00 55 9A . CR LF
Programming Data (write 55h at address 0010h in the Flash)
HOST : 02 0000 03 05 01 F5
BOOTLOADER : 02 0000 03 05 01 F5. CR LF
Programming Atmel function (write SSB to level 2)
HOST : 03 0000 03 06 00 55 9F
BOOTLOADER : 03 0000 03 06 00 55 9F . CR LF
Writing Frame (write BSB to 55h)
70 T89C51RD2 4243G–8051–05/03
Blank Check Command
Description
Figure 28. Blank Check Flow
Example
Host Bootloader
Blank Check Command
’X’ & twice (CR & LF)
Flash blank
Wait Blank Check Command
Send first Address
Send COMMAND_OK
Send Blank Check Command
Wait Checksum Error
Wait Address not
erased
Wait COMMAND_OK
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum error
COMMAND FINISHED
’.’ & CR & LF
OR
address & CR & LF not erased
Checksum error
HOST : 05 0000 04 0000 7FFF 01 78
BOOTLOADER : 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ok
BOOTLOADER : 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
Blank Check with checksum error
HOST : 05 0000 04 0000 7FFF 01 70
BOOTLOADER : 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check ko at address xxxx
HOST : 05 0000 04 0000 7FFF 01 78
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Display Data
Description
Figure 29. Display Fl ow
Note: The maximum size of block is 400h. To read more than 400h Bytes, the Host must send a new command.
Host Bootloader
Display Command
RD_WR_SECURITY
Wait Display Command
Read Data
Send Security Error
Send Dis play Data
Send Display Command
Wait Checksum Error
Wait Display Data
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum Error
COMMAND ABORTED
’L’ & CR & LF
OR
"Address = "
All data read
Complete Frame
"Reading value"
CR & LF
All data readAll data read
COMMAND FINISHED
Checksum error
’X’ & twice (CR & LF)
72 T89C51RD2 4243G–8051–05/03
Example
Read Function
This flow is similar for the following frames:
•Rea ding Frame
•EOF Frame/Atmel Frame (only reading Atmel Frame)
Description
Figure 30. Read Flow
Example
HOST : 05 0000 04 0000 0020 00 D7
BOOTLOADER : 05 0000 04 0000 0020 00 D7
BOOTLOADER 0000=-----data------ CR LF (16 data)
BOOTLOADER 0010=-----data------ CR LF (16 data)
BOOTLOADER 0020=data CR LF ( 1 data)
Display data from address 0000h to 0020h
Host Bootloader
Read Command
RD_WR_SECURITY
Wait Read Command
Read Value
Send Security error
Send Data Read
Send Read Command
Wait Checksum Error
Wai t Va lue of D a t a
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum error
COMMAND ABORTED
’L’ & CR & LF
OR
’value’ & ’.’ & CR & LF
Checksum error
’X’ & twice (CR & LF)
HOST : 02 0000 05 07 02 F0
BOOTLOADER : 02 0000 05 07 02 F0 Value . CR LF
HOST : 02 0000 01 02 00 FB
BOOTLOADER : 02 0000 01 02 00 FB Value . CR LF
Read function (read SBV)
Atmel Read function (read Bootloader version)
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ISP Commands Summary Table 40. ISP Commands Summary
API Call Description Several Application Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
through a common interfac e, PGM_MTP. The programming fun ctions are selected by
setting up the microcontroller’s registers before making a call to PGM_MTP at FF F0h.
Results are returned in the registers.
When several Bytes have to be programmed, it is highly recommended to use the Atmel
API “PROGRAM DATA PAGE” call. Indeed, this API call writes up to 128 Bytes in a sin-
gle command.
All routines for software access are provided in the C Flash driver available at Atmel’s
web site.
Command Command Name Data[0] Data[1] Command Effect
00h Program Data
Program Nb Data Byte.
Bootloader will accept up to 16 (10h)
data Bytes. The data Bytes should be
128 Byte page Flash boundary.
03h Write Function
04h 00h Erase SBV
05h 00h Program SSB l evel 1
01h Program SSB l evel 2
06h 00h Program BS B (value to write in
data[2])
01h Program SB V (value to write in
data[2])
07h - Full Chip Erase
04h Display Function
Data[0:1] = start address
Data [2:3] = end address
Data[4] = 00h -> Display data
Data[4] = 01h -> Blank check
Display Data
Blank Check
05h Read Function
00h
00h Manufacturer ID
01h Device ID #1
02h Device ID #2
03h Device ID #3
07h
00h Read SSB
01h Read BSB
02h Read SBV
03h Read Hardware Byte Copy
08h 00h Read Bootloader Version
0Eh 00h Read Device Boot ID1
01h Read Device Boot ID2
74 T89C51RD2 4243G–8051–05/03
The API calls descri ption and ar gum ents are shown in Tabl e 41.
Table 41. API Call Summary
Command R1 A DPTR0 DPTR1 Returned Value Command Effect
READ MANUF ID 00h XXh 0000h XXh ACC=Manufacturer
ID Read Manufacturer identifier
READ DEVICE ID1 00h XXh 0001h XXh ACC= Device ID 1 Read Device identifier 1
READ DEVICE ID2 00h XXh 0002h XXh ACC=Device ID 2 Read Device identifier 2
READ DEVICE ID3 00h XXh 0003h XXh ACC=Device ID 3 Read Device identifier 3
PROGRAM DATA
BYTE 02h Byte value to
program
Address of
Byte to
program
ACC = 0 : DONE Program one Data Byte in user Flash
ERAS E BO O T
VECTOR 04h XXh XXh XXh ACC=FCh Erase Software boot vector and boot status
Byte. (SBV=FCh and BSB=FFh)
PROGR A M SSB 05h XXh
DPH = 00h
DPL = 00h
00h ACC= SSB value
Set SS B level 1
DPH = 00h
DPL = 01h Set SS B level 2
DPH = 00h
DPL = 10h Set SS B level 0
DPH = 00h
DPL = 11h Set SSB level 1
PROGR A M BSB 06h New BSB
value 0000h XXh none Program boot status Byte
PROGR A M SBV 06h New SBV
value 0001h XXh none Program software boot vector
READ SSB 07h XXh 0000h XXh ACC=SSB Read Software Security Byte
READ HSB 07h XXh 0004h XXh ACC=HSB Read Hardware Byte
READ BSB 07h XXh 0001h XXh ACC=BSB Read Boot St atus Byte
READ SBV 07h XXh 0002h XXh ACC=SBV Read Software Boot Vector
PROGRAM DATA
PAGE 09h Number of
Byte to
program
Address of
the fir st By te
to program in
the Flash
memory
Address in
XRAM of the
first data to
program
ACC = 0 : DONE
Program up to 128 Bytes in user Flash.
Remark: number of Bytes to program is
limited such as the Flash write remains in a
single 128 Bytes page. Hence, when ACC is
128, valid values of DPL are 00h, or 80h.
READ BOOT ID1 0Eh XXh DPL = 00h XXh ACC=ID 1 Read boot ID1
READ BOOT ID2 0Eh XXh DPL = 01h XXh ACC=ID 2 Read boot ID2
READ BOOT VERSION 0Fh XXh XXXXh XXh ACC=Boot_Version Read bootloader version
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Flash Parallel
Programming
Signature Bytes Four hardware read only registers have to be accessed with parallel static test modes
(mode TMS) in order to control the Flash parallel programmimg:
•Manufacturer code
•Device ID # 1: Family code
•Device ID # 2: Memories size and type
•Device ID # 3: Name and revision
As these registers can only be accessed by hardware, they must be read by the parallel
programm ers and then c opied in the X AF in order t o make their values accessibl e by
software (ISP or API).
Set-up modes Configuration In order to pro gram an d ve ri fy the F lash or to read th e si gna tur e by tes, the T 89 C51R D2
is placed in specific set-up modes. (See Figure 31.)
Figure 31. Set-Up Modes Configuration
Definition of Terms Address Lines:P1.0-P1.7, P2.0-P2.5, P3.4-P3.5, respectively for A0-A15.
Dat a Lines: P0.0-P0.7 for D0-D7
Control Signals:RST, PSEN, P2.6, P2.7, P3.2, P3.3, P3.6, P3.7.
Program Signals: ALE/PROG, EA
+5V
VCC
P0.0-P0.7
P1.0-P1.7
P2.0-P2.5
VSS
GND
D0-D7
A0-A7
A8-A13
RST
EA
ALE/PROG
PSEN
P2.6
P2.7
P3.3
P3.7
P3.6
XTAL1
4 to 6 MHz
CONTROL
SIGNALS*
PROGRAM
SIGNALS*
P3.4 A14
P3.5 A15
76 T89C51RD2 4243G–8051–05/03
Set-up modes configuration Contr ol and pro gram signal s must be hel d at the leve ls indic ated in the tw o followin g
tables.
Mode
Name Mode Rst Psen
Ale
_ _
|_| EA P2.6 P2.7 P3.6 P3.7 P0[7..0]
PELCK Program or Erase Lock.
Disable the Erasure or Programming access 10 _ _
|_| 11010 xx
PEULCK Program or Erase UnLock.
Enable the Erasure or Programming access 1 0 Note 2 1101055-AA
PGMC Write Code Data (byte)
or write Page
Always precedeed by PGML 10
_ _
|_|
Internally
timed
10111 xx
PGML Memory Page Load
(up to 128 bytes) 1 0 Note 1 10101 Din
PGMV Read Code Data (byte) 1 0 1 1 0 _ _
|_| 1 1 Dout
VSB Read Security Byte (=HSB) 1 0 1 1 0 _ _
|_| 0 1 Dout
PGMS Write Security Byte (Note 3)
(security byte = HSB) 1 0 10 ms 11100 Din
CERR C hip Erase U ser + XAF 1 0 100 ms 1 1 0 0 0 xx
PGXC Wr ite Byte or Page in Extra Memory (XAF)
Always precedeed by PGXL 10
_ _
|_|
Internally
timed
11101 xx
PGXL Memo ry Page Load XAF
(up to 128 bytes) 1 0 Note 1 11101 Din
TMS
Read Signature bytes
30h (Manufacturer code)
31h (Device ID #1)
60h (Device ID #2)
61h (Device ID #3)
10 1 10
_ _
|_| 0 0
Dout =
58h
D7h
FCh
FFh
RXAF Read Extra Memory (XAF) 1 0 1 1 0 _ _
|_| 0 0 Dout
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1. In Page Load Mode the current byte is loaded on ALE rising edge.
2. After a power up all external test mode to program or to erase the Flash are locked to avoid any untimely programming or
erasure.
After each programming or erasure test mode, it’s advised to lock this feature (test mode PELCK).
To validate the test mode mode PEULCK the foll owin g sequence has to be applied:Test Mode PEULCK with ALE = 1.
Pulse on ALE (min width=25clk) with P0=55 (P0 latched on ALE rising edge)
Pulse on ALE (min width=25clk) with P0=AA (P0 latched on ALE rising edge)
3. The highest security bit (bit 7) is used to secure the 7 lowest bit erasure. The only way to erase this bit is to erase the whole
Flash m emory.
Procedure to program security bits (After array programming):
- program bit7 to 0, program all other bits ( 1 = erased, 0 = programmed).
- test mode PGMS (din = HSB).
Procedure to erase security byte:
- test mode CERR: erase all array included HSB.
- program hardware security byte to FF: test mode PGMS (din = FF).
Mode
Name Mode P1[7..0] P2[5..0] P3.0 P3.1 P3.2 P3.3 P3.4 P3.5
PELCK Program or Erase Lock.
Disable the Erasure or Programm ing access xx xx xxx1xx
PEULCK Program or Erase UnLock.
Enable the Erasure or Programming access xx xx xxx0xx
PGMC Write Code Data (byte)
or write Page
Always precedeed by PGML A7-A0 A13-A8 1 x x 0 A14 A15
PGML Memory Page Load
(up to 128 bytes) A7-A0 A13-A8 1 x x 0 A14 A15
PGMV Read Code Data (byte) A7-A0 A13-A 8 1 x x 1 A 1 4 A15
VSB Read Security Byte (=HSB) xx xx 1 x x 1 x x
PGMS Write lock Byte (Note 4)
(security byte = HSB) xx xx 1 x x 0 x x
CERR Chip Erase User + XAF xx xx 1 x x 0 x x
PGXC Write Byte or Page Extra Memory (X AF )
Always precedeed by PGXL A7-A0
(0-7F) xx 1 x x 0 x x
PGXL Memory Page Load XAF
(up to 128 bytes) A7-A0
(0-7F) xx 1 x x 1 x x
TMS
Read Signature bytes
30h (Manufacturer code)
31h (Device ID #1)
60h (Device ID #2)
61h (Device ID #3)
30h
31h
60h
61h
x xxx1xx
RXAF Read Extra Memory
(XAF) Addr
(0-7F) 00 1 x x 0 x x
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Programming Algorithm To program the T89C51RD2 the following sequence must be exercised:
•Check the signature bytes
•Check the HSB (VSB mode)
If the security bits are activated, the following commands must be done before
programming:
•Unlock test modes (PEULCK mode, pulse 55h and AAh)
•Chip erase (CERR mode)
•Write FFh in the HSB (PGMS mode)
•Write the signature bytes content in the XAF
•As the boot loader and the XAF content is lost after a "chip erase", it must be
reprogrammed if needed.
•Disable programming access (PELCK mode)
To write a page in the Flash memory, execute the following steps:
•Step 0: Enable programming access (PEULCK mode)
•Step 1: Activate the combination of control signals (PGML mode)
•Step 2: Input the valid address on the address lines (High order bits of the address
must be stable during the complete ALE low time)
•Step 3: Activate the combination of control signals (PGML mode)
•Step 4: Input the appropriate data on the data lines.
•Step 5: Pulse ALE/PROG once.
Repeat step 2 through 5 changing the address and data for end of a 128 bytes page
•Step 6: Enable programming access (PEULCK mode)
•Step 7: Activate the combination of control signals (PGMC mode)
•Step 8: Input the valid address on the address lines.
•Step 9: Pulse ALE/PROG once the specified write time is reached.
Repeat step 0 through 9 changing the address and data until the entire array or until the
end of the object file is reached (See Figure 32.)
•Step 10: Disable programming access (PELCK mode)
Verify Algorithm Verify must be done after each byte or block of bytes is programmed. In either case, a
complete verify of the programmed array will ensure reliable programming of the
T89C51RD2.
P 2.7 is used to enable data output.
To verify the T89C51RD2 code the following sequence must be exercised:
•Step 1:Activate the combination of program and control signals (PGMV)
•Step 2: Input the valid address on the address lines.
•Step 3: Read data on the data lines.
Repeat step 2 through 3 changing the address for the entire array verification
(See Figure 32.).
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Figure 32. Programming and Verification Signal’s Waveform
Extra Memory Mapping The memory mappi ng the T89C51 RD2 software re gisters in the Extra Fla sh memory is
described in the table below.
All other addre ss es are reserv ed
Control sign al s
Data In
ALE/PROG
A0-A15
Progr amming Cycle
D0-D7
EA
Data Out
Read/Verify Cycle
5V
0V
P2.7
48 clk (load latch ) or 10 ms (write) or 100 ms (erase)
Table 42. Extra Row Memory Mapping (XAF)
Address Default content
Copy of device ID #3 0061h FFh
Copy of device ID #2 0060h FCh
Copy of device ID #1 0031h D 7h
Copy of Manufacturer Code:
ATMEL 0030h 58h
Software Security Byte (level 1 by
default) 0005h FFh
Copy of HSB (level 4 by default
and BLJB = 0) 0004h 18h or 1Bh
Software Boot Vec tor 0001h FCh
Boot Status Byte 0000h FFh
80 T89C51RD2 4243G–8051–05/03
Electrical Characteristics
Absolute Maximum
Ratings
DC Parameters for
Standard Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
Ambiant Temperature Under Bias:
C = commercial ..........................................0°C to 70°C
I = industrial .............................................-40°C to 85°C
Storage Temperature ..........................-65°C to +150°C
Voltage on VCC VSS ................................-0.5 V to +6.5V
Voltage on Any Pin VSS...................-0.5 V to VCC+0.5 V
Power Dissipation .................................................1 W(2)
*NOTICE: Stresses at or above those listed under “ Abso-
lute Ma xi mu m Ra tings” may cause permanent
damage to the device . This is a stres s rating onl y
and functi onal operati on of the devic e at these or
any other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Power dissipation value is based on the maxi-
mum allowable die temperature and the thermal
resistance of the package.
Table 43. DC Parameters in Standard Voltage (1)
Symbol Parameter Min Typ (5) Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V
VIH Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High Voltage, XTAL1, RST 0.7 VCC VCC + 0.5 V
VOL Output Low V oltage, ports 1, 2, 3, 4 and 5 (6) 0.3
0.45
1.0
V
V
V
IOL = 100 µA(4)
IOL = 1.6 mA(4)
IOL = 3.5 mA(4)
VOL1 Output Low Voltage, port 0, ALE , PSEN (6) 0.3
0.45
1.0
V
V
V
IOL = 200 µA(4)
IOL = 3.2 mA(4)
IOL = 7.0 mA(4)
VOH Output High V oltage, ports 1, 2, 3, 4 and 5 VCC - 0.3
VCC - 0.7
VCC - 1.5
V
V
V
IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
VCC = 5 V ± 10%
VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 0.3
VCC - 0.7
VCC - 1.5
V
V
V
IOH = -200 µA
IOH = -3.2 mA
IOH = -7.0 mA
VCC = 5 V ± 10%
RRST RST Pulldown Resistor 50 90 200 k Ω
IIL Logical 0 Input Current ports 1, 2, 3, 4 and 5 -50 µA Vin = 0.45 V
ILI Input Leakage Current for P0 only ±10 µA 0.45 V < Vin < VCC
ITL Logical 1 to 0 T r ansi tion Current, ports 1, 2, 3, 4
and 5 -650 µA Vin = 2.0 V
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DC Parameters for
Standard Voltage (2)
TA = 0°C to +70°C; VSS = 0 V; VCC = 3 V to 5.5 V; F = 0 to 33 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 3 V to 5.5 V; F = 0 to 33 MHz.
CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz
TA = 25°C
IPD Power Down Current 120 150 µAV
CC = 3 V to 5.5 V(3)
ICCOP
Power Supply Current on normal mode 0.7 Freq
(MHz) + 3 mA VCC = 5.5 V(1)
ICCProgFlash
Power Supply Current during Flash Write / Erase 0.3 Freq
(MHz) + 10 0.4 Freq
(MHz) + 12 mA VCC = 5.5 V(1)
ICCProgEE
Power Supply Current during EEprom data Write
/ Erase 0.7 Freq
(MHz) + 3 0.7 Freq
(MHz) + 18 mA VCC = 5.5 V(1)
ICCIDLE Power Supply Current on idle mode 0.4 Freq
(MHz) + 2 mA VCC = 5.5 V(2)
Table 43. DC Parameters in Standard Voltage (1)
Symbol Parameter Min Typ (5) Max Unit Test Conditions
Table 44. DC Parameters for Standard Voltage (2)
Symbol Parameter Min Typ(5) Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V
VIH Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High V oltage, XTAL1, RST 0.7 VCC VCC + 0.5 V
VOL Output Low V oltage, ports 1, 2, 3, 4 and 5 (6) 0.45 V IOL = 0.8 mA(4)
VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 0.45 V IOL = 1.6 mA(4)
VOH Output High Voltage, ports 1, 2, 3, 4 and 5 0.9 VCC VI
OH = -10 µA
VOH1 Output High Voltage, port 0, ALE, PSEN 0.9 VCC VI
OH = -40 µA
IIL Logical 0 Input Current ports 1, 2, 3, 4 and 5 -50 µA Vin = 0.45 V
ILI Input Leakage Current for P0 only ±10 µA 0.45 V < Vin < VCC
ITL Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
and 5 -650 µA Vin = 2.0 V
RRST RST Pulldown Resistor 50 90 200 kΩ
CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz
TA = 25°C
IPD Power Down Current 120 150 µAV
CC = 3 V to 5.5 V(3)
ICCOP Power Supply Current on normal mode 0.7 Freq (MHz)
+ 3 mA mA VCC = 5.5 V(1)
82 T89C51RD2 4243G–8051–05/03
ICCProgFlash
Power Supply Current during Flash Write / Era se 0 .3 Freq
(MHz) + 10 0.4 Freq (MHz)
+ 12 mA VCC = 5.5 V(1)
ICCProgEE
Power Supply Current during EEprom data Write
/ Erase 0.7 Freq
(MHz) + 3 0.7 Freq (MHz)
+ 18 mA VCC = 5.5 V(1)
ICCIDLE Power Sup ply Current on idle mode 0.5 Freq (MHz)
+ 2 mA mA VCC = 5.5 V(2)
Table 44. DC Parameters for Standard Voltage (2)
Symbol Parameter Min Typ(5) Max Unit Test Conditions
83
T89C51RD2
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DC Parameters for Low
Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 3.6 V; F = 0 to 25 MHz
TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 3.6 V; F = 0 to 25 MHz
4. Ope rati ng I CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns ( see Fi gure 36. ), VIL =
VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure
33.).
5. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC -
0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 34.).
6. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
ure 35.). In addition, the WDT must be inactive and the POF flag must be set.
7. C apaci tance lo ading on Ports 0 and 2 may ca use spuriou s noise pulses to be superimpos ed on the VOLs of ALE and Ports 1
and 3. The noise is due to ex tern al b us cap ac ita nce di sc harg in g in to the Port 0 and Port 2 pi ns when thes e p ins m ake 1 to 0
Table 45. DC Parameters for Low Voltage
Symbol Parameter Min Typ(5) Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V
VIH Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High V oltage, XTAL1, RST 0.7 VCC VCC + 0.5 V
VOL Output Low V oltage, ports 1, 2, 3, 4 and 5 (6) 0.45 V IOL = 0.8 mA(4)
VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 0.45 V IOL = 1.6 mA(4)
VOH Output High Voltage, ports 1, 2, 3, 4 and 5 0.9 VCC VI
OH = -10 µA
VOH1 Output High Voltage, port 0, ALE, PSEN 0.9 VCC VI
OH = -40 µA
IIL Logical 0 Input Current ports 1, 2, 3, 4 and 5 -50 µA Vin = 0.45 V
ILI Input Leakage Current ±10 µA 0.45 V < Vin < VCC
ITL Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
and 5 -650 µA Vin = 2.0 V
RRST RST Pulldown Resistor 50 90 200 kΩ
CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz
TA = 25°C
IPD Power Down Current 1 50 µAV
CC = 2.7 V to 3.6 V(3)
ICCOP Power Supply Current on normal mode 0.6 Freq (MHz)
+ 3 mA VCC = 3.6 V(1)
ICCProgFlash
Power Supply Current during Flash Write / Era se 0 .3 Freq
(MHz) + 10 0.4 Freq (MHz)
+ 12 mA VCC = 3.6 V(1)
ICCProgEE
Power Supply Current during EEprom data Write
/ Erase 0.7 Freq
(MHz) + 3 0.7 Freq (MHz)
+ 18 mA VCC = 3.6 V(1)
ICCIDLE Power Sup ply Current on idle mode 0.3 Freq (MHz)
+ 2 m A V CC = 3.6 V(2)
84 T89C51RD2 4243G–8051–05/03
transitio ns during bus operatio n. In the worst cases (ca pa cit iv e loa din g 100 pF), the noise pulse on the ALE line may exc ee d
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
8. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature..
9. U nde r stead y sta te (non-t r ans ie nt) con dit ion s, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pi ns: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
Figure 33. ICC Test Condition, Active Mode
Figure 34. ICC Test Condition, Idle Mode
EA
VCC
VCC
ICC
(NC)
CLOCK
SIGNAL
VCC
All other pins are disconnected.
RST
XTAL2
XTAL1
VSS
VCC
P0
RST EA
XTAL2
XTAL1
VSS
VCC
VCC
ICC
(NC)
P0
VCC
All other pins are disconnected.
CLOCK
SIGNAL
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Figure 35. ICC Test Condition, Power-Down Mode
Figure 36. Clock Signal Waveform for ICC Tests in Active and Idle Modes
AC Parameters
Explanation of the AC
Symbols Each timing symbol has 5 char acters. T he firs t character is always a “T” (stands for
time). The other characters, depending on their positions, stand for the name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example:TAVLL = Time for Addr es s Valid to ALE Low .
TLLPL = Time for ALE Low to PSEN Low.
TA = 0 to +70°C; VSS = 0 V; VCC = 5 V ± 10%; M range.
TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; M range.
TA = 0 to +70°C; VSS = 0 V; 2.7 V < VCC < 3.3 V; L range.
TA = -40°C to +85°C; VSS = 0 V; 2.7 V < VCC < 3.3 V; L range.
AC characteristics of -M parts at 3 volts are similar to -L parts
(Load Cap acitance for port 0, ALE and PSEN = 100 pF ; Load Capa citance for all other
outputs = 80 pF.)
Table 44, Table 48 and Table 50 give the description of each AC symbols.
Table 46, Table 49 and Table 51 give for each range the AC parameter.
Table 47, Table 50 and Table 52 give the frequency derating formula of the AC parame-
ter for each s peed ran ge de scr ipt ion . To calc ula te eac h A C symbo ls . tak e the x value in
the correponding column (-M or -L) and use this value in the formula.
Example: TLLIU for -M and 20 MHz, Standard clock.
x = 35 ns
T = 50 ns
TCCIV = 4T - x = 165 ns
VCC-0.5V
0.45V 0.7VCC
0.2VCC-0.1
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
RST EA
XTAL2
XTAL1
VSS
VCC
VCC
ICC
(NC)
P0
VCC
All other pins are disconnected.
86 T89C51RD2 4243G–8051–05/03
External Program Memory
Characteristics
Symbol Parameter
T Oscillator clock period
TLHLL ALE pulse width
TAVLL Address Valid to ALE
TLLAX Address Hold After ALE
TLLIV ALE to Valid Instruction In
TLLPL ALE to PSEN
TPLPH PSEN Pulse Width
TPLIV PSEN t o Valid Instruction In
TPXIX Input Instruction Hold After P SE N
TPXIZ Input Instruction Float After PSEN
TAVIV Address to Valid Instruction In
TPLAZ PSEN Low to Address Float
Table 46. AC Parameters for a Fix Clock
Symbol -M -L Units
MinMaxMinMax
T25 25 ns
TLHLL 40 40 ns
TAVLL 10 10 ns
TLLAX 10 10 ns
TLLIV 70 70 ns
TLLPL 15 15 ns
TPLPH 55 55 ns
TPLIV 35 35 ns
TPXIX 00 ns
TPXIZ 18 18 ns
TAVIV 85 85 ns
TPLAZ 10 10 ns
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External Program Memory
Read Cycle
Table 47. AC Parameters for a Variable Clock
Symbol Type Stan da r d Clock X2 Clock X parameter for -
M range X parameter for -
L range Units
TLHLL Min 2 T - x T - x 10 10 ns
TAVLL Min T - x 0.5 T - x 15 15 ns
TLLAX Min T - x 0.5 T - x 15 15 ns
TLLIV Max 4 T - x 2 T - x 30 30 ns
TLLPL Min T - x 0.5 T - x 10 10 ns
TPLPH Min 3 T - x 1.5 T - x 20 20 ns
TPLIV Max 3 T - x 1.5 T - x 40 40 ns
TPXIX Min x x 0 0 ns
TPXIZ Max T - x 0.5 T - x 7 7 ns
TAVIV Max 5 T - x 2.5 T - x 40 40 ns
TPLAZ Max x x 10 10 ns
TPLIV
TPLAZ
ALE
PSEN
PORT 0
PORT 2
A0-A7A0-A7 INSTR ININSTR IN INSTR IN
ADDRESS
OR SFR-P2 ADDRESS A8-A15ADDRESS A8-A15
12 TCLCL
TAVIV
TLHLL
TAVLL
TLLIV
TLLPL
TPLPH
TPXAV
TPXIX
TPXIZ
TLLAX
88 T89C51RD2 4243G–8051–05/03
Exte rnal Data Memory
Characteristics
Table 48. Symbol Description
Symbol Parameter
TRLRH RD Pulse Width
TWLWH WR Pulse Width
TRLDV RD to Valid Data In
TRHDX Data Hold After RD
TRHDZ Data Float After RD
TLLDV AL E to Val i d D ata In
TAVDV Address to Valid Data In
TLLWL ALE to WR or RD
TAVWL Address to WR or RD
TQVWX Data Valid to WR Transition
TQVWH Data set-up to WR High
TWHQX Data Hold After WR
TRLAZ RD Low to Address Float
TWHLH RD or WR High to ALE high
Table 49. AC Parameters for a Fix Clock
Symbol -M -L Units
MinMaxMinMax
TRLRH 130 130 ns
TWLWH 130 130 ns
TRLDV 100 100 ns
TRHDX 00 ns
TRHDZ 30 30 ns
TLLDV 160 160 ns
TAVDV 165 165 ns
TLLWL 50 100 50 100 ns
TAVWL 75 75 ns
TQVWX 10 10 ns
TQVWH 160 160 ns
TWHQX 15 15 ns
TRLAZ 00ns
TWHLH 10 40 10 40 ns
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External Data Memory Write
Cycle
Table 50. AC Parameters for a Variable Clock
Symbol Type Standard Clock X2 Clock X parameter for -
M range X parameter for -
L range Units
TRLRH Min 6 T - x 3 T - x 20 20 ns
TWLWH Min 6 T - x 3 T - x 20 20 ns
TRLDV Max 5 T - x 2.5 T - x 25 25 ns
TRHDX Min x x 0 0 ns
TRHDZ Max 2 T - x T - x 20 20 ns
TLLDV Max 8 T - x 4T -x 40 40 ns
TAVDV Max 9 T - x 4.5 T - x 60 60 ns
TLLWL Min 3 T - x 1.5 T - x 25 25 ns
TLLWL Max 3 T + x 1.5 T + x 25 25 ns
TAVWL Min 4 T - x 2 T - x 25 25 ns
TQVWX Min T - x 0.5 T - x 15 15 n s
TQVWH Min 7 T - x 3.5 T - x 15 15 ns
TWHQX Min T - x 0 .5 T - x 10 10 ns
TRLAZ Max x x 0 0 ns
TWHLH Min T - x 0.5 T - x 15 15 ns
TWHLH Max T + x 0.5 T + x 15 15 ns
TQVWH
TLLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7 DATA OUT
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TQVWX
ADDRESS A8-A15 OR SFR P2
TWHQX
TWHLH
TWLWH
90 T89C51RD2 4243G–8051–05/03
External Data Memory Read
Cycle
Serial Port Timing - Shift
Register Mode
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TRLAZ
ADDRES S A8-A 15 OR SF R P2
TRHDZ
TWHLH
TRLRH
TLLDV
TRHDX
TLLAX
TAVDV
Symbol Parameter
TXLXL Serial port clock cycl e time
TQVHX Output data set-up to clock rising edge
TXHQX Output data hold after clock rising edge
TXHDX Input data hold after clock rising edge
TXHDV Clock rising edge to input data valid
Table 51. AC Parameters for a Fix Clock
Symbol -M -L Units
MinMaxMinMax
TXLXL 300 300 ns
TQVHX 200 200 ns
TXHQX 30 30 ns
TXHDX 00 ns
TXHDV 117 117 ns
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Shif t Register Timing
Waveforms
Flash EEPROM Programming
and Verification
Characteristics
TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10%.
Table 52. AC Parameters for a Variable Clock
Symbol Type Standard Clock X2 Clock X parameter for -
M range X parameter for -
L range Units
TXLXL Min 12 T 6 T ns
TQVHX Min 10 T - x 5 T - x 50 50 ns
TXHQX Min 2 T - x T - x 20 20 ns
TXHDX Min x x 0 0 ns
TXHDV Max 10 T - x 5 T- x 133 133 ns
VALIDVALID
INPUT DATA VALIDVALID
0123456 87
ALE
CLOCK
OUTPUT DATA
WRIT E to SBU F
CLEAR RI
TXLXL
TQVXH TXHQX
TXHDV TXHDX SET TI
SET RI
INSTRUCTION
01234567
VALID VALID VALID VALID
Table 53. Flash Programming Parameters
Symbol Parameter Min Max Units
1/TCLCL Oscillat or Frquency 4 6 MHz
TEHAZ Control to address float 48 TCLCL
TAVGL Address Setup to PROG Low 48 TCLCL
TGHAX Adress Hold after PROG 48 TCLCL
TDVGL Data Setup to PROG Low 48 TCLCL
TGHDX Dat a Hold after PROG 48 TCLCL
TGLGH PROG Wi dth for PGMC and PGXC* 10 20 ms
TGLGH PROG Wi dth for PGML 48 TCLCL
TAVQV A ddress t o Valid Data 48 TCLCL
TELQV ENABLE Low to Data Valid 48 TCLCL
TEHQZ Data Float after ENABLE 0 48 TCLCL
92 T89C51RD2 4243G–8051–05/03
Flash EEPROM Programming
and Verification Waveforms
External Clo ck Driv e
Characteristics (XTAL1)
External Clo ck Driv e
Waveforms
AC Testing Input/Output
Waveforms
TEHAZ
ALE/PROG
TAVGL
TDVGL
P0
P1.0-P1.7
P2.0-P2.4
P3.4-P3.5
CONTROL
SIGNALS
(ENABLE)
ADDRESS
DATA IN
TGHAX
TGHDX
TGLGH
ADDRESS
DATA OUT
TAVQV
TELQV TEHQZ
PROGRAMMING VERIFICATION
Table 54. AC Parameters
Symbol Parameter Min Max Units
TCLCL Oscillat or Period 25 ns
TCHCX High Time 5 ns
TCLCX Low Time 5 ns
TCLCH Rise Time 5ns
TCHCL Fall Time 5ns
TCHCX/TCLCX Cyclic ratio in X2 mode 40 60 %
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL TCLCX TCLCL
TCLCH
TCHCX
INPUT/OUTPUT 0.2 VCC + 0.9
0.2 VCC - 0.1
VCC -0.5 V
0.45 V
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AC in pu ts dur ing tes ting are dri ven a t VCC - 0.5 for a logic “1” and 0.45V for a l ogic “0”.
Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
Float Waveforms
For timing purposes as port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level
occurs. IOL/IOH ≥ ± 20mA.
FLOAT
VOH - 0.1 V
VOL + 0.1 V
VLOAD VLOAD + 0.1 V
VLOAD - 0.1 V
94 T89C51RD2 4243G–8051–05/03
Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
This diagram indicates when signals are clocked internally. The time it takes the signals
to propa gate to the pi ns, howeve r, ranges from 25 to 125 ns. This pro pagatio n delay is
dependent on variables such as temperature and pin loading. Propagation also varies
from output to output and component. Typically though (TA=25°C fully loaded) RD and
WR propagation delays are approximately 50ns . The other signals are typically 85 ns.
Propagation delays are incorporated in the AC specifications.
DATA PCL OUT DATA PCL OUT DATA PCL OUT
SAMPLED SAMPLED SAMPLED
STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
FLOAT FLOAT FLOAT
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
INDICATES ADDRESS TRANSITIONS
EXTERNAL PROGRAM MEMORY FETCH
FLOAT
DATA
SAMPLED
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMO RY IS EXTERNAL )
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
PCL OU T (IF PR OG R AM
MEMORY IS EXTERNAL)
OLD DATA NEW DATA P0 PINS SAMPLED
P1, P2 , P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED
P0 PINS SAMP LED
RXD SAM PLED
INTERNAL
CLOCK
XTAL2
ALE
PSEN
P0
P2 (EXT)
READ CYCLE
WRITE CYCLE
RD
P0
P2
WR
PORT OPERAT I O N
MOV PORT SRC
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INCLUDES INTO. INT1. T O T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
DATA OUT
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0
P2
RXD SAM PLED
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Ordering Information
Part Number Memory Size Supply Voltage Temperature Range Package Packing
T89C51RD2-3CSCL 64 Kby tes 2.7 - 3.6V Com mercial PDIL40 Stick
T89C51RD2-3CSCM 64 Kbytes 4.5 - 5.5V Commercial PDIL40 Stick
T89C51RD2-3CSIL 64 Kbytes 2.7 - 3.6V Industrial PDIL40 Stick
T89C51RD2-3CSIM 64 Kbytes 4.5 - 5.5V Indust rial PDIL40 Stick
T89C51RD2-DDVCM 64 Kbytes 4.5 - 5.5V Commercial Dice Tr ay & Dry Pack
T89C51RD2-RDTCL 64 Kbytes 2.7 - 3.6V Commercial V Q FP64 Tray
T89C51RD2-RDTCM 64 Kbytes 4.5 - 5.5V Commercial VQ FP64 Tray
T89C51RD2-RDTIL 64 Kbytes 2.7 - 3.6V Industrial V Q FP64 Tray
T89C51RD2-RDTIM 64 Kbytes 4.5 - 5.5V Industrial V Q FP64 Tray
T89C51RD2-RDVIM 64 Kby tes 4.5 - 5.5V Industrial V Q FP64 Tray + Dry Pack
T89C51RD2-RLFCM 64 Kbytes 4.5 - 5.5V Commerc ial V Q FP44 Tape & Reel + Dry Pack
T89C51RD2-RLFIM 64 Kbytes 4.5 - 5.5V Industrial V Q FP44 Tape & Reel + Dry Pack
T89C51RD2-RLRIM 64 Kbytes 4.5 - 5.5V I ndustrial VQFP44 Tape & Reel
T89C51RD2-RLTCL 64 Kbytes 2.7 - 3.6V Commercial VQFP44 Tray
T89C51RD2-RLTCM 64 Kbytes 4.5 - 5.5V Commercial VQFP44 Tr ay
T89C51RD2-RLTIL 64 Kby tes 2.7 - 3.6V I ndustrial VQFP44 Tray
T89C51RD2-RLTIM 64 Kby tes 4.5 - 5.5V Industrial V Q FP44 Tray
T89C51RD2-RLVCL 64 Kbytes 2.7 - 3.6V Commercial VQFP44 Tray + Dry Pack
T89C51RD2-RLVCM 64 Kbytes 4.5 - 5.5V Commercial V Q FP44 Tray + Dry Pack
T89C51RD2-RLVIL 64 Kbytes 2.7 - 3.6V I ndust rial V Q FP44 Tray + Dry Pack
T89C51RD2-RLVIM 64 Kbytes 4.5 - 5.5V I ndust rial V Q FP44 Tray + Dry Pack
T89C51RD2-SLFCL 64 Kbytes 2.7 - 3.6V Commercial P L C44 Tape & Reel + Dry Pack
T89C51RD2-SLRCM 64 Kbytes 4.5 - 5.5V Com merc ial P LC44 Tape & Reel
T89C51RD2-SLRIM 64 Kbytes 4.5 - 5.5V Industrial PLC44 Tape & Reel
T89C51RD2-SLSCL 64 Kbytes 2.7 - 3.6V Commercial PLC44 Stic k
T89C51RD2-SLSCM 64 Kby tes 4.5 - 5.5V Com merc ial P LC44 Stick
T89C51RD2-SLSIL 64 Kbytes 2.7 - 3.6V Indust rial P LC44 Stick
T89C51RD2-SLSIM 64 Kbytes 4.5 - 5.5V Indust rial P LC44 Stick
T89C51RD2-SLUCM 64 Kbytes 4.5 - 5.5V Com merc ial P L C44 Stick + Dry Pack
T89C51RD2-SLUIM 64 Kbytes 4.5 - 5.5V Industrial P LC44 Stick + Dry Pack
T89C51RD2-SMRIL 64 Kbytes 2.7 - 3.6V Industrial PLCC68 Tape & Reel
96
T89C51RD2 4243G–8051–05/03
T89C51RD2-SMSCL 64 Kbytes 2.7 - 3.6V Commercial PLCC68 Stick
T89C51RD2-SMSCM 64 Kbytes 4.5 - 5.5V Commercial PLCC68 Stick
T89C51RD2-SMSIL 64 Kbytes 2.7 - 3.6V Industrial PLCC68 Stic k
T89C51RD2-SMSIM 64 Kbytes 4.5 - 5.5V Industrial PLCC68 Stick
T89C51RD2-SMUCM 64 Kbytes 4.5 - 5.5V Com merc ial PLCC68 Stick + Dry Pack
T89C51RD2-SMUIM 64 Kbytes 4.5 - 5.5V Industrial PLCC68 Stic k + Dry Pack
Part Number Memory Size Supply Voltage Temperature Range Package Packing
97
T89C51RD2
4243G–8051–05/03
Package Drawings
DIL40
98
T89C51RD2 4243G–8051–05/03
PLCC44
99
T89C51RD2
4243G–8051–05/03
VQFP44
100
T89C51RD2 4243G–8051–05/03
VQFP64
101
T89C51RD2
4243G–8051–05/03
PLCC68
102
T89C51RD2 4243G–8051–05/03
VQFP64
103
T89C51RD2
4243G–8051–05/03
Datasheet Change
Log for T89C51RD2
Changes from 4243F-
02/01 to 4243G-05/03 1. Added bootloader ISP protocol description.
Printed on recycled paper.
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4243G–8051–05/03 /xM
