February 2010 Doc ID 5853 Rev 3 1/18
1
L9380
Triple high-side MOSFET driver
Features
■Overvoltage charge pump shut off
■For VS > 25 V
■Reverse battery protection (referring to the
application circuit diagram)
■Programmable overload protection function for
channel 1 and 2
■Open ground protection function for channel 1
and 2
■Constant gate charge/discharge current
Description
The L9380 device is a controller for three external
N-channel power MOS transistors in "High-Side
Switch" configuration.
It is intended for relays replacement in automotive
electric control units.
SO20
Table 1. Device summary
Order code Package Packing
L9380 SO20 Tube
L9380-TR SO20 Tape and reel
L9380-LF(1)
1. Devices in ECOPACK® packages (see Section 5: Package information on page 16).
SO20 Tube
L9380-TR-LF(1) SO20 Tape and reel
www.st.com
Contents L9380
2/18 Doc ID 5853 Rev 3
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Typical characteristics curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.1 Electromagnetic emission classification (EME) . . . . . . . . . . . . . . . . . . . 15
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
L9380 List of tables
Doc ID 5853 Rev 3 3/18
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pins function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Electromagnetic emission classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
List of figures L9380
4/18 Doc ID 5853 Rev 3
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Timing characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Drain, source input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Charge loading time as function of VS (Vcp = 8 V +VS) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Charge pump current as function of the charge voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Ground loss protection gate discarge current for source voltage . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Input current as function of the input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Overvoltage shutdown of the charge pump with hysteresis . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Measured circuit (The EMS of the device was verified in the below described setup) . . . . 14
Figure 13. Printed circuit board (PCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. SO20 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
L9380 Block diagram
Doc ID 5853 Rev 3 5/18
1 Block diagram
Figure 1. Block diagram
VS
GND
DRIVER 1
≥1
ENN
-
CHARGE PUMP
OVERVOLTAGE
CP
T1
VSI
IN1
+
≥1
VSI
T2
IN2
IN3
EN
CP
IPR D1
S1
G1
DRIVER 2
≥1
ENN
-
VSI
+
≥1
VSI
CP
D2
S2
G2
IPR
ENN ≥1
VSI
CP
DRIVER 3
G3
ENN VS VSI
PR
I
PR
2V
REFERENCE
REG.
D98AT390
Pins description L9380
6/18 Doc ID 5853 Rev 3
2 Pins description
Figure 2. Pins connection (top view)
Table 2. Pins function
N° Pin
name Function
1T1
Timer capacitor; the capacitor defines the time for the channel 1 shut down, after overload of
the external MOS transistor has been detected.
2V
S
Supply voltage.
4T2
Timer capacitor; the capacitor defines the time for the channel 2 shut down, after overload of
the external MOS transistor has been detected.
5PR
Programming resistor for overload detetcion threshold; the resistor from this pin to ground
defines the drain pin current and the charging of the timer capacitor.
6 IN3 Input 3; equal to IN1.
7 IN2 Input 2; equal to IN1.
8IN1
Input 1; logic signal applied to this pin controls the driver 1; this pin features a current source
to assure defined high status when the pin is open.
9 EN Enable logic signal high on this pin enables all channels
10 GND Ground
11 G3 Gate 3 driver output; current source from CP or ground
12 G2 Gate 2 driver output; current source from CP or ground
14 S2 Source 2 sense input; monitors the source voltage.
15 S1 Source 1 sense input; monitors the source voltage.
16 G1 Gate 1 driver output; current source from CP or ground
17 D2 Drain 2 sense input; a programmable input bias current defines the drop across the external
resistor R
D1
; this drop fixes the overload threshold of the external MOS.
19 D1 Drain 1 sense input; a programmable input bias current defines the drop across the external
resistor R
D1
; this drop fixes the overload threshold of the external MOS.
20 CP
Charge pump capacitor; a alternating current source at this pin charges the connected
capacitor C
CP
to a voltage 10V higher than V
S
; the charge stored in this capacitor is than used
to charge all the three gates of the power MOS transistors.
3, 13, 18 NC Not connected
T1
VS
N.C.
T2
PR
IN2
IN3
IN1
EN G2
N.C.
S2
G1
S1
D2
N.C.
D1
CP1
3
2
4
5
6
7
8
9
18
17
16
15
14
12
13
11
19
10
20
GND G3
D98AT391
L9380 Electrical specifications
Doc ID 5853 Rev 3 7/18
3 Electrical specifications
3.1 Absolute maximum ratings
Note: ESD for all pins, except the timer pins, are according to MIL 883C, tested at 2 kV,
corresponds to a maximum energy dissipation of 0.2 mJ.
The timer pins are tested with 800 V.
3.2 Thermal data
3.3 Electrical characteristics
7V ≤ V
S
≤ 18.5 V; -40° C ≤ T
J
≤ 150 °C, unless otherwise specified.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
S
DC supply voltage -0.3 to +27 V
V
S
Supply voltage pulse (t ≤ 400 ms) 45 V
ΔV
S
/dt Supply voltage slope -10 to +10 V/µs
V
IN,EN
Input / enable voltage -0.3 to +7 V
V
T
Timer voltage -0.3 to 27 V
V
D, G, S
Drain, gate, source voltage -15 to +27 V
V
D, G, S
Drain, gate, source voltage pulse (t ≤ 400 ms) 45 V
I
D, G, S
Drain, gate, source current (t ≤ 2 ms) 0 to +4 mA
T
j
Operating junction temperature -40 to 150 °C
T
stg
Storage temperature -65 to 150 °C
Table 4. Thermal data
Symbol Parameter Value Unit
R
th j-amb
Thermal resistance junction-to-ambient 100 °C/W
Table 5. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
Supply
I
VS
Static operating supply current V
S
= 14 V - - 2.5 mA
Charge pump
V
CP
Charge pump voltage above VS-8-17V
I
CP
Charge pump current V
S
= 7 V, V
CP
= 15 V, T
j
≥ 25 °C -23 - -12 µA
V
S
= 7 V, V
CP
= 15 V, T
j
< 25 °C -23 - -10 µA
Electrical specifications L9380
8/18 Doc ID 5853 Rev 3
Function is given for supply voltage down to 5.5 V.
Function means: the channels are controlled from the inputs, some other parameters may
exceed the limit. In this case the programming voltage and timer threshold will be lower. This
leads to a lower protection threshold and time.
I
CP
Charge pump current V
S
= 12 V, V
CP
= 20 V, T
j
≥ 25 °C -70 - -45 µA
V
S
= 12 V, V
CP
= 20 V, T
j
< 25 °C -70 - -38 µA
t
CP
Charging time V
CP
= V
S
+ 8 V C
CP
= 100 pF - - 200 µs
V
SCP off
Overvoltage shut down - 20 - 30 V
V
SCP hys
Overvoltage shut down hysteresis
(1)
- 50 200 1000 mV
f
CP
Charge pump frequency (1) - 100 250 400 KHz
Gate drivers
I
GSo
Gate source current V
G
= V
S
-5 -3 -1 mA
I
GSi
Gate sink current V
G
≥ 0.8 V 1 3 5 mA
I
GCP
Charge pump current on the gate V
S
= 12 V, V
G
= 20 V, T
j
≥ 25 °C -60 - -35 µA
V
S
= 12V, V
G
= 20 V, T
j
< 25 °C -60 - -28 µA
Drain - source sensing
V
PR
Bias current programming voltage
10 µA ≤ I
PR
≤ 100 µA; V
D
≥ 4 V 1.822.2V
I
D Leak
Drain pin leakage current V
S
= 0 V; V
D
=14 V 0 - 5 A
I
D
Drain pin bias current V
S
≥ V
D
+ 1 V; V
D
≥ 5 V 0.9 I
PR
- 1.1 I
PR
I
Smax
Source pin input current V
S
≥ V
D
+ 1 V; V
D
≥ 7 V 10 - 60 A
V
HYST
Comparator hysteresis - - 20 - mV
Timer
V
THi
Timer threshold high - 4 4.4 4.8 V
V
TLo
Timer threshold low - 0.3 0.4 0.5 V
I
T
Timer current
IN = 5 V; V
T
= 2 V
IN = 0 V; V
S
< V
D
;
V
D
≥ 5 V; V
T
= 2 V
0.4 I
PR
-0.6
IPR
-
0.6 I
PR
-0.4
IPR
-
Inputs
V
LOW
Input enable low voltage - -0.3 - 1 V
V
HIGH
Input enable high voltage - 3 - 7 V
V
INhys
Input enable hysteresis(1) - 50 200 500 mV
I
IN
Input source current V
IN
≤ 3 V -30 - -5 μA
I
EN
Enable sink current V
EN
≥ 1 V 5 - 30 μA
t
d
Transfer time IN/ENABLE V
S
= 14 V V
G
= V
S
; Open Gate - - 2.5 µs
1. Not measured guaranteed by design.
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
L9380 Functional description
Doc ID 5853 Rev 3 9/18
4 Functional description
The triple high-side Power-MOS Driver features all necessary control and protection
functions to switch on three Power-MOS transistors operating as High-Side switches in
automotive electronic control units. The key application field is relays replacement in
systems where high current loads, usually motors with nominal currents of about 40 A
connected to ground, has to be switched.
A high signal at the EN pin enables all three channels. With enable low gates are clamped to
ground. In this condition the gate sink current is higher than the specified 3 mA. An enable
low signal makes also a reset of the timer.
A low signal at the inputs switch on the gates of the external MOS. A short circuit at the input
leads to permanent activation of the concerned channel. In this case the device can be
disabled with the enable pin. The charge pump loading is not influenced due to the enable
input.
An external N-channel MOS driver in high side configuration needs a gate driving voltage
higher than V
S
. It is generated by means of a charge pump with integrated charge transfer
capacitors and one external charge storage capacitor C
CP
.
The charge pump is dimensioned to load a capacitor CCP of 33 nF in less than 20 ms up to
8V above V
S
. The value of C
CP
depends on the input capacitance of the external MOS and
the decay of the charge pump voltage down to that value where no significant influence on
the application occurs.
The necessary charging time for C
CP
has to be respected in the sequence of the input
control signals.
As a consequence the lower gate to source voltage can cause a higher drop across the
Power-MOS and get into overload condition. In this case the overload protection timer will
start.
After the protection time the concerned channel will be switched off. Channel 3 is not
equipped with an overload protection. The same situation can occur due to a discharge of
the storage capacitor caused by the gate short to ground. The gate driver that is supplied
from the pin CP, which is the charge pump output, has a sink and source current capability
of 3 mA. For a short-circuit of the load (source to ground) the L9380 has no gate to source
limitation. The gate source protection must be done externally.
Channel 1 and 2 provide drain to source voltage sensing possibility with programmable
shut-off delay when the activation threshold was exceeded.
This threshold V
DSmin
is set by the external resistor R
D
. The bias current flowing through this
resistor is determined by the programming resistor R
PR
. This external resistor R
PR
defines
also the charge and discharge current of the timer capacitor C
CT
. The drain to source
threshold V
DSmin
and the timer shut off delay time To
ff
can be calculated:
Toff = 4.4 CT RPR
VDSmin VPR
RD
RPR
------------
⎝⎠
⎜⎟
⎛⎞
=
Functional description L9380
10/18 Doc ID 5853 Rev 3
In application which don’t use the overload protection or if one channel is not used, the
Timer pin of this channel must be connected to ground and the drain pin with a resistor to
V
bat
.
The timing characteristic illustrates the function and the meaning of V
DSmin
and Toff (see
Figure 6). The input current of the overload sense comparator is specified as I
Smax
. The sum
I
PR
+ I
Dmax
generates a drop across the external resistor R
D
if the drain pin voltage is higher
than the source pin (see Figure 4). In the switching point the comparator input source pin
currents are equal and the half of the specified current I
Smax
. For an offset compensation
equal external resistors (RD = RS) at drain and source pin are imperative. The drain sense
comparator, which detects the overload, has a symmetrical hysteresis of 20 mV (see
Figure 5).
Exceeding the source pin voltage by 10 mV with respect to the drain voltage forces the timer
capacitor to discharge. Decreasing the source pin voltage 10 mV lower than the drain pin
voltage an overload of the external MOS is detected and the timer capacitor will be loaded.
After reaching a voltage at pin CT higher than the timer threshold V
Thi
the influenced
channel is switched off. In this case the overload is stored in the timer capacitor.
The timer capacitor will be discharged with a ’High’ signal at the input (see Figure 3). After
reaching the lower timer threshold V
TLo
the overload protection is reset and the channel is
able to switch on again.
Figure 3. Timing characteristic
Figure 4. Drain, source input current.
VIN
VG
VS
VT
4.4V
0.4V
VDSmin
tdtd
Toff
D98AT392
ID
I
PR
+ I
Dmax
I
Smax
I
S
V
D
> V
S
V
S
> V
D
V
S
= V
D
I
PR
0
D98AT393
L9380 Functional description
Doc ID 5853 Rev 3 11/18
Figure 5. Comparator hysteresis
The application diagram is shown in Figure 6. Because of the transients present at the
power lines during operation and possible disturbances in the system the external resistors
are necessary.
Positive ISO-Pulses at Drain, Gate Source are clamped with an active clamping structure.
The clamping voltage is less than 60V. Negative Pulses are only clamped with the ESD-
Structure less than -15 V. This transients lower than -15 V can influence the other channels.
In order to protect the transistor against overload and gate breakdown protection diodes
between gate and source and gate and drain has to be connected. In case of overvoltage
into V
S
(V
S
> 20 V) the charge pump oscillation is stopped.
Then the charge pump capacitor will be loaded by a diode and a resistor in series up to V
S
(see Figure 1). In this case the channels are not influenced. In reverse battery condition the
pins D1, D2, S1, S2 follow the battery potential down to -13 V (high impedance) and the
gate driver pins G1, G2 is referred to S1, S2. In this way it is assured that M1 and M2 will not
be driven into the linear conductive mode. This protection function is operating for V
S1
, V
S2
down to -15 V. The gate driver output G3 is referred to the D1 in this case. This function
guarantees that the source to source connected N-Channel MOS transistors M3 and M4
remains OFF.
All the supplies and the in- and output of the PC Board are supplied with a 40 wires flat
cable (not used wires are left open). This cable is submitted to the RF in the strip-line like
described in DIN 40839-4 or ISO 11456-5.
The measured circuit was build up on a PCB board with ground plane. In the frequency
range from 1 MHz to 400 MHz and 80 % AM-modulation of 1 kHz with field strength of
200 V/m no influence to the basic function was detected on a typical device.
The failure criteria is an envelope of the output signal with 20 % in the amplitude and 2 % in
the time.
V
T
-10mV V
Dr
+10mV V
So
D98AT394
Functional description L9380
12/18 Doc ID 5853 Rev 3
Figure 6. Application circuit
Recommendations to the application circuit: The timer and the charge capacitors are loaded
with an alternating current source. A short ground connection of the charge capacitor is
indispensable to avoid electromagnetic emigrations. The dimension of the resistors RD, RG
and RS have to respect the maximum current during transients at each pin.
VS
GND
DRIVER 1
≥1
ENN
-
CHARGE PUMP
OVERVOLTAGE
CP
T1
VSI
IN1
+
≥1
VSI
T2
IN2
IN3
EN
CP
IPR
D1
S1
G1
DRIVER 2
≥1
ENN
-
VSI
+
≥1
VSI
CP
D2
S2
G2
IPR
ENN ≥1
VSI
CP
DRIVER 3
G3
ENN VS VSI
PR
IPR
2V
REFERENCE
REG.
C1D2
D1
C2
C3
C4
MICROCONTROLLER
LOAD CONTROL
M1
M2
R1
R2
R3
R4
R5
R6
D3
D4
D5
D6
R7
D7
M3
M4
D8
L4L3L2L1
VALUE DRIVER
U405
MM1
MM2
D98AT395A
VBAT
R8
L9380 Functional description
Doc ID 5853 Rev 3 13/18
4.1 Typical characteristics curve
Depending on production spread, certain deviations may occure. For limits see Ta bl e 5 .
Figure 7. Charge loading time as function of
V
S
(V
cp
= 8 V +V
S
)
Figure 8. Charge pump current as function of
the charge voltage
Figure 9. Ground loss protection gate
discarge current for source voltage
Figure 10. Input current as function of the
input voltage
Figure 11. Overvoltage shutdown of the
charge pump with hysteresis
6 10121416V
S(V)8
0
10
20
t
CH
(ms)
68nF
33nF
10nF
D98AT396
71727V
C(V)
0
50
100
ICP
(μA)
D98AT397
7V
10V
12V 16V
-15 -10 -5 V
S
(V)
-1000
-800
-600
-400
-200
I
G
(μA)
D98AT398
01234V
I
(V)
-20
-15
-10
-5
I
C
(μA)
D98AT399
24 24.5 25 25.5 VS(V)
20
30
VCH
(V)
D98AT400
Functional description L9380
14/18 Doc ID 5853 Rev 3
Figure 12. Measured circuit (The EMS of the device was verified in the below described setup)
VS
GND
DRIVER 1
≥1
ENN
-
CHARGE PUMP
OVERVOLTAGE
CP
T1
VSI
IN1
+
≥1
VSI
T2
IN2
IN3
EN
CP
IPR
D1
S1
G1
DRIVER 2
≥1
ENN
-
VSI
+
≥1
VSI
CP
D2
S2
G2
IPR
ENN
≥1
VSI
CP
DRIVER 3
G3
ENN VS VSI
PR
I
PR
2V
REFERENCE
REG.
33μFSMT_39A
SMB7W01-200
10nF
10nF
33nF
B60N06
10KΩ
2KΩ
2KΩ
10KΩ
2KΩ
33V
18V
33V
18V
33V
18V
D98AT401
CAR-BATTERY
1KΩ
1KΩ
1KΩ
100nF
5.6V 4.7nF 2.2nF
10KΩ
2.2nF
10KΩ
2.2nF
10KΩ
2KΩ
STD17N06 5Ω
B60N06
5Ω
B60N06
STD17N06
STD17N06
4.7nF5.6V
3.125Hz
6.25Hz
12.5Hz
25Hz
f
2
4.7nF5.6V
1KΩ
4.7nF
PC-BOARD IN RF BOX
5.6V
10
9
8
7
2m
STRIPLINE
U(t)
f
2
f
2
1KΩ
1KΩ
1KΩ
EN
IN3
IN2
6
IN1
2
V
S
1
V
BAT
2.2nF
2.2nF
2.2nF
2.2nF
OUT1
3
OUT2
4
OUT3
5
ANECHOIC CHAMBER
10KΩ
20KΩ
BNC
BNC
+
8
9
7
6
345 10 12
L9380 Functional description
Doc ID 5853 Rev 3 15/18
Figure 13. Printed circuit board (PCB)
4.1.1 Electromagnetic emission classification (EME)
Electromagnetic emission classes presented below are typical data found on bench test. For
detailes test description please refer to "Electromagnetic Emission (EME) Measurement of
Integrated Circuits, DC to 1 GHz" of VDE/ZVEI work group 767.13 and VDE/ZVEI work
group 767.14 or IEC project number 47A 1967Ed. This data is targeted to board designers
to allow an estimation of emission filtering effort required in application. All measurements
are done with the EMS-board (See Figure 12 and 13).
Note: Electromagnetic Emission and Susceptivity is not tested in production.
Table 6. Electromagnetic emission classification
Pin EME class Remark
VCP G - w -
Package information L9380
16/18 Doc ID 5853 Rev 3
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 14. SO20 mechanical data and package dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.200
C 0.23 0.32 0.009 0.013
D (1) 12.60 13.00 0.496 0.512
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.0 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO20
0016022 D
L9380
18/18 Doc ID 5853 Rev 3
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