Hit achi Eu rop e Lt d . ISS U E : TU T/005/1.0
Tutorial 2 : ITU controlled LED flash
The second tutorial for the SH evaluation board uses an ITU interrupt for timed LED flashing. Not only
function ality of the progr am with respect to the SH chip should be noted on but also the basic method of using
interrupts in the SH/EVB environment.
As men tion ed ear lier, in the tutorial over view, to use in terr upts with in th e EVB system it is necessa r y to cr eat e
entries in the vector table. The vector table consists of a number of function pointers, or more simply addresses,
to load the progr am counter for execution of the ISR. An extra point to note for the purposes of th e EVB on ly,
is that it is necessary to alter the vector base register (VBR). The reasoning beh ind this is that on an exception
(interrupt or reset) the SH CPU will access an address between 00000 and 255H for the pertinent exception
handler address. This mechanism is fine for a normal application where the vector table is stored in ROM
along with the execution code. However, for the purposes of the EVB our exception table can only reside in
the user RAM area which has addresses A000000 to A010000, thus an offset must be made of A002000 to
access vectors (A000000 to A001300 is taken by monitor data). This can made by alterin g within th e start-up
code the VBR to show the correct offset for all other exceptions except reset which does not use the VBR offset.
Apart from making the necessary changes to the vector table this tutorial has the following functional
requirements.
1. Write initialisation code to access port B pin 15 as the control line for the LED.
2. Write initialisation code for the ITU timing unit to enable an interrupt controlled LED flash.
3. Provide an array of integer values to be used as count values to provide a decreasing cadence in the LED
flash. This array can be the same as that used in tutorial 1.
4. Enable the LED flash and ensure ITU loads with correct frequency value and the program terminates
correctly with green LED still on.
Before examining the tutorial work the following notes on the operation of the ITU should be remembered.
1. ITU channel 0 to be used
2. Operation of counter should be as an up counter.
3. GRA compare match should trigger the interrupt to CPU.
4. After toggling the LED the ITU compare register should be reloaded with new count value and
then ITU enabled again.
5. The ITU unit should be completely disabled after the final LED flash.
Registers required to be set-up are :
1. TCNT0 : Timer counter cleared for initialisation
2. GRA0 : General reg A for channel 0 used as output compare - set with delay val.
3. TCR0 : Timer control reg - TCNT cleared by GRA, Internal clock /8
4. TIOR0 : Timer I/O control - No output from GRA match
5. TSR0 : Timer status register - Clear overflow, GRB and GRA matches
6. TIER0 : Timer interrupt enable - Enable channel 0 only.
7. IPRC : Interrupt priority reg C - ITU mid priority
8. TSTR : Timer start register - enable only TCNT0
The final point to n ote about this tutorial is that uses the inline function set_interr upt_mask (set_imask). This
function can set the four I bits to provide an interrupt mask level from 0 to 15 and thus only enable certain
pri ori ty inter rupts. T he ITU in t errupt should be made a mid-pr i ori ty interrupt a nd t hus the i nter rupt ma sk l evel
should be se accordingly, value of 7 is suitable.
Application code is shown in ANSWERS/SOL2 along with the necessary link and build files.
The same tutorial pr ocedure as tutor ial 1 should be utilised although tr y settin g a breakpoin t in th e ISR to trace
correct action of SH EVB.
Again the SH can be benchmarked by enabling the code to run in on-chip RAM, as shown in tutorial1.