1
Features
• 12 parallel channels, total 32.6 Gbps capacity
• Data rate up to 2.72 Gbps per channel
• 850 nm VCSEL array
• Data I/O is CML compatible with DC blocking
capacitors
• Link reach 300 m with 50/125 µm 500 MHz.km
fiber at 2.5 Gbps
• Channel BER better than 10-12
• Industry standard MPO/MTP ribbon fiber
connector interface
• Pluggable MegArray® ball grid array connector
• Optionally available with EMI shield and external
heat sink
• Laser class 1M IEC 60825-1:2001 compliant
• Power supply 3.3 V
• Compatible with industry MSA
Applications
• High-speed interconnects within and between
switches, routers and transport equipment
• Proprietary backplanes
• Low cost SONET/SDH VSR (Very Short Reach)
OC-192/STM64 connections
• InfiniBand® connections
• Interconnects rack-to-rack, shelf-to-shelf, board-
to-board, board-to-optical backplane
Description
The ZL60101 and ZL60102 together make a very high
speed transmitter/receiver pair for parallel fiber
applications.
The transmitter module converts parallel electrical input
signals via a laser driver and a VCSEL array into
parallel optical output signals at a wavelength of
850nm.
The receiver module converts parallel optical input
signals via a PIN photodiode array and a
transimpedance and limiting amplifier into electrical
output signals.
The modules are pluggable each fitted with an industry-
standard MegArray® BGA connector. This provides
ease of assembly on the host board and enables
provisioning of bandwidth on demand.
Issue 1.0 November 2002
Ordering Information
ZL60101/MJD Parallel Fiber Transmitter
ZL60102/MJD Parallel Fiber Receiver
Options
ZL6010*/MKD Module with EMI shield
ZL6010*/MLD Module with external heat sink
ZL6010*/MMD Module with external heat sink
and EMI shield
ZL60101 TX / ZL60102 RX
12 x 2.7 Gbps Parallel Fiber Optic Link
Transmitter and Receiver
Data Sheet
Data Sheet ZL60101 TX / ZL60102 RX
2Zarlink Semiconductor Inc.
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Transmitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Transmitter Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Transmitter Control and Status Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Transmitter Pinout Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Transmitter Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Receiver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Receiver Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Receiver Control and Status Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Receiver Pinout Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Receiver Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Circuit Board Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Heading Frontplate for Panel Accessed Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Regulatory Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Eye safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrostatic discharge immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electromagnetic interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Handling instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Cleaning the optical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ESD handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Link Reach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Link Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical Interface - Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data Sheet ZL60101 TX / ZL60102 RX
3Zarlink Semiconductor Inc.
Absolute Maximum Ratings
Not necessarily applied together. Exceeding these values may cause permanent damage. Functional operation
under these conditions is not implied.
Recommended Operating Conditions
These parameters apply both to the transmitter and the receiver.
Figure 1 - Recommended power supply filter
Table 1 - Absolute Maximum Ratings
Parameter Symbol Min Max Unit
Supply voltage VCC -0.3 4.0 V
Differential input voltage amplitude1
1. Differential input voltage amplitude is defined as ∆V = DIN+ − DIN-.
∆V1.2V
Voltage on any pin VPIN -0.3 VCC + 0.3 V
Relative humidity (non-condensing) MOS 595%
Storage temperature TSTG -40 100 °C
ESD resistance VESD ±1 kV
Table 2 - Recommended Operating Conditions
Parameter Symbol Min Max Unit
Power supply voltage VCC 3.135 3.465 V
Operating case temperature TCASE 080°C
Signaling rate (per channel)1
1. Data patterns are to have maximum run lengths and DC balance shifts no worse than that of a Pseudo Random Bit Sequence of
length 223-1 (PRBS-23). Information on lower bit rates is available on request.
fD1.0 2.72 Gbps
Link distance2
2. For maximum distance, see Table 19.
LD 2 m
Data I/O DC blocking capacitors3
3. For AC-coupling, DC blocking capacitors external to the module with a minimum value of 100 nF is recommended.
CBLK 100 nF
Power supply noise4
4. Power supply noise is defined at the supply side of the recommended filter for all VCC supplies over the frequency range of 500 Hz
to 2720 MHz with the recommended power supply filter in place.
VNPS 200 mVp-p
Host
Vcc
R1 100
Ω
C1
10
µ
F
C2
10
µ
F
L1 1
µ
H
R2 1.0 k
Ω
C3
0.1
µ
F
C4
0.1
µ
F
L2 6.8 nH
Module
Vcc
ZL60101 TX / ZL60102 RX Data Sheet
4Zarlink Semiconductor Inc.
Transmitter Specifications
All parameters below require operating conditions according to Table 2.
Table 3 - Transmitter optical and electrical specifications
Parameter Symbol Min Max Unit
Optical Parameters
Launch power (50/125 µm MMF)1
1. The output optical power is compliant with IEC 60825-1 Amendment 2, Class 1M Accessible Emission Limits.
POUT -7.5 -2 dBm
Extinguished output power POFF -30 dBm
Extinction ratio2
2. The extinction ratio is measured at 622 Mbps.
ER 7 dB
Optical modulation amplitude3
3. Informative. Corresponds to POUT = -7.5 dBm and ER = 7 dB.
OMA 0.24 mW
Center wavelength λC830 860 nm
Spectral width4
4. Spectral width is measured as defined in EIA/TIA-455-127 Spectral Characterization of Multimode Laser Diodes.
∆λ 0.85 nmrms
Relative intensity noise OMA RIN12OMA -116 dB/Hz
Optical output rise time (20 - 80%) tRO 150 ps
Optical output fall time (20 - 80%) tFO 150 ps
Total jitter contributed (peak to peak)5
5. Total jitter equals TP1 to TP2 as defined in IEEE 802.3 clauses 38.2 and 38.6 (Gigabit Ethernet).
TJ 120 ps
Deterministic jitter contributed (peak to peak) DJ 50 ps
Channel to channel skew6
6. Channel skew is defined for the condition of equal amplitude, zero ps skew signals applied to the transmitter inputs.
tSK 100 ps
Electrical Parameters
Power dissipation PD1.5 W
Supply current ICC 450 mA
Differential input voltage amplitude (peak to peak)7
7. Differential input voltage is defined as the peak to peak value of the differential voltage between DIN+ and DIN-. Data inputs are
CML compatible.
∆VIN 200 1600 mVp-p
Differential input impedance8
8. Differential input impedance is measured between DIN+ and DIN-.
ZIN 80 120 Ω
Electrical input rise time (20 - 80%) tRE 160 ps
Electrical input fall time (20 - 80%) tFE 160 ps
Data Sheet ZL60101 TX / ZL60102 RX
5Zarlink Semiconductor Inc.
Figure 2 - Transmitter block diagram
Figure 3 - Differential CML input equivalent circuit
Table 4 - Transmitter optical channel assignment
Front view - MTP key up
Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0
Host circuit board
VCSEL Driver Controller
VCSEL
Driver
VCSEL
Array
FAULTTx_ENTx_DISV
CC
V
EE
RESET
DIN0+
DIN0-
DIN11+
DIN11-
0
1
2
3
4
5
6
7
8
9
10
11
50Ω
50Ω
13k
Ω
11k
Ω
V
EE
V
CC
DIN+
DIN-
ZL60101 TX / ZL60102 RX Data Sheet
6Zarlink Semiconductor Inc.
Transmitter Control and Status Signals
The following table shows the timing relationships of the status and control signals of the pluggable optical
transmitter.
Table 5 - Transmitter control and status signals
Parameter Symbol Min Typ Max Unit
Control input voltage high1
1. Applies to control signals RESET, Tx_DIS and Tx_EN.
VIH 2.1 V
Control input voltage low VIL 0.62 V
Control pull-up resistor2
2. Applies to control signals RESET and Tx_EN. Internal pull-up resistor.
RPU1 10 kΩ
Control pull-down resistor3
3. Applies to control signal Tx_DIS. Internal pull-down resistor.
RPD 10 kΩ
Status output voltage low4, 5
4. Applies to status signal FAULT. Internal pull-up to VCC.
5. With status output sink current max. 2 mA.
VOL 0.4 V
Status pull-up resistor4RPU2 20 100 kΩ
FAULT assert time TFA 100 µs
FAULT lasers off TFD 100 µs
RESET duration TTDD 10 µs
RESET assert time TOFF 510 µs
RESET de-assert time TON 100 ms
Tx_EN assert time TTEN 1ms
Tx_EN de-assert time TTD 510 µs
Tx_DIS assert time TTD 510 µs
Tx_DIS de-assert time TTEN 1ms
Data Sheet ZL60101 TX / ZL60102 RX
7Zarlink Semiconductor Inc.
Transmitter Control and Status Timing Diagrams
The following figures show the timing relationships of the status and control signals of the pluggable optical
transmitter.
Figure 4 - Transmitter power-up sequence
Figure 5 - Transmitter fault signal timing diagram
RESET: floating or high
Transmitter Not Ready Normal operation
Vcc
T
TEN
Tx Output [0:11]
Data [0:11]
No Fault Fault
FAULT T
FA
T
FD
Tx Output [0:11]
Data [0:11]
ZL60101 TX / ZL60102 RX Data Sheet
8Zarlink Semiconductor Inc.
Figure 6 - Transmitter reset signal timing diagram
Figure 7 - Transmitter enable and disable timing diagram
Table 6 - Truth table for transmitter operation (Pre-condition: RESET floating or HIGH)
Tx_DIS High Tx_DIS Low
Tx_EN High Transmitter disabled Normal operation
Tx_EN Low Transmitter disabled Transmitter disabled
Transmitter Not Ready Normal operation
FAULT
T
ON
Tx Output [0:11]
Data [0:11]
RESET
T
TDD
Tx_EN
Data [0:11]
Lasers
off
T
TD
Normal operation Tx Off
Tx_DIS
Lasers
off
Data [0:11]
T
TD
Normal operation Tx Off
Data [0:11]
Tx_EN
T
TEN
Normal operationTransmitter Not Ready
Data Sheet ZL60101 TX / ZL60102 RX
9Zarlink Semiconductor Inc.
Transmitter Pinout Assignments
(10x10 array, 1.27 mm pitch)
Transmitter Pin Description
Table 7 - Transmitter host circuit board layout (Top view, toward MPO/MTP connector end)
KJHGFEDCBA
1NICNICNICV
EE VEE VEE VEE VEE VEE NIC
2NICNICNICV
EE VEE DIN5+ VEE VEE DIN8+ VEE
3NIC VCC VCC VEE DIN4+ DIN5- VEE DIN7+ DIN8- VEE
4NIC VCC VCC DIN3+ DIN4- VEE DIN6+ DIN7- VEE NIC
5NIC VCC VCC DIN3- VEE DIN2+ DIN6- VEE DIN9- VEE
6NIC VCC VCC VEE DIN1+ DIN2- VEE DIN10- DIN9+ VEE
7NIC NIC NIC DIN0+ DIN1- VEE DIN11- DIN10+ VEE NIC
8DNC RESET FAULT DIN0- VEE VEE DIN11+ VEE VEE NIC
9DNC Tx_EN Tx_DIS VEE VEE VEE VEE VEE VEE NIC
10 DNC DNC DNC DNC DNC DNC DNC DNC DNC DNC
Table 8 - Transmitter pin descriptions
Signal Name Type Description Comments
DIN[0:11] +/- Data input Transmitter data in, channel 0 to 11 Internal differential termination at 100 Ω.
VCC Transmitter power supply rail
VEE Transmitter signal common. All
transmitter voltages are referenced
to this potential unless otherwise
stated.
Directly connect these pads to the PC
board transmitter signal ground plane.
Tx_EN Control
input
Transmitter enable.
HIGH: normal operation
LOW: disable transmitter
Active high, internal pull-up. See
Table 6.
Tx_DIS Control
input
Transmitter disable.
HIGH: disable transmitter
LOW: normal operation
Active high, internal pull-down. See
Table 6.
FAULT Status
output
Transmitter fault.
HIGH: normal operation
LOW: laser fault detected on at least
one channel
When active, all channels are disabled.
Clear by reset signal. Internal pull-up.
RESET Control
input
Transmitter reset.
HIGH: normal operation
LOW:reset to clear fault signal
Internal pull-up.
DNC Do not connect to any potential,
including ground.
NIC No internal connection.
ZL60101 TX / ZL60102 RX Data Sheet
10 Zarlink Semiconductor Inc.
Receiver Specifications
All parameters below require operating conditions according to Table 2 and a termination load of 100 Ω differential
at the electrical output.
Table 9 - Receiver optical and electrical parameters
Parameter Symbol Min Max Unit
Optical Parameters
Input optical power1
1. Receive power for a channel is measured for a BER of 10-12 and worst case extinction ratio. PIN (Min) is measured using a fast
rise/fall time source with low RIN and adjacent channel(s) operating with with incident power of 6 dB above PIN (Min).
PIN -16 -2 dBm
Center wavelength λC830 860 nm
Return loss2
2. Return loss is measured as defined in TIA/EIA-455-107A Determination of Component Reflectance or Link/System Return Loss Us-
ing a Loss Test Set.
RL 12 dB
Total jitter contributed (peak to peak)3
3. Total jitter equals TP3 to TP4 as defined in IEEE 802.3 clauses 38.2 and 38.6 (Gigabit Ethernet).
TJ 120 ps
Deterministic jitter contributed (peak to peak) DJ 50 ps
Stressed receiver sensitivity4
4. The stressed receiver sensitivity is measured using PRBS 223-1 pattern, 2.7 dB inter-symbol interference, ISI (Min), 30 ps duty cycle
dependent deterministic jitter, DCD DJ (Min), and 7 dB extinction ratio, ER (Min) (ER penalty = 1.76 dB). All channels not under test
are receiving signals with an average input power of 6 dB above PIN (Min).
PSS -11.3 dBm
Channel to channel skew5
5. Channel skew is defined for the condition of equal amplitude, zero ps skew signals applied to the receiver inputs.
tSK 100 ps
Signal detect assert PSA -17 dBm
Signal detect de-assert PSD -27 dBm
Electrical Parameters
Power dissipation PD1.5 W
Supply current ICC 450 mA
Differential output voltage amplitude (peak to peak)6
6. Differential output voltage is defined as the peak to peak value of the differential voltage between DOUT+ and DOUT- and measured
with a 100 Ω differential load connected between DOUT+ and DOUT-. Data outputs are CML compatible.
∆VOUT 500 800 mVp-p
Output differential load impedance7
7. See Figure 19.
ZL80 120 Ω
Stressed receiver eye opening8
8. The stressed receiver eye opening represents the eye at TP4 as defined in IEEE 802.3 clauses 38.2 and 38.6 (Gigabit Ethernet).
The stressed receiver eye opening is measured using PRBS 223-1 pattern, 2.7 dB ISI min, 30 ps DCD DJ min, 7 dB ER min and an
average input power of -10.8 dBm (0.5 dB above minimum stressed receiver sensitivity as defined in IEEE 802.3 clause 38.6). All chan-
nels not under test are receiving signals with an average input power of 6 dB above PIN (Min).
PSE 0.3 UI
Electrical output rise time (20 - 80 %) tRE 150 ps
Electrical output fall time (20 - 80 %) tFE 150 ps
Data Sheet ZL60101 TX / ZL60102 RX
11Zarlink Semiconductor Inc.
Figure 8 - Receiver block diagram
Receiver Control and Status Signals
The following table shows the timing relationships of the status and control signals of the pluggable optical receiver.
Table 10 - Receiver optical channel assignment
Front view - MTP key up
Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0
Host circuit board
Table 11 - Receiver control and status signals
Parameter Symbol Min Typ Max Unit
Control input voltage high1
1. Applies to control signals Rx_EN, SQ_EN.
VIH 2.0 V
Control input voltage low1VIL 0.9 V
Control input pull-up current1IIN10 100 µA
Status output voltage low2, 3
2. Applies to status signal Rx_SD. Internal pull-up to VCC.
3. With status output sink current max 2 mA.
VOL 0.4 V
Status output pull-up resistor2RPU 3.25 kΩ
Receiver signal detect assert time TSD 50 200 µs
Receiver signal detect de-assert time TLOS 50 200 µs
Receiver enable assert time TRXEN 33 ms
Receiver enable de-assert time TRXD 5µs
PIN
Array
DOUT0+
DOUT0-
V
CC
V
EE
Trans-
Impedance
and
Limiting
Amplifier
SQ_ENRx_EN Rx_SD
0
1
2
3
4
5
6
7
8
9
10
11 DOUT11+
DOUT11-
ZL60101 TX / ZL60102 RX Data Sheet
12 Zarlink Semiconductor Inc.
Receiver Control and Status Timing Diagrams
The following figures show the timing relationships of the status and control signals of the pluggable optical
receiver.
Figure 9 - Receiver enable signal timing diagram
Figure 10 - Receiver signal detect timing diagram
Normal Operation Rx Off
Rx_EN
T
RXD
I
CC
Signal No Signal
Rx_SD
T
LOS
Data Sheet ZL60101 TX / ZL60102 RX
13Zarlink Semiconductor Inc.
Receiver Pinout Assignments
(10x10 array, 1.27 mm pitch)
Receiver Pin Description
Table 12 - Receiver pinout assignments (Top view, toward MPO/MTP connector end)
KJHGFEDCBA
1DNC NIC NIC VEE VEE VEE VEE VEE VEE NIC
2DNC NIC NIC VEE VEE DOUT5- VEE VEE DOUT8- VEE
3NIC VCC VCC VEE DOUT4- DOUT5+ VEE DOUT7- DOUT8+ VEE
4NIC VCC VCC DOUT3- DOUT4+ VEE DOUT6- DOUT7+ VEE NIC
5NIC VCC VCC DOUT3+ VEE DOUT2- DOUT6+ VEE DOUT9+ VEE
6NIC VCC VCC VEE DOUT1- DOUT2+ VEE DOUT10+ DOUT9- VEE
7NIC NIC Rx_SD DOUT0- DOUT1+ VEE DOUT11+ DOUT10- VEE NIC
8DNC NIC NIC DOUT0+ VEE VEE DOUT11- VEE VEE NIC
9DNC Rx_EN NIC VEE VEE VEE VEE VEE VEE NIC
10 SQ_EN DNC DNC DNC DNC DNC DNC DNC DNC DNC
Table 13 - Receiver pin descriptions
Signal Name Type Description Comments
DOUT[0:11] +/- Data
output
Receiver data out, channel 0 to 11.
VCC Receiver power supply rail.
VEE Receiver signal common. All receiver voltages
are referenced to this potential unless
otherwise stated.
Directly connect these pads to
the PC board transmitter
signal ground plane.
Rx_EN Control
input
Receiver enable.
HIGH: normal operation
LOW: disable receiver
Internal pull-up.
Rx_SD Status
output
Receiver signal detect.
HIGH: valid optical input on all channels
LOW: loss of signal on at least one channel
Internal pull-up.
SQ_EN Control
input
Squelch enable.
HIGH: squelch function enabled. Data OUT is
squelched on any channels that have loss of
signal
LOW: squelch function disabled
Internal pull-up.
DNC Do not connect to any potential, including
ground.
NIC No internal connection.
ZL60101 TX / ZL60102 RX Data Sheet
14 Zarlink Semiconductor Inc.
Package Outline
Tolerancing per ASME Y14.5M-1994. All dimensions are in millimeters.
Figure 11 - Module layout (MJD option)
Data Sheet ZL60101 TX / ZL60102 RX
15Zarlink Semiconductor Inc.
Dimensions with reference designators ending in "2" (e.g., C2) are defined in Table 17.
Table 14 - Module dimensions (MJD option)
Key Dimension
[mm] Comments
A1 36.87 Length of module body, less optical receptacle assembly
B1 17.50 Width of module body
C1 14.40 Width of optical receptacle assembly
D1 4.30 Height of bottom of optical receptacle assembly
E1 12.23 Height of top of optical receptacle assembly
F1 7.48 Length of optical receptacle assembly
G1 12.50 Height of top of module
H1 3.26 Clearance over host board at rear of module
J1 0.98 Height of standoff boss on front posts
K1 0.76 Height of front posts
L1 31.75 Distance from rear post to front plane, less optical receptacle assembly
M1 30.23 Distance from front to rear posts
N1 13.72 Distance between posts, side to side
P1 1.145 Location of BGA pin A1
R1 19.43 Location of BGA pin A1, transmitter
S1 Ø3.63 Diameter of rear posts
T1 2-56 UNC-2B Thread dimension, minimum 3.50 mm deep
U1 16.89 Location of BGA pin A1, receiver
V1 Ø1.30 Diameter of front posts
W1 Ø2.50 Diameter of standoff boss on front post
X1 7.55 Height of back of module without heat sink
Y1 27.64 Length of external heat sink body
ZL60101 TX / ZL60102 RX Data Sheet
16 Zarlink Semiconductor Inc.
Figure 12 - Module layout with EMI shield (MKD option)
Table 15 - Module dimensions with EMI shield (MKD option)
Key Dimension
[mm] Comments
Min Max
AA1 8.27 Distance from hostboard to centre of EMI shield
AB1 9.10 11.10 Height of EMI shield with bezel in A2 location
AC1 15.50 17.50 Width of EMI shield with bezel in A2 location
Data Sheet ZL60101 TX / ZL60102 RX
17Zarlink Semiconductor Inc.
Figure 13 - Module layout with external heat sink (MLD option)
Table 16 - Module dimensions with external heat sink (MLD option)
Key Dimension
[mm] Comments
Z1 15.19 Height of top of module, including external heat sink
AD1 24.00 Length of external heat sink
AE1 17.45 Width of external heat sink
ZL60101 TX / ZL60102 RX Data Sheet
18 Zarlink Semiconductor Inc.
Circuit Board Footprint
Tolerancing per ASME Y14.5M-1994. All dimensions are in millimeters.
Figure 14 - Host circuit board footprint layout
Dimensions with reference designators ending in "1" (e.g., B1, C1) are defined in Table 14.
Table 17 - Host circuit board footprint dimensions
Key Dimension
[mm]
Tolerance
[mm] Comments
A2 35.31 ±0.75 Distance from rear post to inside surface of bezel
B2 5.15 ±0.25 Distance from rear post to rear of module keep-out area
C2 Ø0.58 ±0.05 Diameter of pad in BGA pattern
D2 Ø4.50 MIN Diameter of keep-out pad for rear posts: two rear and one front
E2 Ø2.69 ±0.12 Diameter of hole for mounting screws: two rear and one front
F2 Ø1.70 ±0.12 Diameter of hole for front posts
G2 Ø3.30 MIN Diameter of keep-out pad for front post
Data Sheet ZL60101 TX / ZL60102 RX
19Zarlink Semiconductor Inc.
Heading Frontplate for Panel Accessed Modules
Tolerancing per ASME Y14.5M-1994. All dimensions are in millimeters.
Figure 15 - Host frontplate layout
Dimensions with reference designators ending in "2" (e.g., A2) are defined in Table 17.
Table 18 - Host frontplate dimensions
Key Dimension
[mm]
Tolerance
[mm] Comments
A3 18.42 MIN Centre-to-centre spacing for adjacent modules
B3 16.50 ±0.20 Width of opening in frontplate
C3 0.50 MAX Corner radius of opening in frontplate
D3 3.20 ±0.20 Height from host PCB to bottom of frontplate opening
E3 13.33 ±0.20 Height from host PCB to top of frontplate opening
ZL60101 TX / ZL60102 RX Data Sheet
20 Zarlink Semiconductor Inc.
Thermal Characteristics
There are three options for heat sinks depending on the cooling needs. They are
1. Direct application without any attached external heat sink
2. Use the generic heat sink specified in this data sheet
3. Use a customer designed external heat sink
In Figure 16 and Figure 17, the temperature rise and thermal resistance as a function of air velocity (free air velocity
at the top of the module) is shown for option 1 and 2. The thermal resistance is defined as the temperature
difference between the case temperature and ambient flowing air divided by the total heat dissipation of the
module.
Improved thermal properties can be achieved by using a larger heat sink especially if more height is available
(option 3). For this option, a more detailed discussion with Zarlink is recommended regarding heat sink design
attachment materials.
Figure 16 - Temperature difference between ambient flowing air and case at a heat dissipation of
1.5 W
Figure 17 - Thermal resistance, as a function of air velocity (the airflow is along the shortest side
of the module). For any other orientation, the thermal resistance is 75-100% of the values shown
above
Temperature rise at 1.5W
(Free stream air velocity)
0
4
8
12
16
20
01234
Air velocity (m/s)
Temperature rise (K)
Option ZL6010*/ML
Option ZL6010*/MJ
Thermal resistance to air
(Free stream air velocity)
0
5
10
15
01234
Air velocity (m/s)
Thermal resistance (K/W)
Option ZL6010*/ML
Option ZL6010*/MJ
Data Sheet ZL60101 TX / ZL60102 RX
21Zarlink Semiconductor Inc.
Regulatory Compliance
Eye safety
The maximum optical output power is specified to comply with Class 1M in accordance with IEC 60825−1:2001. In
addition the transmitter complies with FDA performance standards for laser products except for deviations pursuant
to Laser Notice No.50, dated July 26, 2001. No maintenance or service of the product may be performed.
Electrostatic discharge
The module is classified as Class 1 (> 1000 Volts) according to MIL−STD−883, test method 3015.7, with regards to
the electrical pads.
Electrostatic discharge immunity
The part withstand a 15 kV (air discharge) and 8 kV (contact discharge) either indirect or directly to receptacle;
tested according to IEC 61000−4−2, while in operation without addition of bit errors.
Electromagnetic interference
Emission
The electromagnetic emission is tested in front of the module (module fitted with EMI shield), with the module
mounted in a frontplate cutout as defined in Figure 15. The part is tested with FCC Part 15, 30 − 1000 MHz and
1 GHz to 5th harmonic of the highest fundamental frequency (6.75 GHz), and is specified to be Class B with > 6 dB
margin.
Immunity
The electromagnetic immunity is tested without a front panel or enclosure. The module specification is maintained
with an applied field of 10 V/m for frequencies between 10 kHz and 10 GHz, according to IEC 61000−4−3 and
GR−1089−CORE.
Handling instructions
Cleaning the optical interface
A protective connector plug is supplied with each module. This plug should remain in place prior to use, and be re-
attached whenever a fiber cable is not inserted. This will keep the optical interface free from dust or other
contaminants, which may potentially degrade the optical signal. Before reattaching the connector plug to the
module, visually inspect the plug and remove any contamination. If the optical interface becomes contaminated, it
can be cleaned with high-pressure nitrogen.
The use of fluids, or physical contact with the optical interface, is not advised due to potential for damage.
ESD handling
When handling the modules, precautions for ESD sensitive devices should be taken. These include use of ESD
protected work areas with wrist straps, controlled work-benches, floors etc.
ZL60101 TX / ZL60102 RX Data Sheet
22 Zarlink Semiconductor Inc.
Link Reach
The following table lists the minimum reach distance of the 12 channel pluggable optical modules for different multi-
mode fiber (MMF) types and bandwidths assuming worst case parameters. Each case allows for a maximum of
2 dB per channel connection loss for patch cables and other connectors.
Link Model Parameters
The link reaches above have been calculated using the following link model parameters and Gigabit Ethernet link
model version 2.3.5 (filename: 5pmd047.xls).
Table 19 - Link reach for different fiber types and data rates
Fiber Type
[core / cladding µm]
Modal Bandwidth
@ 850 nm
[MHz*km]
Reach Distance
@ 1 Gbps
[m]
Reach Distance
@ 2.5 Gbps
[m]
Reach Distance
@ 2.72 Gbps
[m]
62.5/125 MMF 200 350 130 110
62.5/125 or 50/125 MMF 400 650 260 220
50/125 MMF 500 750 300 270
Table 20 - Link model parameters
Parameter Symbol Value Unit
Mode partition noise k-factor k 0.3
Modal noise MN 0.3 dB
Dispersion slope parameter SO0.11 ps/nm2*km
Wavelength of zero dispersion UO1320 nm
Attenuation coefficient at 850 nm αdB 3.5 dB/km
Conversion factor C1 480 ns.MHz
Q-factor [BER 10-12] Q 7.04
TP4 eye opening 0.3 UI
DCD allocation at TP3 DCD DJ 0.08 UI
RMS baseline wander S.D. σBLW 0.025
RIN coefficient kRIN 0.70
Conversion factor c_rx 329 ns.MHz
Data Sheet ZL60101 TX / ZL60102 RX
23Zarlink Semiconductor Inc.
Electrical Interface - Application Examples
Figure 18 - Recommended differential CML input interface
Figure 19 - Recommended differential CML output interface
Z
OUT
=100
Ω
Differential
Recommended CML output
Z
0
=100
Ω
Differential Z
IN
=100
Ω
Differential
Transmitter CML input
100nF
100nF
Host PCB
Receiver CML output
Z
0
=100
Ω
Differential Z
TERM
=100
Ω
Differential
Recommended CML input
100nF
100nF
Host PCB
Z
L
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