ZL60101 TX / ZL60102 RX 12 x 2.7 Gbps Parallel Fiber Optic Link Transmitter and Receiver Data Sheet Issue 1.0 November 2002 Ordering Information ZL60101/MJD Parallel Fiber Transmitter ZL60102/MJD Parallel Fiber Receiver Options ZL6010*/MKD Module with EMI shield ZL6010*/MLD Module with external heat sink ZL6010*/MMD Module with external heat sink and EMI shield Description Features * * * * * * * * * * * * 12 parallel channels, total 32.6 Gbps capacity Data rate up to 2.72 Gbps per channel 850 nm VCSEL array Data I/O is CML compatible with DC blocking capacitors Link reach 300 m with 50/125 m 500 MHz.km fiber at 2.5 Gbps Channel BER better than 10-12 Industry standard MPO/MTP ribbon fiber connector interface Pluggable MegArray(R) ball grid array connector Optionally available with EMI shield and external heat sink Laser class 1M IEC 60825-1:2001 compliant Power supply 3.3 V Compatible with industry MSA The ZL60101 and ZL60102 together make a very high speed transmitter/receiver pair for parallel fiber applications. The transmitter module converts parallel electrical input signals via a laser driver and a VCSEL array into parallel optical output signals at a wavelength of 850nm. The receiver module converts parallel optical input signals via a PIN photodiode array and a transimpedance and limiting amplifier into electrical output signals. The modules are pluggable each fitted with an industrystandard MegArray(R) BGA connector. This provides ease of assembly on the host board and enables provisioning of bandwidth on demand. Applications * * * * * High-speed interconnects within and between switches, routers and transport equipment Proprietary backplanes Low cost SONET/SDH VSR (Very Short Reach) OC-192/STM64 connections InfiniBand(R) connections Interconnects rack-to-rack, shelf-to-shelf, boardto-board, board-to-optical backplane 1 ZL60101 TX / ZL60102 RX Data Sheet Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Transmitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Transmitter Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Transmitter Control and Status Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Transmitter Pinout Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Transmitter Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Receiver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Receiver Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Receiver Control and Status Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Receiver Pinout Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Receiver Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Circuit Board Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Heading Frontplate for Panel Accessed Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Regulatory Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Eye safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Electrostatic discharge immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Electromagnetic interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Handling instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Cleaning the optical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ESD handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Link Reach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Link Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Electrical Interface - Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Zarlink Semiconductor Inc. 2 ZL60101 TX / ZL60102 RX Data Sheet Absolute Maximum Ratings Not necessarily applied together. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Table 1 - Absolute Maximum Ratings Parameter Symbol Min Max Unit VCC -0.3 4.0 V 1.2 V Supply voltage 1 V Differential input voltage amplitude Voltage on any pin VPIN -0.3 VCC + 0.3 V Relative humidity (non-condensing) MOS 5 95 % Storage temperature TSTG -40 100 C ESD resistance VESD 1 kV 1. Differential input voltage amplitude is defined as V = DIN+ - DIN-. Recommended Operating Conditions These parameters apply both to the transmitter and the receiver. Table 2 - Recommended Operating Conditions Parameter Symbol Min Max Unit VCC 3.135 3.465 V Operating case temperature TCASE 0 80 C Signaling rate (per channel)1 fD 1.0 2.72 Gbps Link distance2 LD 2 m CBLK 100 nF Power supply voltage Data I/O DC blocking capacitors3 Power supply noise4 VNPS 200 mVp-p 1. Data patterns are to have maximum run lengths and DC balance shifts no worse than that of a Pseudo Random Bit Sequence of length 223-1 (PRBS-23). Information on lower bit rates is available on request. 2. For maximum distance, see Table 19. 3. For AC-coupling, DC blocking capacitors external to the module with a minimum value of 100 nF is recommended. 4. Power supply noise is defined at the supply side of the recommended filter for all VCC supplies over the frequency range of 500 Hz to 2720 MHz with the recommended power supply filter in place. Host Vcc C1 10 F L1 1 H L2 6.8 nH R1 100 R2 1.0 k C2 10 F C3 0.1 F Module Vcc C4 0.1 F Figure 1 - Recommended power supply filter Zarlink Semiconductor Inc. 3 ZL60101 TX / ZL60102 RX Data Sheet Transmitter Specifications All parameters below require operating conditions according to Table 2. Table 3 - Transmitter optical and electrical specifications Parameter Symbol Min Max Unit Launch power (50/125 m MMF)1 POUT -7.5 -2 dBm Extinguished output power POFF -30 dBm Optical Parameters Extinction ratio2 Optical modulation amplitude3 ER 7 dB OMA 0.24 mW C 830 860 nm 0.85 nmrms RIN12OMA -116 dB/Hz Optical output rise time (20 - 80%) tRO 150 ps Optical output fall time (20 - 80%) tFO 150 ps TJ 120 ps DJ 50 ps tSK 100 ps PD 1.5 W ICC 450 mA Center wavelength Spectral width4 Relative intensity noise OMA Total jitter contributed (peak to peak)5 Deterministic jitter contributed (peak to peak) Channel to channel skew6 Electrical Parameters Power dissipation Supply current Differential input voltage amplitude (peak to Differential input peak)7 VIN 200 1600 mVp-p ZIN 80 120 impedance8 Electrical input rise time (20 - 80%) tRE 160 ps Electrical input fall time (20 - 80%) tFE 160 ps 1. The output optical power is compliant with IEC 60825-1 Amendment 2, Class 1M Accessible Emission Limits. 2. The extinction ratio is measured at 622 Mbps. 3. Informative. Corresponds to POUT = -7.5 dBm and ER = 7 dB. 4. Spectral width is measured as defined in EIA/TIA-455-127 Spectral Characterization of Multimode Laser Diodes. 5. Total jitter equals TP1 to TP2 as defined in IEEE 802.3 clauses 38.2 and 38.6 (Gigabit Ethernet). 6. Channel skew is defined for the condition of equal amplitude, zero ps skew signals applied to the transmitter inputs. 7. Differential input voltage is defined as the peak to peak value of the differential voltage between DIN+ and DIN-. Data inputs are CML compatible. 8. Differential input impedance is measured between DIN+ and DIN-. 4 Zarlink Semiconductor Inc. ZL60101 TX / ZL60102 RX Data Sheet DIN0+ DIN0- VCSEL Driver 0 1 2 3 4 5 6 7 8 9 10 11 VCSEL Array DIN11+ DIN11- VCSEL Driver Controller VCC VEE RESET Tx_DIS Tx_EN FAULT Figure 2 - Transmitter block diagram Table 4 - Transmitter optical channel assignment Front view - MTP key up Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0 Host circuit board DIN+ 50 50 DIN- VCC 13k 11k VEE Figure 3 - Differential CML input equivalent circuit Zarlink Semiconductor Inc. 5 ZL60101 TX / ZL60102 RX Data Sheet Transmitter Control and Status Signals The following table shows the timing relationships of the status and control signals of the pluggable optical transmitter. Table 5 - Transmitter control and status signals Parameter Symbol Min Control input voltage high1 VIH 2.1 Control input voltage low VIL Control pull-up resistor 2 Control pull-down resistor Status output voltage 3 low4, 5 4 Status pull-up resistor Max Unit V 0.62 V RPU1 10 k RPD 10 k VOL RPU2 20 0.4 V 100 k FAULT assert time TFA 100 s FAULT lasers off TFD 100 s RESET duration TTDD RESET assert time TOFF RESET de-assert time s 10 10 s TON 100 ms Tx_EN assert time TTEN 1 ms Tx_EN de-assert time TTD 5 10 s Tx_DIS assert time TTD 5 10 s Tx_DIS de-assert time TTEN 1 ms 1. Applies to control signals RESET, Tx_DIS and Tx_EN. 2. Applies to control signals RESET and Tx_EN. Internal pull-up resistor. 3. Applies to control signal Tx_DIS. Internal pull-down resistor. 4. Applies to status signal FAULT. Internal pull-up to VCC. 5. With status output sink current max. 2 mA. 6 Typ Zarlink Semiconductor Inc. 5 ZL60101 TX / ZL60102 RX Data Sheet Transmitter Control and Status Timing Diagrams The following figures show the timing relationships of the status and control signals of the pluggable optical transmitter. Vcc TTEN Tx Output [0:11] Data [0:11] Transmitter Not Ready Normal operation RESET: floating or high Figure 4 - Transmitter power-up sequence FAULT TFA TFD Data [0:11] Tx Output [0:11] No Fault Fault Figure 5 - Transmitter fault signal timing diagram Zarlink Semiconductor Inc. 7 ZL60101 TX / ZL60102 RX Data Sheet RESET FAULT TTDD TON Data [0:11] Tx Output [0:11] Transmitter Not Ready Normal operation Figure 6 - Transmitter reset signal timing diagram Tx_DIS Tx_EN TTD Data [0:11] Normal operation TTD Lasers off Data [0:11] Tx Off Normal operation Lasers off Tx Off Tx_EN TTEN Data [0:11] Transmitter Not Ready Normal operation Figure 7 - Transmitter enable and disable timing diagram Table 6 - Truth table for transmitter operation (Pre-condition: RESET floating or HIGH) 8 Tx_DIS High Tx_DIS Low Tx_EN High Transmitter disabled Normal operation Tx_EN Low Transmitter disabled Transmitter disabled Zarlink Semiconductor Inc. ZL60101 TX / ZL60102 RX Data Sheet Transmitter Pinout Assignments Table 7 - Transmitter host circuit board layout (Top view, toward MPO/MTP connector end) K J H G F E D C B A 1 NIC NIC NIC VEE VEE VEE VEE VEE VEE NIC 2 NIC NIC NIC VEE VEE DIN5+ VEE VEE DIN8+ VEE 3 NIC VCC VCC VEE DIN4+ DIN5- VEE DIN7+ DIN8- VEE 4 NIC VCC VCC DIN3+ DIN4- VEE DIN6+ DIN7- VEE NIC 5 NIC VCC VCC DIN3- VEE DIN2+ DIN6- VEE DIN9- VEE 6 NIC VCC VCC VEE DIN1+ DIN2- VEE DIN10- DIN9+ VEE 7 NIC NIC NIC DIN0+ DIN1- VEE DIN11- DIN10+ VEE NIC 8 DNC RESET FAULT DIN0- VEE VEE DIN11+ VEE VEE NIC 9 DNC Tx_EN Tx_DIS VEE VEE VEE VEE VEE VEE NIC 10 DNC DNC DNC DNC DNC DNC DNC DNC DNC DNC (10x10 array, 1.27 mm pitch) Transmitter Pin Description Table 8 - Transmitter pin descriptions Signal Name Type Description Comments DIN[0:11] +/- Data input Transmitter data in, channel 0 to 11 Internal differential termination at 100 . VCC Transmitter power supply rail VEE Transmitter signal common. All transmitter voltages are referenced to this potential unless otherwise stated. Directly connect these pads to the PC board transmitter signal ground plane. Tx_EN Control input Transmitter enable. HIGH: normal operation LOW: disable transmitter Active high, internal pull-up. See Table 6. Tx_DIS Control input Transmitter disable. HIGH: disable transmitter LOW: normal operation Active high, internal pull-down. See Table 6. FAULT Status output Transmitter fault. HIGH: normal operation LOW: laser fault detected on at least one channel When active, all channels are disabled. Clear by reset signal. Internal pull-up. RESET Control input Transmitter reset. HIGH: normal operation LOW:reset to clear fault signal Internal pull-up. DNC Do not connect to any potential, including ground. NIC No internal connection. Zarlink Semiconductor Inc. 9 ZL60101 TX / ZL60102 RX Data Sheet Receiver Specifications All parameters below require operating conditions according to Table 2 and a termination load of 100 differential at the electrical output. Table 9 - Receiver optical and electrical parameters Parameter Symbol Min Max Unit Input optical power PIN -16 -2 dBm Center wavelength C 830 860 nm RL 12 Optical Parameters 1 2 Return loss Total jitter contributed (peak to peak)3 dB TJ 120 ps DJ 50 ps PSS -11.3 dBm tSK 100 ps Signal detect assert PSA -17 dBm Signal detect de-assert PSD Deterministic jitter contributed (peak to peak) 4 Stressed receiver sensitivity skew5 Channel to channel -27 dBm Electrical Parameters Power dissipation Supply current Differential output voltage amplitude (peak to Output differential load Stressed receiver eye peak)6 PD 1.5 W ICC 450 mA VOUT 500 800 mVp-p ZL 80 120 PSE 0.3 impedance7 opening8 Electrical output rise time (20 - 80 %) Electrical output fall time (20 - 80 %) 10-12 UI tRE 150 ps tFE 150 ps 1. Receive power for a channel is measured for a BER of and worst case extinction ratio. PIN (Min) is measured using a fast rise/fall time source with low RIN and adjacent channel(s) operating with with incident power of 6 dB above PIN (Min). 2. Return loss is measured as defined in TIA/EIA-455-107A Determination of Component Reflectance or Link/System Return Loss Using a Loss Test Set. 3. Total jitter equals TP3 to TP4 as defined in IEEE 802.3 clauses 38.2 and 38.6 (Gigabit Ethernet). 4. The stressed receiver sensitivity is measured using PRBS 223-1 pattern, 2.7 dB inter-symbol interference, ISI (Min), 30 ps duty cycle dependent deterministic jitter, DCD DJ (Min), and 7 dB extinction ratio, ER (Min) (ER penalty = 1.76 dB). All channels not under test are receiving signals with an average input power of 6 dB above PIN (Min). 5. Channel skew is defined for the condition of equal amplitude, zero ps skew signals applied to the receiver inputs. 6. Differential output voltage is defined as the peak to peak value of the differential voltage between DOUT+ and DOUT- and measured with a 100 differential load connected between DOUT+ and DOUT-. Data outputs are CML compatible. 7. See Figure 19. 8. The stressed receiver eye opening represents the eye at TP4 as defined in IEEE 802.3 clauses 38.2 and 38.6 (Gigabit Ethernet). The stressed receiver eye opening is measured using PRBS 223-1 pattern, 2.7 dB ISI min, 30 ps DCD DJ min, 7 dB ER min and an average input power of -10.8 dBm (0.5 dB above minimum stressed receiver sensitivity as defined in IEEE 802.3 clause 38.6). All channels not under test are receiving signals with an average input power of 6 dB above PIN (Min). 10 Zarlink Semiconductor Inc. ZL60101 TX / ZL60102 RX Data Sheet 0 1 2 3 4 5 6 7 8 9 10 11 DOUT0+ DOUT0- TransImpedance and Limiting Amplifier PIN Array DOUT11+ DOUT11- VCC VEE Rx_EN Rx_SD SQ_EN Figure 8 - Receiver block diagram Table 10 - Receiver optical channel assignment Front view - MTP key up Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0 Host circuit board Receiver Control and Status Signals The following table shows the timing relationships of the status and control signals of the pluggable optical receiver. Table 11 - Receiver control and status signals Parameter Control input voltage high1 Control input voltage low1 Control input pull-up current1 Min VIH 2.0 Typ IIN 10 VOL Status output voltage low resistor2 Max Unit V VIL 2, 3 Status output pull-up Symbol 0.9 V 100 A 0.4 V RPU 3.25 k Receiver signal detect assert time TSD 50 200 s Receiver signal detect de-assert time TLOS 50 200 s Receiver enable assert time TRXEN 33 ms Receiver enable de-assert time TRXD 5 s 1. Applies to control signals Rx_EN, SQ_EN. 2. Applies to status signal Rx_SD. Internal pull-up to VCC. 3. With status output sink current max 2 mA. Zarlink Semiconductor Inc. 11 ZL60101 TX / ZL60102 RX Data Sheet Receiver Control and Status Timing Diagrams The following figures show the timing relationships of the status and control signals of the pluggable optical receiver. Rx_EN TRXD ICC Normal Operation Rx Off Figure 9 - Receiver enable signal timing diagram Rx_SD TLOS Signal No Signal Figure 10 - Receiver signal detect timing diagram 12 Zarlink Semiconductor Inc. ZL60101 TX / ZL60102 RX Data Sheet Receiver Pinout Assignments Table 12 - Receiver pinout assignments (Top view, toward MPO/MTP connector end) K J H G F E D C B A 1 DNC NIC NIC VEE VEE VEE VEE VEE VEE NIC 2 DNC NIC NIC VEE VEE DOUT5- VEE VEE DOUT8- VEE 3 NIC VCC VCC VEE DOUT4- DOUT5+ VEE DOUT7- DOUT8+ VEE 4 NIC VCC VCC DOUT3- DOUT4+ VEE DOUT6- DOUT7+ VEE NIC 5 NIC VCC VCC DOUT3+ VEE DOUT2- DOUT6+ VEE DOUT9+ VEE 6 NIC VCC VCC VEE DOUT1- DOUT2+ VEE DOUT10+ DOUT9- VEE 7 NIC NIC Rx_SD DOUT0- DOUT1+ VEE DOUT11+ DOUT10- VEE NIC 8 DNC NIC NIC DOUT0+ VEE VEE DOUT11- VEE VEE NIC 9 DNC Rx_EN NIC VEE VEE VEE VEE VEE VEE NIC 10 SQ_EN DNC DNC DNC DNC DNC DNC DNC DNC DNC (10x10 array, 1.27 mm pitch) Receiver Pin Description Table 13 - Receiver pin descriptions Signal Name Type DOUT[0:11] +/- Data output Description Comments Receiver data out, channel 0 to 11. VCC Receiver power supply rail. VEE Receiver signal common. All receiver voltages are referenced to this potential unless otherwise stated. Directly connect these pads to the PC board transmitter signal ground plane. Rx_EN Control input Receiver enable. HIGH: normal operation LOW: disable receiver Internal pull-up. Rx_SD Status output Receiver signal detect. HIGH: valid optical input on all channels LOW: loss of signal on at least one channel Internal pull-up. SQ_EN Control input Squelch enable. HIGH: squelch function enabled. Data OUT is squelched on any channels that have loss of signal LOW: squelch function disabled Internal pull-up. DNC Do not connect to any potential, including ground. NIC No internal connection. Zarlink Semiconductor Inc. 13 ZL60101 TX / ZL60102 RX Data Sheet Package Outline Tolerancing per ASME Y14.5M-1994. All dimensions are in millimeters. Figure 11 - Module layout (MJD option) 14 Zarlink Semiconductor Inc. ZL60101 TX / ZL60102 RX Data Sheet Table 14 - Module dimensions (MJD option) Key Dimension [mm] A1 36.87 Length of module body, less optical receptacle assembly B1 17.50 Width of module body C1 14.40 Width of optical receptacle assembly D1 4.30 Height of bottom of optical receptacle assembly E1 12.23 Height of top of optical receptacle assembly F1 7.48 Length of optical receptacle assembly G1 12.50 Height of top of module H1 3.26 Clearance over host board at rear of module J1 0.98 Height of standoff boss on front posts K1 0.76 Height of front posts L1 31.75 Distance from rear post to front plane, less optical receptacle assembly M1 30.23 Distance from front to rear posts N1 13.72 Distance between posts, side to side P1 1.145 Location of BGA pin A1 R1 19.43 Location of BGA pin A1, transmitter S1 O3.63 Diameter of rear posts T1 2-56 UNC-2B U1 16.89 Location of BGA pin A1, receiver V1 O1.30 Diameter of front posts W1 O2.50 Diameter of standoff boss on front post X1 7.55 Height of back of module without heat sink Y1 27.64 Length of external heat sink body Comments Thread dimension, minimum 3.50 mm deep Dimensions with reference designators ending in "2" (e.g., C2) are defined in Table 17. Zarlink Semiconductor Inc. 15 ZL60101 TX / ZL60102 RX Data Sheet Figure 12 - Module layout with EMI shield (MKD option) Table 15 - Module dimensions with EMI shield (MKD option) Key Dimension [mm] Min AA1 16 Comments Max 8.27 Distance from hostboard to centre of EMI shield AB1 9.10 11.10 Height of EMI shield with bezel in A2 location AC1 15.50 17.50 Width of EMI shield with bezel in A2 location Zarlink Semiconductor Inc. ZL60101 TX / ZL60102 RX Data Sheet Figure 13 - Module layout with external heat sink (MLD option) Table 16 - Module dimensions with external heat sink (MLD option) Key Dimension [mm] Z1 15.19 Height of top of module, including external heat sink AD1 24.00 Length of external heat sink AE1 17.45 Width of external heat sink Comments Zarlink Semiconductor Inc. 17 ZL60101 TX / ZL60102 RX Data Sheet Circuit Board Footprint Tolerancing per ASME Y14.5M-1994. All dimensions are in millimeters. Figure 14 - Host circuit board footprint layout Table 17 - Host circuit board footprint dimensions Key Dimension [mm] Tolerance [mm] A2 35.31 0.75 Distance from rear post to inside surface of bezel B2 5.15 0.25 Distance from rear post to rear of module keep-out area C2 O0.58 0.05 Diameter of pad in BGA pattern D2 O4.50 MIN E2 O2.69 0.12 Diameter of hole for mounting screws: two rear and one front F2 O1.70 0.12 Diameter of hole for front posts G2 O3.30 MIN Comments Diameter of keep-out pad for rear posts: two rear and one front Diameter of keep-out pad for front post Dimensions with reference designators ending in "1" (e.g., B1, C1) are defined in Table 14. 18 Zarlink Semiconductor Inc. ZL60101 TX / ZL60102 RX Data Sheet Heading Frontplate for Panel Accessed Modules Tolerancing per ASME Y14.5M-1994. All dimensions are in millimeters. Figure 15 - Host frontplate layout Table 18 - Host frontplate dimensions Key Dimension [mm] Tolerance [mm] A3 18.42 MIN B3 16.50 0.20 Width of opening in frontplate C3 0.50 MAX Corner radius of opening in frontplate D3 3.20 0.20 Height from host PCB to bottom of frontplate opening E3 13.33 0.20 Height from host PCB to top of frontplate opening Comments Centre-to-centre spacing for adjacent modules Dimensions with reference designators ending in "2" (e.g., A2) are defined in Table 17. Zarlink Semiconductor Inc. 19 ZL60101 TX / ZL60102 RX Data Sheet Thermal Characteristics There are three options for heat sinks depending on the cooling needs. They are 1. Direct application without any attached external heat sink 2. Use the generic heat sink specified in this data sheet 3. Use a customer designed external heat sink In Figure 16 and Figure 17, the temperature rise and thermal resistance as a function of air velocity (free air velocity at the top of the module) is shown for option 1 and 2. The thermal resistance is defined as the temperature difference between the case temperature and ambient flowing air divided by the total heat dissipation of the module. Improved thermal properties can be achieved by using a larger heat sink especially if more height is available (option 3). For this option, a more detailed discussion with Zarlink is recommended regarding heat sink design attachment materials. Temperature rise at 1.5W (Free stream air velocity) Temperature rise (K) 20 16 12 Option ZL6010*/ML 8 Option ZL6010*/MJ 4 0 0 1 2 3 4 Air velocity (m/s) Figure 16 - Temperature difference between ambient flowing air and case at a heat dissipation of 1.5 W Thermal resistance to air (Free stream air velocity) Thermal resistance (K/W) 15 10 Option ZL6010*/ML Option ZL6010*/MJ 5 0 0 1 2 3 4 Air velocity (m/s) Figure 17 - Thermal resistance, as a function of air velocity (the airflow is along the shortest side of the module). For any other orientation, the thermal resistance is 75-100% of the values shown above 20 Zarlink Semiconductor Inc. ZL60101 TX / ZL60102 RX Data Sheet Regulatory Compliance Eye safety The maximum optical output power is specified to comply with Class 1M in accordance with IEC 60825-1:2001. In addition the transmitter complies with FDA performance standards for laser products except for deviations pursuant to Laser Notice No.50, dated July 26, 2001. No maintenance or service of the product may be performed. Electrostatic discharge The module is classified as Class 1 (> 1000 Volts) according to MIL-STD-883, test method 3015.7, with regards to the electrical pads. Electrostatic discharge immunity The part withstand a 15 kV (air discharge) and 8 kV (contact discharge) either indirect or directly to receptacle; tested according to IEC 61000-4-2, while in operation without addition of bit errors. Electromagnetic interference Emission The electromagnetic emission is tested in front of the module (module fitted with EMI shield), with the module mounted in a frontplate cutout as defined in Figure 15. The part is tested with FCC Part 15, 30 - 1000 MHz and 1 GHz to 5th harmonic of the highest fundamental frequency (6.75 GHz), and is specified to be Class B with > 6 dB margin. Immunity The electromagnetic immunity is tested without a front panel or enclosure. The module specification is maintained with an applied field of 10 V/m for frequencies between 10 kHz and 10 GHz, according to IEC 61000-4-3 and GR-1089-CORE. Handling instructions Cleaning the optical interface A protective connector plug is supplied with each module. This plug should remain in place prior to use, and be reattached whenever a fiber cable is not inserted. This will keep the optical interface free from dust or other contaminants, which may potentially degrade the optical signal. Before reattaching the connector plug to the module, visually inspect the plug and remove any contamination. If the optical interface becomes contaminated, it can be cleaned with high-pressure nitrogen. The use of fluids, or physical contact with the optical interface, is not advised due to potential for damage. ESD handling When handling the modules, precautions for ESD sensitive devices should be taken. These include use of ESD protected work areas with wrist straps, controlled work-benches, floors etc. Zarlink Semiconductor Inc. 21 ZL60101 TX / ZL60102 RX Data Sheet Link Reach The following table lists the minimum reach distance of the 12 channel pluggable optical modules for different multimode fiber (MMF) types and bandwidths assuming worst case parameters. Each case allows for a maximum of 2 dB per channel connection loss for patch cables and other connectors. Table 19 - Link reach for different fiber types and data rates Fiber Type Modal Bandwidth @ 850 nm [MHz*km] Reach Distance @ 1 Gbps [m] Reach Distance @ 2.5 Gbps [m] Reach Distance @ 2.72 Gbps [m] 62.5/125 MMF 200 350 130 110 62.5/125 or 50/125 MMF 400 650 260 220 50/125 MMF 500 750 300 270 [core / cladding m] Link Model Parameters The link reaches above have been calculated using the following link model parameters and Gigabit Ethernet link model version 2.3.5 (filename: 5pmd047.xls). Table 20 - Link model parameters Parameter Symbol Value k 0.3 Modal noise MN 0.3 dB Dispersion slope parameter SO 0.11 ps/nm2*km Wavelength of zero dispersion UO 1320 nm Attenuation coefficient at 850 nm dB 3.5 dB/km Conversion factor C1 480 ns.MHz Q 7.04 Mode partition noise k-factor Q-factor [BER 10-12] TP4 eye opening Unit 0.3 UI DCD DJ 0.08 UI RMS baseline wander S.D. BLW 0.025 RIN coefficient kRIN 0.70 Conversion factor c_rx 329 DCD allocation at TP3 22 Zarlink Semiconductor Inc. ns.MHz ZL60101 TX / ZL60102 RX Data Sheet Electrical Interface - Application Examples Recommended CML output Transmitter CML input Host PCB 100nF ZOUT=100 Differential ZIN=100 Differential Z0=100 Differential 100nF Figure 18 - Recommended differential CML input interface Receiver CML output Recommended CML input Host PCB 100nF Z0=100 Differential ZL ZTERM =100 Differential 100nF Figure 19 - Recommended differential CML output interface Zarlink Semiconductor Inc. 23 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE