s . PRELIMINARY intel. 27C220 2M (128K x 16) CHMOS EPROM m JEDEC Approved EPROM Pinouts wg Fast Programming 40-Pin DIP Quick-Pulse Programming 44-Pin PLCC Algorithm Programming Times As Fast As g@ Versatile EPROM Features CMOS and TTL Compatibility 15 Seconds Two Line Control a Surface Mount Packaging Available High-Performance m Complete Upgrade to Higher Densities 150 ns +10% Vcc 50 mA Icc Active Intels 27C220 is a 5V only, 2,097,152-bit Erasable Programmable Read Only Memory. Organized as 131,072 words of 16 bits each. It is pin compatible with Intels 1 Mbit 270210 and provides for a simple upgrade to 4 Mbits in the future. The 27C220 represents state-of-the-art 1 micron CMOS manufacturing technology while providing unequaled performance. Its 150 ns speed (tacc) offers no-wait-state operation with high performance CPUs in applica- tions ranging from numerical control to office automation to telecommunications. Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic dip (CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the design i is in full production, the plastic dip (PDIP) one-time programmable part provides a lower cost alternative that is well adapted for auto insertion. In addition to the JEDEC 40-pin DIP package, Intel also offers a 44-lead PLCC version of the 270220. This one-time-programmable surface mount device is ideal where board space consumption is a major concern or where surface mount manufacturing technology is being implemented across an entire production line. -- The 27C220 is equally at home in both a TTL or CMOS environment. And like Intels other high density EPROMs, the 27C220 programs quickly using Intels industry leading Quick-Pulse Programming algorithm. DATA OUTPUTS Vec or 00-015 GND o> TO, Veep o__> GE JOUTPUT ENABLE PGM CHIP ENABLE CE=| cnoaoaic [>] OUTPUT BUFFERS Y DECODER : Y-GATING Ao-Ais | ADDRESS { *' x : INPUTS | *"] 2,097,152-BIT | DECODER : CELL MATRIX Po} e 290217-1 Figure 1. Block Diagram October 1990 5-102 Order Number: 290217-005PRELIMINARY es intel. 270220 27C220 4M 1M - 1M 4M Vpp Vpp Vpp 1 : 40D Vee Veo Voc te Ce cecy2 391 Pew PGN Ai7 O15 Ow 0.5043 38E Ay NC Aw Om | Or oe 37B 0 Ais Aw | Ais Og | O49 O35 36 Ay, Aw Aw O12 f 2 one 35D Ars Ai3 Ais On On 91,47 34 An Ai2 Ai Pin Names O10 O10 ots SPA An An Os Os oye 32F 1 Ato Ato Ato Ag-A1g| ADDRESSES Os Os o,Cj10 Si Ag Ag Ag CE CHIP ENABLE Guo Ets 30) cnp GNO GND GND GND OE OUTPUT ENABLE 7 7 0, C412 29F A, Ag Ms 0-045 [OUTPUTS Os | 06 Sl 22 A, Ar | Ay IPGM [PROGRAM Os | Os ose 27M Ae | As [NC __ [NO INTERNAL CONNECT O% | % ois 26P ss As | As O3 Og o, Che 2Da, A Ay Oz Oo 0, Chi7 24D ay As Ag 0; 0; o, Chis 23a, Ap Ag Op Oo Oo Cts 2B 4, Ay |. A OE CE dE G20 ~ 2g Ao Ao 290217-2 Figure 2. DIP Pin Configurations arcozorzekxtel t tft tia dis tie dts [yt titre tay 1M (64K x 16)] O13] | O14} | Ors} | CE] | ver| | Ne | |voc] |Poml Tc [] 15] | 414 6 5 4 3 2 44 43 42 41 40 712 Ll ' 39 il Ay 3h 5 74944 [Is 38 | yar =o, [Is 37 i Ay + 0% []r 36 | Aiot 8 [| "1 44 LEAD PLCC 35 | sl leno [| 2 0.650" x 0.650" 34 | enol TOP VIEW . {NC [| 13 33 | NC} = 07 [| 14 32 | Agi | 0 [| 15 31 | a 05 [| 16 30 | Ag lo, [| 17 29 | as |= 18 49 20 21 22 23 24 #25 26 27 28 \ CIID D IIDLLLIL J, 3 |] 2 |] 1 ff J] OEP TNC] ] Ao] | Ard] Az] | As] | As PHATE TEE TE EE TT 200217-14 5-103 Figure 3. PLCC Lead Configurationintel. 270220 PRELIMINARY ABSOLUTE MAXIMUM RATINGS* Operating Temperature cect eee enone 0C to 70C(1) Temperature Under Bias ........ 42.7 10C to 80C Storage Temperature............. 65C to 125C Voltages on Any Pin (except Ag, Voc and Vpp) NOTICE; This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. * WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the with Respect toGND .........:0.6V to 6.5v(2) Operating Conditions is not recommended and ex- Voltage on Ag with tended exposure beyond the Operating Conditions Respect toGND ............. 0.6V to 13.0V(2) may affect device reliability. Vpp Supply Voltage : with Respect toGND........... 0.6V to 14V(2) Voc Supply Voltage with Respect to GND .........:0.6V to 7.0V(2) READ OPERATION DC CHARACTERISTICS Vcc = 5.0V +10% Symbol Parameter Notes Min Typ Max Unit Test Condition tu Input Load Current . 7 : 0.01 1.0 BA | Vin = OV to Voc ILo Output Leakage Current +10 pA | Vout = OV to Voc Ise Voc Standby Current 1.0 mA | CE = Vin 100 | pA | CE = Vcc +0.2V loc Voc Operating Current 3 |. 50 mA | CE = Vi . f = 5 MHz, lout = OMA Ipp Vpp Operating Current 3 10 pA | Vpp = Voc los Output Short Circuit Current] 4, 6 100 mA ViL Input Low Voltage 0.5 0.8 Vv Vin Input High Voltage 2.0 Voc + 0.5! V Vo. __| Output: Low Voltage 0.45 V lop = 2.1mA Vou Output High Voltage 2.4 V |iow = 400 pA Vpp Vpp Operating Voltage 5 Voc 0.7 Voc V NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods <20 ns. Maximum DC voltage on input/output pins is Vcc + 0.5V which, during transitions, may overshoot to Voc + 2.0V for periods <20 ns. : 3. Maximum active power usage is the sum Ipp + Icc. Maximum current is with outputs Op to O15 unloaded. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. Vpp may be connected directly to Voc, or may be one diode voltage drop below Vcc. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 6. Sampled, not 100% tested. 7. Typical limits are at Voc = 5V, Ta = 28C. 5-104intel. 370220 PRELIMINARY READ OPERATION AC CHARACTERISTICS(1) Vcc = 5.0v + 10% 27C220-200V 10 Versions(4) / Veco 10% | 27C220-150V10_ P27C220-200V10 | N27C220-200v10 | Units Symbol Parameter Notes Min _ Max. Min Max tacc Address to Output Delay 150 200 ns toe CE to Output Delay 2 150 200 ns toe OE to Output Delay 2 60 70 ns tor OE High to Output High Z 3 50 60 ns tou Output Hold from. 3 0 0 ns Addresses, CE or OE Change-Whichever is First NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE may be delayed up to tce-tog after the falling edge of CE without impact on tce. 3. Sampled, not 100% tested. 4. Model Number Prefixes: No Prefix = GERDIP, P = PDIP, N = PLCC. 5. Typical limits are for Ta = 25C and nominat supply voltages. CAPACITANCE(S) 1, = 25C, f = 1MHz Parameter Max | Unit | Conditions 4 8 = OV 8 12 Vv = 18 25 = 0V AC INPUT/OUTPUT REFERENCE WAVEFORM AC TESTING LOAD CIRCUIT . 13V 2.4 7) 20 : 1NO14 INPUT TEST POINTS OUTPUT x 0.8 _ ce <Xi 0.45 55 . & : 290217-6 DEVICE UNDER out TEST AC test inputs are driven at Vou (2.4 Viz.) for a logic 1 and + Vor, (0.45 Vit) for a logic 0. Input timing begins at Vj4 (2.0 VrTU and Vi, (0.8 V+7,). Output timing ands at Vj and Vj. Input rise and fall times (10% to 90%) < 10 ns. 290217-7 CL = 100 pF C, Includes Jig Capacitance Ri = 3.3kN 5-105PRELIMINARY YL... og face Tr" AMY intel. 276220 AC WAVEFORMS ok aK ADDRESSES scones Vi N a, Va eeoe _/ cg $ | ot tou VALIO OUTPUT 290217-8 DEVICE OPERATION The Mode Selection table lists 27C220 operating modes. Read Mode requires a single 5V power supply. All inputs, except Vcc and Vpp, and Ag during intgligent identifier Mode, are TTL or CMOS. Table 1. Mode Selection Mode Notes | CE | OF | PGM | Ao Ao Vpp | Vcc | Outputs Read 1 Vit Vig xt) x x Voc Voc Dout Output Disable Vir Vin x x xX Voc Voc High Z Standby Vin Xx X x xX Voc | Voc High Z Program 2 Vit Vin Vit X xX Vpp Vop Din Program Verify Vic Vit Vint x x Vpp Vop Dout Program Inhibit Vin x x x x Vpp Vop High Z intgligent Manufacturer Vit Vit X Vip VIL Voc Voc 0089 H Identifier Device 23 vi | Vi | x | Vio | Via | Voc | Veco | 22EEH NOTES: 1. X can be Vi_ or Vin 2. See DC Programming Characteristics for Vcp, Vpp and Vip voltages. 3. AyAg, A1o-Aie = Vit 5-106intel. 270220 PRELIMINARY Read Mode The 27C220 has two control functions; both must be enabled to obtain data at the outputs. CE is the pow- ~ E controls the output - er control and device select. buffers to gate data to the outputs. With addresses stable, the address access time (tacc) equals the delay from CE to output (toe). Outputs display valid data tog after OEs falling edge, assuming tacc and tcge times are met. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. . Two Line Output Control EPROMs are often used in larger memory arrays. Intel provides two control inputs to accommodate multiple memory connections. Two-line control pro- vides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these two control inputs, an ad- dress decoder should enable CE, while OE should be connected to all memory devices and the sys- . tems READ control line. This assures that only se- lected memory devices have active outputs while deselected memory devices are in Standby Mode. Standby Mode prandby Mods substantially reduces. Voc current. When CE = Vj, the outputs are in a high imped- ance state, independent of OE. Program Mode Caution: Exceeding 14V on Vpp will permanently damage the device. Initially, and after each erasure, all EPROM bits are in the 1 state. Data is introduced by selectively programming Os into the desired bit locations. Al- though only Os are. programmed, the data word can contain both 1s and Os. Ultraviolet light era- sure is the only way to change Os to.1s. Program Mode is entered when Vpp is raised to 12.75V. Data is introduced by applying a 16-bit word to the output pins. Pulsing P' low while CE = ViL and OE = Vix programs that data into the device. Program Verify A verify should be performed following a program operation to determine that bits have been correctly programmed. With Voc at 6.25V, a substantial pro- en margin is ensured. The verify is performed with and PGM at Vix. Valid data is available tog after OE falls low. - Program Inhibit . Program Inhibit Mode allows parallel programming of. multiple EPROMs with different data. CE-high in- hibits programming of non-targeted devices. Except for CE, parallel EPROMs may have common inputs. <intgligent Identifier Mode The intgligent Identifier Mode will determine an EPROMs manufacturer and device type, allowing programming equipment to automatically match a - device with its proper programming algorithm. This mode is activated when a programmer forces 12V +0.5V on Ag. With CE, OE, AyAg, and Aio- Ajg at Vii, Ap =: Viz will present the manufacturer cod and Ag = Vjiy the device code. This mode functions in the 25C +5C ambient temperature range required during programming. UPGRADE PATH Future upgrade to the 4-Mbit density is easily ac- complished due to the standardized pin configura- tion of the 27C220. When the 27C220 is in Read - Mode, the PGM input becomes non-functional. This allows address line A17 to be routed directly to this input in anticipation of future density upgrades. Sys- ters designed for 2-Mbit program memories today can be upgraded to 4-Mbit in the future with no cir- cuit board changes. : - SYSTEM CONSIDERATIONS EPROM power switching characteristics require careful device decoupling. System designers are in- terested in 3 supply current issures: standby current levels (igg), active current levels (icc), and transient current.peaks: produced by falling and rising edges of CE. Transient current magnitudes depend on the device. outputs capacitive and inductive loading. Two-line control and:-proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between its Voc and GND. This high fre- quency, low. inherent-inductance capacitor should be placed as close as possible to the device. Addi- tionally, for every 8 devices, a 4.7 nF electrolytic capacitor should be placed _at the arrays power sup- ply connection between Voc and GND. The bulk ca- pacitor will overcame voltage slumps caused by PC board trace inductances. . 5-107270220 PRELIMINARY ADDRESS = FIRST LOCATION Vog = 6.28 Vpp = 12.78 290217-9 ~ Figure 4. Quick-Pulse Programming Algorithm ERASURE CHARACTERISTICS Erasure begins when EPROMs are exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain fluorescent lamps have wavelengths in the 3000A~4000A range. Data shows that constant ex- posure to room level fluorescent lighting can erase an EPROM in approximately 3 years, :while it takes approximately 1. week when exposed to direct sun- light. If the device is exposed to these fightirig condi- tioris for extended periods, opaque labels. should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to ultraviolet light of wavelength 2537A. The inte- grated dose (UV intensity x exposure time) for era- sure should be a minimum of 15 Wsec/cm?. Erasure time is approximately 15 to 20 minutes using an ul- traviolet lamp with a-12000 W/cm2 power rating. The EPROM should be placed within 1 inch of the lamp tubes. An EPROM can be permanently dam- aged if the integrated dose exceeds 7258 Wsec/ cm2 (1 week @ 12000 pW/cme2). Quick-Pulse Programming Algorithm The Quick-Pulse programming algorithm programs Intels 27C220. Developed to substantially reduce programming throughput, this algorithm can program the 27C220 as fast as 15 seconds: Actual program- ming time depends on programmer overhead. The Quick-Pulse programming algorithm employs a 100 ps pulse followed by a word verification to de- termine when the addressed word has been suc- cessfully programmed. The algorithm terminates if 25 attempts fail to program a word. The entire program pulse/word verify sequence is performed with Vpp = 12.75V and Vcc = 6.25V. When programming is complete, all words are com- pared to the original data with Voc = Vpp = 5.0V. 5-108intel. 27c220 PRELIMINARY DC PROGRAMMING CHARACTERISTICS T, = 25C +5C Symbol Parameter Notes | Min Typ | Max | Unit Test Condition tay Input Load Current 1 BA | Vin = Vitor Vin lop Vcc Program Current 1 50 | mA | CE = PGM= vy, Ipp Vpp Program Current | -. -f 50 | mA | CE = PGM = Wj. ViL Input Low Voltage -0.1 0.8 Vv Vin Input High Voltage 2.4- 6.5 Vv Voi Output Low Voltage (Verity) 0.45] V. | Iol=2.1mA Vou Output High Voltage (Verify) 3.5 v lon = 2.5mA Vip Ag intgligent Identifier Voltage 11.5 12.0 | 12.5 Vv Vpp Vpp Program Voltage 2,3 .|..12.5 .| 12.75 | 13.0 Vv Vop Vcc Supply Voltage (Program) 2 6.0 6.25 6.5 Vv AC PROGRAMMING CHARACTERISTICS(4) T, = 25C +5C Symbol Parameter Notes Min Typ - Max Unit tvcs Vop Setup Time 2 2 ps types Vpp Setup Time 2 2 ps toes CE Setup Time 2 ps tas Address Setup Time 2 pS tos Data Setup Time 2 pS tpw PGM Program Pulse Width 95 100 105 ps ton Data Hold Time 2 BS toes OE Setup Time 2 ps tog Data Valid from OE 5 150 ns torp OE High to Output High Z 5,6 0 130 ns tay Address Hold Time o ps NOTES: 1. Maximum current is with outputs OgO 5 unloaded. 2. Vcp must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 3. When programming, a 0.1 F capacitor is required across Vpp and GND to suppress spurious voltage transients which can damage the device. 4. See AC Input/Output Reference Waveform for timing measurements. 5. tog and tprp are device characteristics but must be accommodated by the programmer. 6. Sampled, not 100% tested. 5-109intel. 27C220 PRELIMINARY PROGRAMMING WAVEFORMS a ADDRESSES X ADONESS STABLE Ve Lg- "AS __pal vin DATA DATA IN STABLE Vee q~ '05 __J Lag 'OF 12.78V a Vep 5.0V Wes. oo 628v Vec .0 tives gol Viw a Ma {ces __J Vin a Pom Vu tow foes to IH oe \ 290217-10 REVISION HISTORY Number Description 005 Deleted -150 PDIP, PLCC packages 5-110