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Features
• Industry's first TotalCMOS™ SPLD - both CMOS
design and process technologies
• Fast Zero Power (FZP™) design technique provides
ultra-low power and high speed
- Static current of less than 45 µA
- Dynamic current substantially below that of
competing devices
- Pin-to-pin delay of only 10 ns
• True Zero Power device with no turbo bits or power
down schemes
• Function/JEDEC map compatible with Bipolar,
UVCMOS, EECMOS 22V10s
• Multiple packaging options featuring PCB-f r iendly
flow-through pinouts (SOL and TSSOP)
- 24-pin TSOIC–uses 93% less in-system space than
a 28-pin PLCC
- 24-pin SOIC
- 28-pin PLCC with standard JEDEC pinout
• A vailable in commercial and industrial operating ranges
• Suppor t s mixed voltage systems— 5V tolerant I/Os
• Advanced 0.5µ E2CMOS process
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Varied product term distribution with up to 16 product
terms per output for complex functions
• Programmable output polarity
• Synchronous preset/asynchronous reset capability
• Security bit prevents unauthorized access
• Electronic signature for identification
• Design entry and verification using industry standard
CAE tools
• Reprogrammable using industry standard device
programmers
Description
The XCR22LV10 is the first SPLD to combine high perfor-
mance with low power, without the need for "turbo bits" or
other power down schemes. To achieve this, Xilinx has
used their FZP design technique, which replaces conven-
tional sense amplifier methods for implementing product
terms (a technique that has been used in PLDs since the
bipolar era) with a cascaded chain of pure CMOS gates.
This results in the combination of low power and high
speed that has previously been unattainable in the PLD
arena. For 5V operation, Xilinx offers the XCR22V10 that
offers high speed and low power in a 5V implementation.
The XCR22LV10 uses the familiar AND/OR logic array
structure, which allows direct implementation of
sum-of-products equa tions. This device has a programma-
ble AND array which drives a fixed OR array. The OR sum
of products feeds an "Output Macro Cell" (OMC), which can
be individually configured as a dedicated input, a combina-
torial output, or a registered output with internal feedback.
Functional Description
The XCR22LV10 implements logic functions as
sum-of-products expressions in a programmable-
AND/fixed-OR logic array. User-defined functions are cre-
ated by programming the connections of input signals into
the arra y. User-configurable output structures in the form of
I/O macrocells further increase logic fle x ibility (Figure 1).
0
XCR22LV10: 3V Zero Power,
TotalCMOS, Universal PLD Device
DS047 (v1.1) February 10, 2000 00*
Product Specification
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Figure 1: XCR22LV10 Logic Diagram
NOTE:
Programmable connection.
1
1
0
0
0
1
0
1
DARQ
Q
SP
0
1
Q
1
1
0
0
0
1
0
1
DARQ
SP
0
1
Q
1
1
0
0
0
1
0
1
DARQ
SP
0
1
Q
1
1
0
0
0
1
0
1
DARQ
SP
0
1
Q
1
1
0
0
0
1
0
1
DARQ
SP
0
1
Q
1
1
0
0
0
1
0
1
DARQ
SP
0
1
Q
1
1
0
0
0
1
0
1
DARQ
SP
0
1
Q
1
1
0
0
0
1
0
1
DARQ
SP
0
1
Q
1
1
0
0
0
1
0
1
DARQ
SP
0
1
Q
1
1
0
0
0
1
0
1
DARQ
SP
0
1
AR
SP
0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536 3940 43
0 34 78 1112151619202324272831323536394043
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I10
I8
I9
GND
I11
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
VCC
0
1
9
10
20
21
33
34
48
49
65
66
82
83
97
98
110
111
121
122
130
131
SP00059
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Architecture Overview
The XCR22LV10 architecture is illustrated in Figure. Twelve
dedicated inputs and ten I/Os provide up to 22 inputs and
ten outputs for creation of logic functions. At the core of the
device is a programmable electrically-erasable AND array
which drives a fixed-OR array. With this structure, the
XCR22LV10 can implement up to ten sum-of-products logic
expressions.
Associated with each of the ten OR functions is an I/O mac-
rocell which can be independently programmed to one of
f our different configur ations. The programmable macrocells
allow each I/O to create sequential or combinatorial logic
functions with either active High or active Low polarity.
AND/OR Logic Array
The programmable AND array of the XCR22LV10 (shown
in the Logic Diagram, Figure 1) is formed by input lines
intersecting product terms. The input lines and product
terms are used as follows:
44 input lines:
•24 input lines carry the True and Complement of the
signals applied to the 12 input pins
•20 additional lines carry the True and Complement
values of feedback or input signals from the ten I/Os
•132 product terms :
•120 product terms (arranged in two groups of 8, 10, 12,
14, and 16) used to form logical sums
•Ten output enable terms (one for each I/O)
•One global synchronous preset product ter m
•One global asynchronous clear product term
At each input-line/product-term intersection there is an
EEPROM memory cell which determines whether or not
there is a logical connection at that intersection. Each prod-
uct term is essentially a 44-input AND gate. A product term
which is connected to both the True and Complement of an
input signal will always be FALSE, and thus will not affect
the OR function that it drives. When all the connections on
a product ter m are opened, a Don't Care state exists and
that term will always be TRUE.
Variable Product Term Distribution
The XCR22LV10 provides 120 product terms to drive the
ten OR functions. These product terms are distributed
among the outputs in groups of 8, 10, 12, 14, and 16 to
form logical sums (see Logic Diagram). This distribution
allows optimum use of device resources.
Programmable I/O Macrocell
The output macrocell provides complete control over the
architecture of each output. the ability to configure each
output independently permit s users to tailor the configura-
tion of the XCR22LV10 to the precise requirements of their
designs.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 3 consists of a
D-type flip-flop and two signal-select mul tiple x ers. The con-
figuration of each macrocell of the XCR22LV10 is deter-
mined by the two EEPROM bits controlling these
multiplexers. These bits determine outp ut polarity, and out-
put type (registered or non-registered). Equivalent circuits
for the macrocell configurations are illustrated in Figure 4.
Figur e 2 : Fun c t i onal Di ag r a m
OUTPUT
MACRO
CELL
CLK/I0 I1 – I11
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9
PROGRAMMABLE AND ARRAY
(44 ×
132)
111
81012141616141210 8
SP00060A
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
RESET
PRESET
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XCR22LV10: 3V Zero P o wer , TotalCMOS, Universal PLD
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Figure 3: Output Macrocell Logic Diagram
F
0
1
1
0
0
1
0
0
1
CLK
1
AR
SP S1S0
S
1
S
0
OUTPUT CONFIGURATION
0 = Unprogrammed fuse
1 = Programmed fuse
DQ
Q
0
0
1
1
0
1
0
1
Registered/Active-LOW/Macrocell feedback
Registered/Active-HIGH/Macrocell feedback
Combinatorial/Active-LOW/Pin feedback
Combinatorial/Active-HIGH/Pin feedback
SP00484
Figure 4: Output Macrocell Configurati ons
F
CLK
AR
SP
S0 = 0
S1 = 0
DQ
Q
a. Registered/Active-LOW
F
CLK
AR
SP
S0 = 1
S1 = 0
DQ
Q
b. Registered/Active-HIGH
F
S0 = 0
S1 = 1
c. Combinatorial/Active-LOW
d. Combinatorial/Active-HIGH
F
S0 = 1
S1
SP00376
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Output Type
The signal from the OR array can be fed directly to the out-
put pin (combinatorial function) or latched in the D-type
flip-flop (registered function). The D-type flip-flop latches
data on the rising edge of the clock and is controlled b y the
global preset and clear terms. When the synchronous pre-
set term is satisfied, the Q ou tput of the register will be set
High at the ne xt rising edge of the clock input. Satisfying the
asynchronous clear te r m will s et Q LOW, regardless of the
clock state. If both ter ms are satisfied simultaneously, the
clear will over ride the preset.
Program/Erase Cycles
The XCR22LV10 is 100% testable, erases/programs in
seconds, and guarantees 1000 program/erase erase
cycles.
Output Polarity
Each macrocell can be configured to implement active High
or active Low logic. Programmable polarity eliminates the
need for external inver ters.
Output Enable
The output of each I/O macrocell can be enabled or dis-
abled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is driven into the high-impedance state.
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bidi-
rectional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically FALSE and
the I/O will function as a dedicated input.
Register Feedback Select
When the I/O macrocell is configured to implement a regis-
tered function (S1=0) (Figure 4a or Figure 4b), the feed-
back signal to the AND array is taken from the Q output.
Bi-directional I/O Select
When configuring an I/O mac rocell to implement a com bi-
natorial function (S1=1) (Figure 4c or Figure 4d), the feed-
back signal is taken from the I/O pin. In this case, the pin
can be used as a dedicated input, a dedicated out put, or a
bi-directional I/O .
Powe r-On Reset
To ease system initialization, al l flip-flops will pow er-up to a
reset condition and the Q output wil l be low. The actual out-
put of the XCR22LV10 will depend on the programmed out-
put polarity. The VCC rise must be monotonic.
Design Security
The XCR22LV10 provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs
programmed into the device. The security bit is set by the
PLD programmer, either at the c onclusion of the program-
ming cycle or as a separate step, after the de vice has been
programmed. Once the security bit is set, it is impossible to
verify (read) or program the XCR22LV10 until the entire
device has first been erased with the bulk-erase function.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS SPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gat es to im plement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to off e r SPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must accept low perfor-
mance. Refer to Figure 5 and Table 1 showing the ICC vs.
Frequency of our XCR22LV10 TotalCMOS SPLD.
Table 1: Typical ICC vs. Frequency @ VCC = 3.3V, 25°C
Frequency (MHz) Tupical ICC (mA)
10.2
10 1.5
20 3.0
30 4.5
40 6.0
50 7.4
60 8.9
70 10.4
80 11.8
90 13.2
100 14.5
110 15.8
120 17.0
130 18.2
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Absolute Maximum Ratings1
Operating Range
Figure 5: Typical ICC vs. Frequency @ VCC = 3.3V, 25°C (10-bit counter)
Symbol Parameter Min. Max. Unit
VCC Supply voltage –0.5 4.6 V
VIInput voltage –0.5 5.52V
VOUT Output voltage –0.5 5.52V
IIN Input current –30 30 mA
IOUT Output curr ent –100 100 mA
TRAllowale thermal rise ambient to junction 0 75 °C
TJMaximum junction temperature –40 150 °C
TSTG Storage temperature –65 150 °C
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation
at these or any other condition above those indicated in the operational and programming specification is not implied..
2. Except F7, where max = VCC + 0.5V.
Product Grade Temperature Voltage
Commercial 0 to +70°C3.3V ± 10%
Industrial –40 to +85°C3.3V ± 10%
0
5
10
15
20
25
30
10 20 30 40 50 60 70 80 90 100 110 120 130
TYPICAL
ICC
(mA)
FREQUENCY (MHz)
SP00443
1
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DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 3.03.6V ≤ VCC ≤ 3.6V
Symbol Param eter Test Conditions Min. Ty p. Max. Unit
VIL Input voltage Low VCC = 3.0V 0.8 V
VIH Input voltage High VCC = 3.6V 2 V
VIInput clamp voltage VCC = 3.0V, IIN = –18 mA –1.2 V
VOL Output voltage Low VCC = 3.0V, IOL = 8 mA 0.5 V
VOH Output voltage High VCC = 3.0V, IOH = –4 mA 2.4 V
IIInput leakage current VIN = 0V to VCC –10 10 µA
VIN = VCC to 5.5V 2–10 10
IOZL 3-stated output leakage current VIN = 0V to VCC –10 10 µA
VIN = VCC to 5.5V 2–10 10
ICCQ Standby current VCC = 3.6V, TAMB = 0°C2545µA
ICCD1Dynamic curr ent VCC = 3.6V, TAMB = 0°C at 1 MHz 0.5 2 mA
VCC = 3.6V, TAMB = 0°C at 50 MHz 10 15 mA
IOS Short circuit output current One pin at a time for no longer than 1
second –15 –100 mA
CIN Input pin capacitance TAMB = 25°C, f = 1 MHz 8 pF
CCLK Clock input capacitance TAMB = 25°C, f = 1 MHz 5 12 pF
CI/O I/O pin capacitance TAMB = 25°C, f = 1 MHz 10 pF
Notes: 1. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This
parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where
current may be affected.
2. Does not apply to F7.
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AC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ + 70°C ; 3.0V ≤ VCC ≤ 3.6V
Symbol Parameter -B -D Unit
Min. Max. Min. Max.
tPD Propagation delay time, input or feedback to non-registered output 15 10 ns
tSU Setup time from input, feedback or SP to Clock 4.5 3.5 ns
tCO Clock to output 10 9 ns
tCF Clock to feedback164.5ns
tHHolt time 00ns
tAR Asynchronous Reset to registered output 17 17 ns
tARW Asynchronous Reset width 5 5 ns
tARR Asynchronous Reset recovery time 6 6 ns
tSPF Synchronou Preset recovery time 6 6 ns
tWL Width of Clock Low 3 3 µs
tWH Width of Clock High 3 3 µs
tRInput rise time 20 20 ns
tFInput fall time 20 20 ns
fMAX1 Maximum F F toggle rate2 (1/tSU + tCF) 95 125 MHz
fMAX2 Maximum internal frequency 1 (1/tSU + tCO)6980MHz
fMAX3 Maximum ext ernal frequency1 (1/tWL + tWH) 167 167 MHz
tEA Input to output enable 9 9 ns
tER Input to output disable 9 9 ns
Capacitance
CIN Input pin capacitance 10 10 pF
COUT Output capacitance 10 10 pF
Notes:
1. This para met er is not 100 % teste d, but is calculat ed at i nitial chara cterizatio n and at any time the desi g n is modi fied where current may
be affected.
2. This pa rameter measure d with a 10 -bit, w ith all outp uts enabled an d unlo aded. In puts are tied to VCC or grou nd. T hi s pa rameter is no t
100% tested, but is calculated at initial characterization and at any time the design is modified where current ma y be affected.
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DC Electrical Characteristics For Industrial Grade Devices
Industrial: –40°C ≤ TAMB ≤ +85°C; 3.0V ≤ VCC ≤ 3.6V
Symbol Param eter Test Conditions Min. Ty p. Max. Unit
VIL Input voltage Low VCC = 3.0V 0.8 V
VIH Input voltage High VCC = 3.6V 2 V
VIInput clamp voltage VCC = 3.0V, IIN = –18 mA –1.2 V
VOL Output voltage Low VCC = 3.0V, IOL = 8 mA 0.5 V
VOH Output voltage High VCC = 3.0V, IOH = –4 mA 2.4 V
IIInput leakage current VIN = 0V to VCC –10 10 µA
VIN = VCC to 5.5V 2–10 10
IOZL 3-stated output leakage current VIN = 0V to VCC –10 10 µA
VIN = VCC to 5.5V 2–10 10
ICCQ Standby current VCC = 3.6V, TAMB = –40°C3045µA
ICCD1Dynamic curr ent VCC = 3.6V, TAMB = –40°C at 1 MHz 0.5 3 mA
VCC = 3.6V, TAMB = –40°C at 50 MHz 10 20 mA
IOS Short circuit output current One pin at a time for no longer than 1
second –15 –100 mA
CIN Input pin capacitance TAMB = 25°C, f = 1 MHz 8 pF
CCLK Clock input capacitance TAMB = 25°C, f = 1 MHz 5 12 pF
CI/O I/O pin capacitance TAMB = 25°C, f = 1 MHz 10 pF
Notes: 1. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This
parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where
current may be affected.
2. Does not apply to F7.
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AC Electrical Characteristics For Industrial Grade Devices
Industrial: –40°C ≤ TAMB ≤ +85°C; 3.0V ≤ VCC ≤ 3.6V
Symbol Parameter Unit
Min. Max.
tPD Propagation delay time, input or feedback to non-registered output 15 ns
tSU Setup time from input, feedback or SP to Clock 5 ns
tCO Clock to output 10.5 ns
tCF Clock to feedback16ns
tHHolt time 0ns
tAR Asynchronous Reset to registered output 17 ns
tARW Asynchronous Reset width 5 ns
tARR Asynchronous Reset recovery time 6 ns
tSPF Synchronou Preset recovery time 6 ns
tWL Width of Clock Low 3 µs
tWH Width of Clock High 3 µs
tRInput rise time 20 ns
tFInput fall time 20 ns
fMAX1 Maximum F F toggle rate2 (1/tSU + tCF)91MHz
fMAX2 Maximum internal frequency 1 (1/tSU + tCO)65MHz
fMAX3 Maximum ext ernal frequency1 (1/tWL + tWH)167MHz
tEA Input to output enable 11 ns
tER Input to output disable 11 ns
Capacitance
CIN Input pin capacitance 10 pF
COUT Output capacitance 12 pF
Notes:
1. This parameter is not 100% tested, but is calculated at initial characterization and at any t ime the design is modified
where current may be affected.
2. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or groun d. Th i s param ete r is
not 100% tested, but is cal culated at initial characterization and at any time the design is modi fied where current may be affected.
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Test Load Circuit
Thevenin Equivalent
Voltage Waveform
+3.3V
CL
R1
R2
S1
C2
C1
NOTE:
C1 and C2 are to bypass VCC to GND.
R1 = 300Ω, R2 = 300Ω, CL
= 35pF.
VCC
GND
CK
In
I0F0
Fn
DUT
OE
INPUTS
SP00478
35 pF
150Ω
DUT OUTPUT
V
L
= 1.65V
90%
10%
1.5ns1.5ns
+3.0V
0V
t
R
t
F
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
SP00368
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Switching Waveforms
"AND" Array: (I,B)
tS
NOTES:
1. VT = 1.5V.
2. Input pulse amplitude 0V to 3.0V.
3. Input rise and fall times 2.0 ns max.
Combinatorial Output
Clock Width Input to Output Disable/Enable
Asynchronous Reset Synchronous Preset
tPD
VT
VT
INPUT OR
FEEDBACK
COMBINATORIAL
OUTPUT
VT
VT
VT
INPUT OR
FEEDBACK
CLOCK
REGISTERED
OUTPUT
tStH
tCO
VT
tWH
CLOCK
tWL
tER tEA
VOH – 0.5V
VOL + 0.5V
INPUT
OUTPUT
VT
VT
VT
VT
VT
tARW
tAR
tARR
CLOCK
REGISTERED
OUTPUT
INPUT ASSERTING
ASYNCHRONOUS
RESET
tH
VT
VTVT
VT
tSPR
INPUT ASSERTING
SYNCHRONOUS
PRESET
CLOCK
REGISTERED
OUTPUT
tCO
SP00483
Registered Output
I, B
P, D
CODE
O
STATE
INACTIVE1CODESTATE CODESTATE CODESTATE
TRUE HL—
P, D
I, B
I, B
P, D
I, B
I, B
P, D
I, B
I, B I, B
COMPLEMENT DON’T CARE
SP00008
I, B I, B I, B
I, B
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Pin Configurations
28-pin PLCC
24-pin SOIC and 24-pin TSOIC
Pin Descriptions
25
1234
5
6
7
8
9
10
11
12 13 14 15 16 17 18
19
20
21
22
23
24
262728
NC
IO/CLK
I1
I2
F7
F6
F5
NC
F4
F3
F2
I3
I4
I5
NC
I6
I7
I8
I9
I10
GND
NC
I11
F0
F1 F8
F9
VCC
SP00474
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24IO/CLK
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
VCC
F9
F8
F7
F6
F5
F4
F2
F3
F1
F0
I11GND
AP00475
Pin Label Description
I1-I11 Dedicated input
NC Not Connected
F0-F9 Macrocell Input/Output
I0/CLK Dedicated Input/Clock Output
VCC Supply Voltage
GND Ground
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Ordering Information
Revision History
Component Availability
Pins 24 28
Type Plastic SOIC Plastic Thin SOIC Plastic PLCC
Code SO24 VO24 PC28
XCR22LV10 -15 C, I C, I
-10 C C
Ex am ple: XC R 22LV 10 -1 0 PC 28 C
Temperature Range
Number of Pins
Package Type
Speed Options
-15: 15 ns pin-to-pin delay
-10: 10 ns pin-to-pin delay
Temperature Range
C = Commercial, TA = 0°C to +70°C
I = Industrial, TA = –40°C to +85°C
Packaging O pti ons
SO24: 24-pin SOIC
VO24: 24-pin TSOIC
PC28: 28-pin PLCC
Device Type
Speed Options
Date Version # Revision
8/4/99 1.0 Initial Xilinx release.
2/10/00 1.1 Convert to Xilinx Format
