Advanced a, CATALYST CAT28C512/513 512K-Bit CMOS PARALLEL E?PROM FEATURES m Fast Read Access Times: 120/150 ns m Low Power CMOS Dissipation: Active: 50 mA Max. Standby: 500 WA Max. = Simple Write Operation: On-Chip Address and Data Latches Self-Timed Write Cycle with Auto-Clear m@ Fast Write Cycle Time: 5ms Max m CMOS and TTL Compatible I/O m Automatic Page Write Operation: 1 to 128 Bytes in 5ms Page Load Timer m@ End of Write Detection: -Toggle Bit -DATA Polling Hardware and Software Write Protection 100,000 Program/Erase Cycles 100 Year Data Retention Commercial, Industrial and Automotive Temperature Ranges DESCRIPTION The CAT28C512/513is afast,low power, 5V-only CMOS parallel E7PROM organized as 64K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and Vcc power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28C51 2/513 features hardware and software write protection. The CAT28C512/513 is manufactured using Catalysts advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has adata retention of 100 years. The device is available in JEDEC approved 32-pin DIP, PLCC and 40-pin TSOP pack- ages. BLOCK DIAGRAM AA ADDR. BUFFER > ROW > 65,536 x8 mes , &LATCHES = | DECODER E2PROM - fs ARRAY INADVERTENT HIGH VOLTAGE > i Vog WRITE GENERATOR 128 BYTE PAGE PROTECTION ; A cy hoy OE ___ CONTROL | WE ______- | Ay y >; 1/0 BUFFERS DATA POLLING TIMER AND { TOGGLE BIT Toto, An-A ADDR. BUFFER _ oe > & LATCHES > COLUMN DECODER 5096 FHD Fo2 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8-111CAT28C512/513 Advanced PIN CONFIGURATION DIP Package (P) PLCC Package (N) PLCC Package (N) a Lo oO N+ ow QO o rr oO Lu rrr Ww? nocder a2 H Voc ZELLOES ETERS NCL] 2 31 WE Aono /ALUUOoO 4 3 4 3 2 1 323130 m8 ; 5G ae, A7 5 29171 A14 AgC] 5 29171 Ag Co - eA, Ag 6 2817 A13 Asc 6 28H Ag = 5 HAL As] 7 2717 Ag Asc] 7 27 Ady he 7 ef ho 4(| 8 carascsi2 26 Fi Ae A318 ~ catesc5i3. 26 FNC A ds oh A A3C] 9 TOP VIEW =. 25D Ay Act] 9 TOPVIEW 25D6E ado m4 Oe Ao] 10 24171 OF Arq 10 2414 Aig moc to 23a wo NM 3 Ai od 1 23 CE 2 10 AQ 12 22111 CE Ne C] 12 2217] O07 Ay) 1 22TI CE gg 13 21 vo Op EC] 13 215 0, AgOj 12 21 [1 Woz 14.15 16 17 18 19 20 7 14151617 18 19 20 6 VOgL{ 13 20 FA Og OOOOUoOoO OOOUOCoO VO, 14 19/0 Vos r NN OTD CANNY Ow COnd20090 VOoO) 15 18/0 Og LLPsseEy QQHs Qe VssH 16 17[ I/03 5096 FHD F01 TSOP Package (10mm X 14mm) (114) Aq{oof10 40 H40E Ag =42 39 A A190 Ag-43 38 74 CE Ayg 044 37 I/07 Ayq4 C45 36 FL 1/0g Nc H46 35 FS 1/05 NC 447 34 FC 1/04 Nc Crys 33 Fr 1/03 Weo9 32 A NC Voc C=} 10 31 NC NCCO411 30 A Vss NCL=412 29 FL NC NC 13 281 NC NCI 14 27 FS 02 Ai5007415 2674/01 AjoI1416 25 FA 1/09 A7O417 243 Ao Ag 18 23 Ay A511 19 22 FIT Ap A4C-T120 21A Ag PIN FUNCTIONS Pin Name Function Pin Name Function Ao-A15 Address Inputs WE Write Enable I/Oo-l/O7 Data Inputs/Outputs| Vcc 5V Supply CE Chip Enable Vss Ground OE Output Enable NC No Connect Stock No. 21079-01 2/98 8-112Advanced CAT28C512/513 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. 55C to +125C Stresses above those listed under Absolute Maximum Storage Temperature... 65C to +150C Ratings" may cause permanent damage to the device. . These are stress ratings only, and functional operation Voltage on Any Pin with of the device at these or any other conditions outside of Respect to Ground?) ........... -2.0Vto+Vcc+2.0V those listed in the operational sections of this specifica- Vcc with Respect to Ground ............... -2.0Vto+7.0V __ tion is not implied. Exposure to any absolute maximum Package Power Dissipation rating for extended periods may affect device perfor- Capability (Ta = 25C) .......ccecceceeeeeeeeeeeee 1.0W mance and reliability. Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current) ..0.... 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Test Method Nenp) Endurance 104 or 105 Cycles/Byte MIL-STD-883, Test Method 1033 Tor") Data Retention 100 Years MIL-STD-883, Test Method 1008 Vzap) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILtH)4) | Latch-Up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS Vec = 5V +10%, unless otherwise specified. Limits Symbol Parameter Min. | Typ. Max. | Units Test Conditions loc Vcc Current (Operating, TTL) 50 mA | CE=OE = Vi, f=8MH, All I/Os Open lecc) Vcc Current (Operating, CMOS) 25 mA | CE=OE = Vic, f=8MHz All I/Os Open Isp Vcc Current (Standby, TTL) 3 mA | CE = Vin, All I/Os Open Isao!) Voc Current (Standby, CMOS) 500 wA | CE=Vinc, All I/Os Open IL Input Leakage Current -10 10 LA Vin = GND to Vcc ILo Output Leakage Current -10 10 LA Vout = GND to Vcc, CE = Vin Vint) High Level Input Voltage 2 Veco +0.3] V Vi) Low Level Input Voltage -1 0.8 Vv Vou High Level Output Voltage 2.4 Vv lon = 400uA VoL Low Level Output Voltage 0.4 Vv lol = 2.1mA Vwi Write Inhibit Voltage 3.5 Vv Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is Voc +0.5V, which may overshoot to Vcc +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to Vec +1V. (5) Vic =0.3V to +0.3V. (6) Vinc = Voc 0.3V to Vec +0.3V. 8-113 Stock No. 21079-01 2/98CAT28C512/513 Advanced MODE SELECTION Mode CE WE OE vO Power Read L H L Dout ACTIVE Byte Write (WE Controlled) L \S H DIN ACTIVE Byte Write (CE Controlled) \S L H DIN ACTIVE Standby, and Write Inhibit H x x High-2 STANDBY Read and Write Inhibit x H H High-Z ACTIVE CAPACITANCE Ta = 25C, f = 1.0 MHz, Voc = 5V Symbol Test Max. Units Conditions Cyo) Input/Output Capacitance 10 pF Vio = OV Cin) Input Capacitance 6 pF Vin = OV A.C. CHARACTERISTICS, Read Cycle Vec=5V + 10%, Unless otherwise specified 280512/513-12/28C512/513-15 Symbol | Parameter Min. | Max. | Min. | Max. | Units tro Read Cycle Time 120 150 ns tcE CE Access Time 120 150 ns TAA Address Access Time 120 150 ns toE OE Access Time 50 50 ns iz) CE Low to Active Output 0 0 ns to.z) | OE Low to Active Output 0 0 ns taz2)_ | CE High to High-Z Output 50 50 ns tonz()@) | OE High to High-Z Output 50 50 ns ton") Output Hold from Address Change 0 0 ns Power-Up Timing Symbol Parameter MAX Units tpur Power-up to Read Operation 100 us tpuw ?) Power-up to Write Operation 5 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. Stock No. 21079-01 2/98 8-114Advanced CAT28C512/513 A.C. CHARACTERISTICS, Write Cycle Vec=5V+10%, unless otherwise specified 28C512/513-12/28C512/513-15 Symbol| Parameter Min. | Max. | Min. | Max. | Units two Write Cycle Time 5 5 ms tas Address Setup Time 0 0 ns TAH Address Hold Time 50 50 ns tcs CE Setup Time 0 0 ns tcH CE Hold Time 0 0 ns tow) CE Pulse Time 100 100 ns toes OE Setup Time 0 0 ns toEH OE Hold Time 0 0 ns twp) WE Pulse Width 100 100 ns tos Data Setup Time 50 50 ns tDH Data Hold Time 0 0 ns tint) | Write Inhibit Period After Power-up| 5 10 5 10 ms tarc()(4) | Byte Load Cycle Time 0.1 100 | 0.1 | 100 us Figure 1. A.C. Testing Input/Output Waveform(2) 24V 2.0V INPUT PULSE LEVELS x REFERENCE POINTS 08V 0.45 V 5096 FHD Fo3 Figure 2. A.C. Testing Load Circuit (example) 1.3V 1N914 3.3K DEVICE UNDER OUT TEST CL = 100 pF Note: C, INCLUDES JIG CAPACITANCE 5096 FHD Fo4 (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Input rise and fall times (10% and 90%) < 10 ns. (3) Awrite pulse of less than 20ns duration will not initiate a write cycle. (4) Atimer of duration tg_ max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tg_c max. stops the timer. 8-115 Stock No. 21079-01 2/98CAT28C512/513 Advanced DEVICE OPERATION Byte Write Read Awrite cycle is executed when both CE and WE are low, Data stored in the CAT28C512/513 is transferred to the data bus when WEis held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. Figure 3. Read Cycle ADDRESS x Y c \ -~< tcE _ tof r a OE \ / VIH WE tLZ > httOHZ> t-tOLz> it tOH > }t tHZ > HIGH-Z j DATA OUT { DATA VALID DATAVALID = } }~<tAa 28C512/513 FO6 Figure 4. Byte Write Cycle [WE Controlled] XK tas |+-tAH mics ADDRESS A y XXX KERRY WTSI WAAAY tOEH OE LELLELL) tOoES >} twp we \ / WWMM A HIGH-Z A Ad > }- 1BLC> wae nar patacuT (XXXXXAA DATA IN DATA VALID 5096 FHD FO6 Stock No. 21079-01 2/98 8-116Advanced CAT28C512/513 Page Write The page write mode of the CAT28C512/513 (essen- tially an extended BYTE WRITE mode) allows from 1 to 128 bytes of data to be programmed within a single E*PROM write cycle. This effectively reduces the byte- write time by a factor of 128. Following an initial WRITE operation (WE pulsed low, for twp, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 128 byte temporary buffer. The page address where data is to be written, specified by bits A7 to A15, is latched on the last falling edge of WE. Each byte within the page is defined by address bits Ao to Ag (which can be loaded in any order) during the first and subsequentwrite cycles. Each successive byte load cycle must begin within taic max of the rising edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within tpic max. Upon completion of the page write sequence, WE must stay high a minimum of tgic max for the internal auto- matic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page. Figure 5. Byte Write Cycle [CE Controlled] tAH ADDRESS TR KKK KI tcw ny ml m vw A / WAAAY AY OE LLLLLL} t tOES tcs we \\\\\\\ A y tCH 7 . WAY CN , HIGH-Z DATA OUT ) Ds DH 5096 FHD F07 Figure 6. Page Mode Write Cycle OE /// Lf CE \ /7/\ <r| twP [Tx [T../Ts [TD [TTT >iBLC 5 Wy VS \S NS NS ADDRESS xX xX x Vo XXXXXXXXKKKKX \ \ \ xX 2 BYTE 2 BYTEn BYTEO BYTE 1 BYTE n+1 BYTE n+2 5096 FHD F10 8-117 Stock No. 21079-01 2/98CAT28C512/513 Advanced DATA Polling DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on 1/07 (I/Oo-I/Og are indeterminate) until the programming cycle is com- plete. Upon completion of the self-timed write cycle, all 1/Os will output true data during a read cycle. Toggle Bit In addition to the DATA Polling feature ofthe CAT28C512/ 513, the device offers an additional method for determin- ing the completion of a write cycle. While a write cycle is in progress, reading data from the device will result in I/ Oe toggling between one and zero. However, once the write is complete, I/O6 stops toggling and valid data can be read from the device. Figure 7. DATA Polling X CE Kf \ ff ( 1 a? WE \ / t CEH ey le toe ves OE No o two > VO7 DIN =X DouT = X 28C512/513 F10 Figure 8. Toggle Bit NY wh a [ cE VA \VSI NS XS VS VS NS KR tOEH > e-toe tOES +> OE NS VSI \S\VS\S \S Faw rrr lo\_ft 10g (1) \ \ (1) { twe Note: (1) Beginning and ending state of I/Og is indeterminate. Y 28C512/513 F11 Stock No. 21079-01 2/98 8-118Advanced CAT28C512/513 HARDWARE DATA PROTECTION The following is a list of hardware data protection fea- tures that are incorporated into the CAT28C51 2/513. (1) Vec sense provides for write protection when Vcc falls below 3.5V min. (2) A power on delay mechanism, tint (see AC charac- teristics), provides a 5 to 10 ms delay before a write sequence, after Vcc has reached 3.5V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. SOFTWARE DATA PROTECTION The CAT28C512/513 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28C512/513 is in the standard operating mode). Figure 9. Write Sequence for Activating Software Data Protection WRITE DATA: AA ADDRESS: 5555 y WRITE DATA: 55 ADDRESS: 2AAA WRITE DATA: AO ADDRESS: 5555 SOFTWARE DATA (1) PROTECTION ACTIVATED ! WRITE DATA: XX TO ANY ADDRESS L WRITE LAST BYTE TO LAST ADDRESS 5096 FHD Fos Note: Figure 10. Write Sequence for Deactivating Software Data Protection WRITE DATA: AA ADDRESS: 5555 WRITE DATA: 55 ADDRESS: 2AAA WRITE DATA: 80 ADDRESS: 5555 WRITE DATA: AA ADDRESS: 5555 WRITE DATA: 55 ADDRESS: 2AAA WRITE DATA: 20 ADDRESS: 5555 5096 FHD Foo (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within taic Max., after SDP activation. 8-119 Stock No. 21079-01 2/98CAT28C512/513 Advanced To activate the software data protection, the device must be sentthree write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transi- tions. This gives the user added inadvertent write pro- tection on power-up in addition to the hardware protec- tion provided. To allow the user the ability to program the device with an E2PROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. Figure 11. Software Data Protection Timing DATA AA 55 ADDRESS 5555 2AAA I CE __ 4 WE two > WRITES ENABLED 5096 FHD F13 Figure 12. Resetting Software Data Protection Timing DATA AA 55 80 ADDRESS 5555 2AAA 5555 AA 55 20 two -| SDP 5555 2AAA 5555 RESET ee 7\S\S\/ \S\S\ ~ DEVICE UNPROTECTED I \ 95 We LS \S VS VS 5096 FHD F14 ORDERING INFORMATION | Prefix | Device # | Suffix | CAT 280512 H N | -15 T A A A | A | Product Temperature Range Tape & Reel Number Blank = Commercial (0C to +70C) T: 500/Reel 280512 | = Industrial (-40C to +85C) 280513 A = Automotive (-40 to +105C)* Optional Endurance Package Speed Company Blank = 10,000 Cycle P: PDIP 12:120ns ID H = 100,000 Cycle N: PLCC 15: 150ns T14: TSOP (10mmx14mm) * -40C to +125C is available upon request Notes: 28C512/513 F16 (1) The device used in the above example is a CAT28C512HNI-15T (100,000 Cycle Endurance, PLCC, Industrial temperature, 150 ns Access Time, Tape & Reel). (2) 28C513 is offered only in PLCC package. Stock No. 21079-01 2/98 8-120