AC164335 - Microchip Technology

dsPIC30F1010/202X

Data Sheet

28/44-Pin High-Performance

Switch Mode Power Supply

Digital Signal Controllers

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART ,

PRO MAT E, Pow erSmart, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

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Company are registered trademarks of Microchip Technology

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In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

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PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

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SQTP is a service mark of Microchip Technology Incorporated

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All other trademarks mentioned herein are property of their

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dsPIC30F1010/202X

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized in struction set architecture

• 83 base instructions wit h flexible addressing

modes

• 24-bit wide instructions, 16-bit wide data path

• 12 Kbytes on -chip Flash p rogr am spac e

• 512 bytes on-chip data RAM

• 16 x 16-bit working register array

• Up to 30 MIPS operation:

- Dual Internal RC

- 9.7 and 14.55 MHz (±1%) Industrial Temp

- 6.4 and 9.7 MHz (±1%) Extended Temp

- 32X PLL with 480 MHz VCO

- PLL inputs ±3%

- External EC clock 6.0 to 14.55 MHz

- HS Cr ystal mode 6.0 to 14 .55 MHz

• 32 interrupt sources

• Three external interrupt sources

• 8 user-selectable priority levels for each interrupt

• 4 processor exceptions and software traps

DSP Engine Features:

• Modulo and Bit-Reversed modes

• Two 40-bit wide accumulators with optional

saturati on log ic

• 17-bit x 17-bit si ngl e-c ycle hard w are frac tio nal /

integer multiplier

• Single-cycle Multiply-Accumulate (MAC)

operation

• 40-stage Barrel Shifter

• Dual data fetch

Peripheral Feat ures:

• High-current sink/source I/O pins: 25 mA/25 mA

• Three 16-bit timers/counters; optionally pair up

16-bit timers into 32-bit timer modules

• One 16-bit Capture input functions

• Two 16-bit Compare/PWM output functions

- Dual Compare mode available

• 3-wire SPI modules (supports 4 Frame modes)

•I

2CTM module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• UART Module:

- Supports RS-232, RS-485 and LIN 1.2

- Supports IrD A® with on-chip hardware endec

- Auto wake-up on Start bit

- Auto-Baud Detect

- 4-level FIFO buffer

Power Supply PWM Module Features:

• Four P WM generators with 8 outputs

• Each PWM gen era t or h as independ ent tim e b as e

and duty cycle

• Duty cy cle re solution of 1.1 ns at 30 MIPS

• Individual dead time for each PWM generator:

- Dead-time resolution 4.2 ns at 30 MIPS

- Dead time for rising and falling edges

• Phase-shift resolut ion of 4.2 ns @ 30 MIPS

• Frequency resolution of 8.4 ns @ 30 MIPS

• PWM modes supported:

- Complementary

-Push-Pull

- Multi-Phase

- Variable Phase

- Current Reset

- Current-Limit

• Independent Current-Limit and Fault Inputs

• Output Override Control

• Special Ev ent Trigge r

• PWM generated ADC Trigger

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

28/44-Pin dsPIC30F1010/202X Enhanced Flash

SMPS 16-Bit Digital Signal Controller

dsPIC30F1010/202X

Analog Features:

ADC

• 10-bit resolution

• 2000 Ksps conve rsi on rate

• Up to 12 input channels

• “Conversion pairing” allows simultaneous conver-

sion of two input s (i.e ., curren t and volt age) wit h a

single trigger

• PWM control loop:

- Up to six conversion pairs available

- Each conversion pair has up to four PWM

and seven other selectable trigger sources

• Interrupt hardware supports up to 1M interrupts

per second

COMPARATOR

• Four Analog Comparators:

- 20 ns response time

- 10-bit DAC reference generator

- Programmable output polarity

- Selectable input source

- ADC sample and co nvert capable

• PWM module interface

- PWM Duty Cycle Control

- PWM Period Contr ol

- PWM Fault Detect

• Specia l Event Trigger

• PWM-generated ADC Trigger

Special Microcontroller Features:

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for

industrial temperature range, 100k (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip low

power RC oscillator for reliable operation

• Fail- Safe cl ock monitor operation

• Detects clock failure and switches to on-chip low

power RC oscillator

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

• Selectable Power Managem ent mo des

- Sleep, Idle and Alternate Clock modes

CMOS Technology:

• Low-power, high-speed Flash technology

• 3.3V and 5.0V operati on (±10%)

• Industrial and Extended te mperature ranges

• Low power consumption

dsPIC30F SWITCH MODE POWER SUPPLY FAMILY

Product

Pins

Packaging

Program

Memory

(Bytes)

Data SRAM

(Bytes)

Timers

Capture

Compare

UART

SPI

I2C™

PWM

ADCs

S & H

A/D

Inputs

Analog

Comparators

GPIO

dsPIC30F101028SDIP 6K 2562011112x2136 ch 2 21

dsPIC30F101028SOIC 6K 2562011112x2136 ch 2 21

dsPIC30F1010 28

QFN-S

6K 2562011112x2136 ch 2 21

dsPIC30F202028SDIP12K5123121114x2158 ch 4 21

dsPIC30F202028SOIC12K5123121114x2158 ch 4 21

dsPIC30F2020 28

QFN-S

12K5123121114x2158 ch4 21

dsPIC30F202344QFN12K5123121114x21512 ch4 35

dsPIC30F202344TQFP12K5123121114x21512 ch4 35

dsPIC30F1010/202X

Pin Diagrams

28-Pin SDIP and SOIC

dsPIC30F1010

MCLR

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

RE4

RE5V

AN0/CMP1A/CN2/RB0

AN1/CMP1B/CN3/RB1

AN2/CMP1C/CMP2A/CN4/RB2

PGD2/EMUD2/SCK1/SFLT3/INT2/RF6 PGC2/EMUC2/OC1/SFLT1/INT1/RD0

PGC1/EMUC1/EXTREF/T1CK/U1ARX/CN0/RE6

PGD1/EMUD1/T2CK/U1ATX/CN1/RE7 V

OSC2/CLKO/RB7

OSC1/CLKI/RB6 V

SFLT2/INT0/OCFLTA/RA9

PGC/EMUC/SDI1/SDA/U1RX/RF7

PGD/EMUD/SDO1/SCL/U1TX/RF8

AN5/CMP2D/CN7/RB5

AN4/CMP2C/CN6/RB4

AN3/CMP1D/CMP2B/CN5/RB3

28-Pin QFN-S

1011

121314 15

716

232425262728

dsPIC30F1010

PGD1/EMUD1/T2CK/U1ATX/CN1/RE7

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

RE4

RE5

PGC/EMUC/SDI1/SDA/U1RX/RF7

PGD/EMUD/SDO1/SCL/U1TX/RF8

SFLT2/INT0/OCFLTA/RA9

PGC2/EMUC2/OC1/SFLT1/INT1/RD0

MCLR

AN0/CMP1A/CN2/RB0

AN1/CMP1B/CN3/RB1

AN2/CMP1C/CMP2A/CN4/RB2

AN3/CMP1D/CMP2B/CN5/RB3

AN4/CMP2C/CN6/RB4

AN5/CMP2D/CN7/RB5

OSC1/CLKI/RB6

OSC2/CLKO/RB7

PGC1/EMUC1/EXTREF/T1CK/U1ARX/CN0/RE6

PGD2/EMUD2/SCK1/SFLT3/INT2/RF6

dsPIC30F1010/202X

Pin Diagrams

28-Pin SDIP and SOIC

dsPIC30F2020

MCLR

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5V

AN0/CMP1A/CN2/RB0

AN1/CMP1B/CN3/RB1

AN2/CMP1C/CMP2A/CN4/RB2

PGD2/EMUD2/SCK1/SFLT3/OC2/INT2/RF6 PGC2/EMUC2/OC1/SFLT1/IC1/INT1/RD0

PGC1/EMUC1/EXTREF/PWM4L/T1CK/U1ARX/CN0/RE6

PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7 V

AN7/CMP3D/CMP4B/OSC2/CLKO/RB7

AN6/CMP3C/CMP4A/OSC1/CLKI/RB6 V

SFLT2/INT0/OCFLTA/RA9

PGC/EMUC/SDI1/SDA/U1RX/RF7

PGD/EMUD/SDO1/SCL/U1TX/RF8

AN5/CMP2D/CMP3B/CN7/RB5

AN4/CMP2C/CMP3A/CN6/RB4

AN3/CMP1D/CMP2B/CN5/RB3

28-Pin QFN-S

1011

121314 15

716

232425262728

dsPIC30F2020

PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5

PGC/EMUC/SDI1/SDA/U1RX/RF7

PGD/EMUD/SDO1/SCL/U1TX/RF8

SFLT2/INT0/OCFLTA/RA9

PGC2/EMUC2/OC1/SFLT1/IC1/INT1/RD0

MCLR

AN0/CMP1A/CN2/RB0

AN1/CMP1B/CN3/RB1

AN2/CMP1C/CMP2A/CN4/RB2

AN3/CMP1D/CMP2B/CN5/RB3

AN4/CMP2C/CMP3A/CN6/RB4

AN5/CMP2D/CMP3B/CN7/RB5

AN6/CMP3C/CMP4A/OSC1/CLKI/RB6

AN7/CMP3D/CMP4B/OSC2/CLKO/RB7

PGC1/EMUC1/EXTREF/PWM4L/T1CK/U1ARX/CN0/RE6

PGD2/EMUD2/SCK1/SFLT3/OC2/INT2/RF6

dsPIC30F1010/202X

Pin Diagrams

44-PIN QFN

dsPIC30F2023

434241 40393837 3635

121314 15161718 192021

330

232

AN4/CMP2C/CMP3A/CN6/RB4

AN5/CMP2D/CMP3B/CN7/RB5

AN6/CMP3C/CMP4A/OSC1/CLKI/RB6

AN7/CMP3D/CMP4B/OSC2/CLKO/RB7

AN8/CMP4C/RB8

AN10/IFLT4/RB10

AN11/IFLT2/RB11

PGD/EMUD/SDO1/RF8

AN9/EXTREF/CMP4D/RB9

PGC2/EMUC2/OC1/IC1/INT1/RD0

PGC1/EMUC1/PWM4L/T1CK/U1ARX/CN0/RE6

OC2/RD1

SFLT2/INT0/OCFLTA/RA9

PGD2/EMUD2/SCK1/INT2/RF6

SFLT1/RA8

PGD1/EMUD1

PWM4H/T2CK/U1ATX/CN1/RE7

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5

SYNCO/SS1/RF15

SDA/RG3

SFLT4/RA11

SFLT3/RA10

PGC/EMUC/SDI1/RF7

PWM2L/RE2 AN3/CMP1D/CMP2B/CN5/RB3

AN2/CMP1C/CMP2A/CN4/RB2

AN1/CMP1B/CN3/RB1

AN0/CMP1A/CN2/RB0

MCLR

U1RX/RF2

PWM1L/RE0

PWM1H/RE1

SYNCI/RF14

U1TX/RF3

SCL/ RG2

dsPIC30F1010/202X

Pin Diagrams

PGD/EMUD/SDO1/RF8

AN9/EXTREF/CMP4D/RB9

PGC2/EMUC2/OC1/IC1/INT1/RD0

PGC1/EMUC1/PWM4L/T1CK/U1ARX/CN0/RE6

SYNCI/RF14

SFLT2/INT0/OCFLTA/RA9

PGD2/EMUD2/SCK1/INT2/RF6

SFLT1/RA8

AN3/CMP1D/CMP2B/CN5/RB3

AN2/CMP1C/CMP2A/CN4/RB2

AN1/CMP1B/CN3/RB1

AN0/CMP1A/CN2/RB0

MCLR

U1RX/RF2

PWM1L/RE0

PWM1H/RE1

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5

SDA/RG3

SFLT4/RA11

SFLT3/RA10

PGC/EMUC/SDI1/RF7

AN4/CMP2C/CMP3A/CN6/RB4

AN5/CMP2D/CMP3B/CN7/RB5

AN6/CMP3C/CMP4A/OSC1/CLKI/RB6

AN7/CMP3D/CMP4B/OSC2/CLKO/RB7

AN8/CMP4C/RB8

SYNCO/SS1/RF15

SCL/RG2

U1TX/RF3

PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7

dsPIC30F2023

PWM2L/RE2

OC2/RD1

AN11/IFLT2/RB11

AN10/IFLT4/RB10

44-Pin TQFP

© 2006 Microchip Technology Inc. Preliminary DS70178C-page 7
dsPIC30F1010/202X
Table of Contents
0 Device Overview .......................................................................................................................................................................... 9
0 CPU Architecture Overview........................................................................................................................................................ 19
0 Memory O rganization. ................................................................................................................................................................ 29
0 Address Generato r Units............................................................................................................................................................ 41
0 Interrupts.................................................................................................................................................................................... 47
0 I/O Ports .............. ....................... ....................... ....................... .................................................................................................. 77
0 Flash Pro g ram Memory........................ .............................. ............................. ........................................................................... 81
0 Timer1 Module ........................................................................................................................................................................... 87
0 Timer2/3 Module ........... .. .... .. ....... .. .. .. .... .. .. ....... .. .. .... .. .. .. ....... .. .. .... .. .. .. ....... .. .... .. .. .. ....... ............................................................ 91
0 Input Capture Module............................. .... ..... .... .. .. .... .. .. ....... .. .... .. .. .... ..... .... .. .. .... .. .. ....... .......................................................... 97
0 Output Compa re Module................ ............................. ................... ................... ....................................................................... 101
0 Power Supply PWM .......................................... .... .... .. .... ....... .... .. .... .. ......... .. .... .. .... .. ............................................................... 107
0 Serial Peripheral Interf ace (SP I)............................................................................................................................................... 145
0 I2C™ Module ........................................................................................................................................................................... 153
0 U nivers al Asynchr onous Receiver  Transmi tter (UART) Module .............................................................................................. 161
0 10-bit 2 Msps Analog-to-Digital Converter (ADC) Module........................................................................................................ 169
0 SMPS Comparator Module .................. .. .. ....... .... .. .... .. .. ....... .... .. .. .... .. ....... .... .. .. .... .. .. ....... .... .. .................................................. 191
0 System Inte g r a tion ................ .............................. ................... ................... ................... ............................................................ 197
0 Instruction Set Summary.......................................................................................................................................................... 219
0 Development Support............................................................................................................................................................... 227
0 Electrical Characteristics.......................................................................................................................................................... 231
0 Pac kage Mark ing  Information................................................................................................................................................... 267

dsPIC30F1010/202X

TO OUR VALUED CUSTOMERS

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Customer Noti fic atio n Syst em

dsPIC30F1010/202X

1.0 DEVICE OVERVIEW This document contains device specific information for

the dsPIC30F1010/202X SMPS devices. Thes e devices

contain extensive Digital Signal Processor (DSP) func-

tionality within a high-performance 16-bit microcontroller

(MCU) architecture, as reflected in the following block

diagrams. Figure 1-1 and Table 1-1 describe the

dsPIC30F1010 SMPS device, Figure 1-2 and Table 1-2

describe the dsPIC30F2020 device and Figure 1-3 and

Table 1-3 describe the dsPIC30F2023 SMPS device.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

dsPIC30F1010/202X

FIGU RE 1-1 : dsPI C30F 1010 BLO CK DI AGRAM

Power-up

Timer

Oscillator

Start-up Timer

POR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLK1

MCLR

AN4/CMP2C/CN6/RB4

UART1SPI1 SMPS

PWM

Timing

Generation

AN5/CMP2D/CN7/RB5

PCH PCL

Program Counter

ALU<16>

Address Latch

Prog ram Memory

(12 Kbytes)

Data Latch

X Data Bus

I2C™

Comparator

PCU

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

RE4

10-bit ADC

Timers

RE5

PGC1/EMUC1/EXTREF/T1CK/

Output

Compare

Module

SFLT2/INT0/OCFLTA/RA9

PORTB

PGC/EMUC/SDI1/SDA/U1RX/RF7

PGD/EMUD/SD01/SCL/U1TX/RF8

PORTF

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effecti ve Address

X RAGU

X WAGU

Y AGU AN0/CMP1A/CN2/RB0

AN1/CMP1B/CN3/RB1

AN2/CMP1C/CMP2A/CN4/RB2

AN3/CMP1D/CMP2B/CN5/RB3

PORTA

PORTE

Interrupt

Controller

PSV & Table

Data Access

Control Bloc k

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(256 bytes )

RAM X Data

(256 bytes)

RAM

Address

Latch

Address

Latch

Control Signals

to Variou s Blocks

PGC2/EMUC2/OC1/SFLT1/

OSC1/CLKI/RB6

OSC2/CLKO/RB7

INT1/RD0

PGD2/EMUD2/SCK1/SFLT3/

INT2/RF6

PGD1/EMUD1/T2CK/U1ATX/

Module

Input

Change

Notification U1ARX/CN0/RE6

CN1/RE7

dsPIC30F1010/202X

Table 1-1 provides a brief description of device I/O

pinouts for the dsPIC30F1010 and the functions that

may be multiplexed to a port pin. Multiple functions may

exist on one port pin. When multiplexing occurs, the

peripheral module’s functional requirem ents may force

an override of the data direction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS FOR dsPIC30F1010

Pin Name Pin

Type Buffer

Type Description

AN0-AN5 I Analog Analog input channels.

AVDD P P Positive supply for analog module.

AVSS P P Ground reference for analog module.

CLKI

CLKO I

OST/CMOS

—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillat or mode. O ptionally function s as CLKO i n RC and EC m odes. Alway s

associated wit h OSC2 pin function.

EMUD

EMUC

EMUD1

EMUC1

EMUD2

EMUC2

I/O

ICD Primary Communication Channel data input/output pin.

ICD Primary Communication Channel clock input/output pin.

ICD Secondary Communication Channel data input/output pin.

ICD Secondary Communication Channel clock input/output pin.

ICD Tertiary Communication Channel data input/output pin.

ICD Tertiary Communication Channel clock input/output pin.

INT0

INT1

INT2

External int errup t 0

External int errup t 1

External int errup t 2

SFLT1

SFLT2

SFLT3

PWM1L

PWM1H

PWM2L

PWM2H

—

Shared Fault Pin 1

Shared Fault Pin 2

Shared Fault Pin 3

PWM 1 Low output

PWM 1 High output

PWM 2 Low output

PWM 2 High output

MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an

active low Reset to the device.

OC1 O — Compare outputs.

OCFLTA I ST Output Compare Fault Pin

OSC1

OSC2 I

I/O CMOS

—Oscillator crystal input.

Oscil lator crys tal o utput. Co nnect s to crys tal or resona tor in Cr ystal Oscillato r

mode. Optionally functions as CLKO in FRC and EC modes.

PGD

PGC

PGD1

PGC1

PGD2

PGC2

I/O

I/0

In-Circuit Serial Programming™ data input/output pin.

In-Circuit Serial Programming clock input pin.

In-C ircuit Seria l Programming data in put/output pin 1.

In-Circuit Serial Programming clock input pin 1.

In-C ircuit Seria l Programming data in put/output pin 2.

In-Circuit Serial Programming clock input pin 2.

RB0-RB7 I/O ST PORTB is a bidirectional I/O port.

RA9 I/O ST PORTA is a bidirectional I/O port.

RD0 I/O ST PORTD is a bidirectional I/O port.

Legend: CMOS = CMOS compat ible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F1010/202X

RE0-RE7 I/O ST PORTE is a bidirectional I/O port.

RF6, RF7, RF8

I/O ST PORTF is a bidirectional I/O port.

SCK1

SDI1

SDO1

I/O

—

Synchronous serial clock input/output for SPI #1.

SPI #1 Data In.

SPI #1 Data Out.

SCL

SDA I/O

I/O ST

ST Synchronous serial clock input/output for I2C™.

Synchronous serial data input/output for I2C.

T1CK

T2CK I

IST

ST Timer1 external clock input.

Timer2 external clock input.

U1RX

U1TX

U1ARX

U1ATX

—

UART1 Receive.

UART1 Tr an smit.

Alternate U ART1 Receive.

Alternate U AR T1 Transmit.

CMP1A

CMP1B

CMP1C

CMP1D

CMP2A

CMP2B

CMP2C

CMP2D

Analog

Comparator 1 Channel A

Comparator 1 Channel B

Comparator 1 Channel C

Comparator 1 Channel D

Comparator 2 Channel A

Comparator 2 Channel B

Comparator 2 Channel C

Comparator 2 Channel D

CN0-CN7 I ST Input Change notification inputs

Can be software programme d for internal weak pull-ups on all inputs.

VDD P — Positive supply for logic and I/O pins.

VSS P — Ground reference for logic and I/O pins.

EXTREF I Analog External reference to Comparator DAC

TABLE 1-1: PINOUT I/O DESCRIPTIONS FOR dsPIC30F1010 (CONTINUED)

Pin Name Pin

Type Buffer

Type Description

Legend: CMOS = CMOS compat ible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F1010/202X

FIGURE 1-2: dsPIC30F2020 BLOCK DIAGRAM

Power-up

Timer

Oscillator

Start-up Timer

POR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLK1

MCLR

AN4/CMP2C/CMP3A/CN6/RB4

UART1SPI1 SMPS

PWM

Timing

Generation

AN5/CMP2D/CMP3B/CN7/RB5

PCH PCL

Program Counter

ALU<16>

Address Latch

Prog ram Memory

(12 Kbytes)

Data Latch

X Data Bus

I2C™

Comparator

PCU

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

10-bit ADC

Timers

PWM3H/RE5

PGC1/EMUC1/EXTREF/PWM4L/

Input

Capture

Module

Output

Compare

Module

SFLT2/INT0/OCFLTA/RA9

PORTB

PGC/EMUC/SDI1/SDA/U1RX/RF7

PGD/EMUD/SD01/SCL/U1TX/RF8

PORTF

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effecti ve Address

X RAGU

X WAGU

Y AGU AN0/CMP1A/CN2/RB0

AN1/CMP1B/CN3/RB1

AN2/CMP1C/CMP2A/CN4/RB2

AN3/CMP1D/CMP2B/CN5/RB3

PORTA

PORTE

Interrupt

Controller

PSV & Table

Data Access

Control Bloc k

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(256 bytes )

RAM X Data

(256 bytes)

RAM

Address

Latch

Address

Latch

Control Signals

to Variou s Blocks

PGC2/EMUC2/OC1/SFLT1/IC1/

AN6/CMP3C/CMP4A/

AN7/CMP3D/CMP4B/

OSC1/CLKI/RB6

OSC2/CLKO/RB7

INT1/RD0

PGD2/EMUD2/SCK1/SFLT3/OC2

INT2/RF6

PGD1/EMUD1/PWM4H/T2CK/

Module

Input

Change

Notification U1ARX/CN0/RE6

U1ATX/CN1/RE7

T1CK/

dsPIC30F1010/202X

Table 1-2 provides a brief description of device I/O

pinouts for the dsPIC30F2020 and the functions that

may be multiplexed to a port pin. Multiple functions may

exist on one port pin. When multiplexing occurs, the

periphe ral mo dule’s functional requir ements may force

an override of the data direction of the port pin.

TABLE 1-2: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2020

Pin Name Pin

Type Buffer

Type Description

AN0-AN7 I Analog Analog input channels.

AVDD P P Positive supply for analog module.

AVSS P P Ground reference for analog module.

CLKI

CLKO I

OST/CMOS

—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillat or mode. O ptionally function s as CLKO in RC and EC mode s. Always

associated wit h OSC2 pin function.

EMUD

EMUC

EMUD1

EMUC1

EMUD2

EMUC2

I/O

ICD Primary Communication Channel data input/output pin.

ICD Primary Communication Channel clock input/output pin.

ICD Secondary Communication Channel data input/output pin.

ICD Secondary Communication Channel clock input/output pin.

ICD Tertiary Communication Channel data input/output pin.

ICD Tertiary Communication Channel clock input/output pin.

IC1 I ST Capture input.

INT0

INT1

INT2

External int errup t 0

External int errup t 1

External int errup t 2

SFLT1

SFLT2

SFLT3

PWM1L

PWM1H

PWM2L

PWM2H

PWM3L

PWM3H

PWM4L

PWM4H

—

Shared Fault Pin 1

Shared Fault Pin 2

Shared Fault Pin 3

PWM 1 Low output

PWM 1 High output

PWM 2 Low output

PWM 2 High output

PWM 3 Low output

PWM 3 High output

PWM 4 Low output

PWM 4 High output

MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an

active low Reset to the device.

OC1-OC2

OCFLTA O

I— Compare outputs.

Output Compare Fault pin

OSC1

OSC2 I

I/O CMOS

—Oscillator crystal input.

Oscil lator crys tal o utput. Co nnect s to crys tal or resona tor in Cr ystal Oscillato r

mode. Optionally functions as CLKO in FRC and EC modes.

PGD

PGC

PGD1

PGC1

PGD2

PGC2

I/O

In-Circuit Serial Programming™ data input/output pin.

In-Circuit Serial Programming clock input pin.

In-C ircuit Serial Progr amming data input/output pi n 1.

In-Circuit Serial Programming clock input pin 1.

In-C ircuit Serial Progr amming data input/output pi n 2.

In-Circuit Serial Programming clock input pin 2.

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F1010/202X

RB0-RB7 I/O ST PORTB is a bidirectional I/O port.

RA9 I/O ST PORTA is a bidirectional I/O port.

RD0 I/O ST PORTD is a bidirectional I/O port.

RE0-RE7 I/O ST PORTE is a bidirectional I/O port.

RF6, RF7, RF8

I/O ST PORTF is a bidirectional I/O port.

SCK1

SDI1

SDO1

I/O

—

Synchronous serial clock input/output for SPI #1.

SPI #1 Data In.

SPI #1 Data Out.

SCL

SDA I/O

I/O ST

ST Synchronous serial clock input/output for I2C™.

Synchronous serial data input/output for I2C.

T1CK

T2CK I

IST

ST Timer1 external clock input.

Timer2 external clock input.

U1RX

U1TX

U1ARX

U1ATX

—

UART1 Receive.

UART1 Tr an smit.

Alternate U ART1 Receive.

Alternate U AR T1 Transmit.

CMP1A

CMP1B

CMP1C

CMP1D

CMP2A

CMP2B

CMP2C

CMP2D

CMP3A

CMP3B

CMP3C

CMP3D

CMP4A

CMP4B

Analog

Comparator 1 Channel A

Comparator 1 Channel B

Comparator 1 Channel C

Comparator 1 Channel D

Comparator 2 Channel A

Comparator 2 Channel B

Comparator 2 Channel C

Comparator 2 Channel D

Comparator 3 Channel A

Comparator 3 Channel B

Comparator 3 Channel C

Comparator 3 Channel D

Comparator 4 Channel A

Comparator 4 Channel B

CN0-CN7 I ST Input Change notification inputs

Can be software programme d for internal weak pull-ups on all inputs.

VDD P — Positive supply for logic and I/O pins.

VSS P — Ground reference for logic and I/O pins.

EXTREF I Analog External reference to Comparator DAC

TABLE 1-2: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2020 (CONTINUED)

Pin Name Pin

Type Buffer

Type Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F1010/202X

FIGU RE 1-3 : dsPI C30F 2023 BLO CK DI AGRAM

Power-up

Timer

Oscillator

Start-up Timer

POR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLK1

MCLR

AN4/CMP2C/CMP3A/CN6/RB4

UART1SPI1 Power Supply

PWM

Timing

Generation

AN5/CMP2D/CMP3B/CN7/RB5

PCH PCL

Program Counter

ALU<16>

Address Latch

Prog ram Memory

(12 Kbytes)

Data Latch

X Data Bus

I2C™

Comparator

PCU

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

10-bit ADC

Timers

PWM3H/RE5

PGC1/EMUC1/PWM4L/T1CK/

Input

Capture

Module

Output

Compare

Module

PORTB

SCL/RG2

SDA/RG3

PORTG

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effecti ve Address

X RAGU

X WAGU

Y AGU AN0/CMP1A/CN2/RB0

AN1/CMP1B/CN3/RB1

AN2/CMP1C/CMP2A/CN4/RB2

AN3/CMP1D/CMP2B/CN5/RB3

PORTA

PORTE

Interrupt

Controller

PSV & Table

Data Access

Control Bloc k

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(256 bytes )

RAM X Data

(256 bytes)

RAM

Address

Latch

Address

Latch

Control Signals

to Variou s Blocks

OC2/RD1

AN6/CMP3C/CMP4A/

AN7/CMP3D/CMP4B/

OSC1/CLKI/RB6

OSC2/CLKO/RB7

PGD1/EMUD1/PWM4H/T2CK/

Module

SFLT1/RA8

SFLT2/INT0/OCFLTA/RA9

SFLT3/RA10

PGC/EMUC/SDI1/RF7

PGD/EMUD/SD01/RF8

PORTF

PGD2/EMUD2/SCK1/INT2/RF6

AN8/CMP4C/RB8

AN9/EXTREF/CMP4D/RB9

AN10/IFLT4/RB10

AN11/IFLT2/RB11

SYNCI/RF14

PGC2/EMUC2/OC1/IC1/INT1/

SFLT4/RA11

SYNCO/SSI/RF15

U1TX/RF3

U1RX/RF2

Input

Change

Notification

U1ARX/CN0/RE6

U1ATX/CN1/RE7

RD0

dsPIC30F1010/202X

Table 1-3 provides a brief description of device I/O

pinouts for the dsPIC30F2023 and the functions that

may be multiplexed to a port pin. Multiple functions may

exist on one port pin. When multiplexing occurs, the

peripheral module’s functional requirem ents may force

an override of the data direction of the port pin.

TABLE 1-3: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2023

Pin Name Pin

Type Buffer

Type Description

AN0-AN11 I Analog Analog input channels.

AVDD P P Positive supply for analog module.

AVSS P P Ground reference for analog module.

CLKI

CLKO I

OST/CMOS

—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillat or mode. O ptionally function s as CLKO in R C and EC mo des. Always

associated with OSC2 pin function.

EMUD

EMUC

EMUD1

EMUC1

EMUD2

EMUC2

I/O

ICD Primary Communication Channel data input/output pin.

ICD Primary Communication Channel clock input/output pin.

ICD Secondary Communication Channel data input/output pin.

ICD Secondary Communication Channel clock input/output pin.

ICD Tertiary Communication Channel data input/output pin.

ICD Tertiary Communication Channel clock input/output pin.

IC1 I ST Capture input.

INT0

INT1

INT2

External int errup t 0

External int errup t 1

External int errup t 2

SFLT1

SFLT2

SFLT3

SFLT4

IFLT2

IFLT4

PWM1L

PWM1H

PWM2L

PWM2H

PWM3L

PWM3H

PWM4L

PWM4H

—

Shared Fault 1

Shared Fault 2

Shared Fault 3

Shared Fault 4

Independent Fault 2

Independent Fault 4

PWM 1 Low output

PWM 1 High output

PWM 2 Low output

PWM 2 High output

PWM 3 Low output

PWM 3 High output

PWM 4 Low output

PWM 4 High output

SYNCO

SYNCI O

I—

ST PWM SYNC output

PWM SYNC input

MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an

active low Reset to the device.

OC1-OC2

OCFLTA O

I—

ST Compare outputs.

Output Compare Fault condition.

OSC1

OSC2 I

I/O CMOS

—Oscillator crystal input.

Oscil lator crys tal o utput. Co nnect s to crys tal or resona tor in Cr ystal Oscillato r

mode. Optionally functions as CLKO in FRC and EC modes.

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F1010/202X

PGD

PGC

PGD1

PGC1

PGD2

PGC2

I/O

In-Circuit Serial Programming™ data input/output pin.

In-Circuit Serial Programming clock input pin.

In-C ircuit Seria l Programming data in put/output pin 1.

In-Circuit Serial Programming clock input pin 1.

In-C ircuit Seria l Programming data in put/output pin 2.

In-Circuit Serial Programming clock input pin 2.

RA8-RA11 I/O ST PORTA is a bidirectional I/O port.

RB0-RB11 I/O ST PORTB is a bidirectional I/O port.

RD0,RD1 I/O ST PORTD is a bidirectional I/O port.

RE0-RE7 I/O ST PORTE is a bidirectional I/O port.

RF2, RF3,

RF6-RF8, RF14,

RF15

I/O ST PORTF is a bidirectional I/O port.

RG2, RG3 I/O ST PORTG is a bidirectional I/O port.

SCK1

SDI1

SDO1

SS1

I/O

—

Synchronous serial clock input/output for SPI #1.

SPI #1 Data In.

SPI #1 Data Out.

SPI #1 Slave Synchroniz ati on .

SCL

SDA I/O

I/O ST

ST Synchronous serial clock input/output for I2C.

Synchronous serial data input/output for I2C.

T1CK

T2CK I

IST

ST Timer1 external clock input.

Timer2 external clock input.

U1RX

U1TX

U1ARX

U1ATX

—

UART1 Receive.

UART1 Tr an smit.

Alternate U ART1 Receive.

Alternate U AR T1 Transmit

CMP1A

CMP1B

CMP1C

CMP1D

CMP2A

CMP2B

CMP2C

CMP2D

CMP3A

CMP3B

CMP3C

CMP3D

CMP4A

CMP4B

CMP4C

CMP4D

Analog

Comparator 1 Channel A

Comparator 1 Channel B

Comparator 1 Channel C

Comparator 1 Channel D

Comparator 2 Channel A

Comparator 2 Channel B

Comparator 2 Channel C

Comparator 2 Channel D

Comparator 3 Channel A

Comparator 3 Channel B

Comparator 3 Channel C

Comparator 3 Channel D

Comparator 4 Channel A

Comparator 4 Channel B

Comparator 4 Channel C

Comparator 4 Channel D

CN0-CN7 I ST Input Change notification inputs

Can be software programme d for internal weak pull-ups on all inputs.

VDD P — Positive supply for logic and I/O pins.

VSS P — Ground reference for logic and I/O pins.

EXTREF I Analog External reference to Comparator DAC

TABLE 1-3: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2023 (CONTINUED)

Pin Name Pin

Type Buffer

Type Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F1010/202X

2.0 CPU ARCHITECTURE

OVERVIEW

2.1 Core Overview

The core has a 24-bit instruction word. The Program

Counter (PC) is 23 bits wide with the Least Significant

bit (LSb) always clear (see Section 3.1 “Program

Address Space”), and the Most Significant bit (MSb)

is ign ored du ring no rmal program executi on, ex cept for

certain specialized instructions. Thus, the PC can

address up to 4M instruction words of user program

space. An instruction prefetch mechanism is used to

help maintain throughput. Program loop constructs,

free from loop count management overhead, are sup-

ported using the DO and REPEAT instructions, both of

which are interruptible at any point.

The working register array consists of 16x16-bit regis-

ters, each of which can act as data, address or offset

registers. One working register (W15) operates as a

software Stack Pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split

into two blocks, referred to as X and Y data memory.

Each block has its own independent Address Genera-

tion Unit (AGU). Most instructions operate solely

through the X memory AGU, which provides the

appearance of a single unified data space. The

Multiply-Accumulate (MAC) class of dual source DSP

instructions operate through both the X and Y AGUs,

splitting the data address space into two parts (see

Section 3.2 “Data Address Space”). The X and Y

data space boundary is device-specific and cannot be

alter ed by the user . Each dat a word consis ts of 2 bytes,

and mos t instruction s can address data eith er as words

or bytes.

There are two methods of accessing data stored in

program memory:

• The upper 32 Kbytes of data sp ace memory can be

mapped into the lower half (user space) of program

space at any 16K program word boundary, defined

by the 8-bit Program Space Visibility Page

(PSVPAG) register. This lets any instruction access

program space as if it were data space, with a limit a-

tion that the access requires an additional cycle.

Moreover , only the lower 16 bits of each instruction

word can be accessed using this method.

• Linear indirect access of 32K word pages within

progra m spac e is also possibl e using any w orking

Table read and write instructions can be used to

access all 24 bits of an instruction word.

Overhead-free circular buffers (modulo addressing)

are supported in both X and Y address spaces. This is

primarily intended to remove the loop overhead for

DSP algorithms.

The X AGU also supports Bit-Reversed Addressing

mode on destination effective addresses, to greatly

simplify input or output data reordering for radix-2 FFT

algorith ms . Re fer to Secti on 4.0 “Address Generator

Units” for details on modulo and Bit-Reversed

Addressing.

The core s up ports Inherent (no opera nd), Relative, Lit-

eral, Memory Direct, Register Direct, Register Indirect,

Instruct ions ar e associat ed with p redefined Addressin g

modes, depending upon their functional requirements.

For m os t i ns tru c ti o ns , the c or e i s c apa bl e of e xe c ut i ng

a data (or program data) memory read, a working reg-

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, 3-operand instructions are supported, allowing

C = A + B operations to be executed in a single cycle.

A DSP engine has been included to significantly

enhance the core arithmetic capab ility and throughput.

It features a high-speed 17-bit by 17-bit multiplier, a

40-bit ALU, two 40-bit saturating accumulators and a

40-bit b idi rec tio nal b arrel shi fter. Data in the a cc um ul a-

tor or any worki ng r egist er can be shif ted up to 15 bits

right or 16 bits left in a single cycle. The DSP instruc-

tions ope rate sea mles sly with all other in struct ions an d

have be en desi gned for o ptimal re al-time p erforma nce.

The MAC class of instructions can concurrently fetch

two data operands from memory, while multiplying two

W registers. To enable this concurrent fetching of data

operands, the data space has been split for these

instructions and linear for all others. This has been

achieved in a transparent and flexible manner, by

dedicating certain working registers to each address

spac e for the MAC class of instructions.

The core does not support a multi-stage instruction

pipeline. However, a single stage instruction prefetch

mechanism is used, which accesses and partially

decodes instructions a cycle ahead of execution, in

order to maximize available execution time. Most

instructions execute in a single cycle, with certain

exceptions.

The core features a vectored exception processing

structure for traps and interrupts, with 62 independent

vectors. The exceptions consist of up to 8 traps (of

which 4 are res erv ed ) an d 54 interrupt s . Eac h in terru pt

is prioritized based on a user-assigned priority between

1 and 7 (1 being the lowest priority and 7 being the

highest) in conjunction with a predetermined ‘natural

order’. T raps hav e fixed prio rities, rangi ng from 8 to 15.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

dsPIC30F1010/202X

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and

consists of 16x16-bit working registers (W0 through

W15), 2x40-bit accumulators (ACCA and ACCB),

STATUS register (SR), Data Table Page register

(TBLPAG), Program Space Visibility Page register

(PSVPAG), DO and REPEAT registers (DOSTART,

DOEND, DCOUNT and RCOUNT), and Program

Counter (PC). The working registers can act as data,

address or offset registers. All registers are memory

mapped. W0 acts as the W register for file register

addressing.

Some of these registers have a shadow register asso-

ciated with each of them, as shown in Figure 2-1. The

shadow registe r is used as a te mporary holding register

and can tr ansfer its con ten t s t o or fro m i t s hos t reg is ter

upon the occurrence of an event. None of the shadow

registers are accessible directly. The following rules

apply for transfer of registers into and out of shadows.

•PUSH.S and POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits

only) are transferred.

•DO instruction

DOSTART, DOEND, DCOUNT shadows are

pushed on loop start, and popped on loop end.

When a byte operation is performed on a working reg-

ister, only th e Least Signific ant Byte (LSB) of the t arget

mapped working registers is that both the Least and

Most Significant Bytes (MSBs) can be manipulated

through byte wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/

FRAM E POIN TE R

The dsPIC® DSC devices contain a software stack.

W15 is the dedicated software Stack Pointer (SP), and

will be automatically modified by exception processing

and sub routine calls and returns. However , W15 can be

referenced by any instruction in the same manner as all

other W registers. This simplifies the reading, writing

and manipulation of the Stack Pointer (e.g., creating

stac k fram es ).

W15 is initialized to 0x0800 during a Reset. The user

may reprogram the SP during initialization to any

location within data space.

W14 has been dedicated as a Stack Frame Pointer as

defined by the LNK and ULNK instructions. However,

W14 can be referenced by any instruction in the same

manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS Register

(SR), the LSB of which is referred to as the SR Low

Byte (SRL) and the MSB as the SR High Byte (SRH).

See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags

(includ ing the Z bit ), as well as the CPU Inter rupt Prior-

ity Level Status bi t s , IPL <2:0 >, a nd the REPEAT ac tiv e

Status bit, RA. During exception processing, SRL is

concate na ted with the MSB of the PC to form a

complete word value, which is then stacked.

The upper byte of the STATUS register contains the

DSP Adder/Subtracter status bits , the DO Loop Active

bit (DA) and the Digit Carry (DC) Status bit.

2.2.3 PROGRA M COUNTER

The Program Counter is 23 bits wide. Bit 0 is always

clear. Therefore, the PC can address up to 4M

instruction words.

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

dsPIC30F1010/202X

FIGURE 2-1 : PRO GRAMMER’ S MOD EL

TABPAG

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP Operand

Registers

W10

W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

DSP Address

Registers

AD39 AD0AD31

DSP

Accumulators ACCA

ACCB

PSVPAG

7 0Program Space Visibility Page Address

OA OB SA SB

RCOUNT

15 0

REPEAT Loop Counter

DCOUNT

15 0

DO Loop Counter

DOSTART

22 0

DO Loop Start Address

IPL2 IPL1

SPLIM Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

15 0 Core Configuration Register

Legend

CORCON

DA DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End Address

DOEND

dsPIC30F1010/202X

2.3 Divide Support

The dsPIC DSC devices feature a 16/16-bit signed

fraction al d iv ide ope rati on , as w ell as 32/1 6-b it a nd 1 6/

16-bit signed and unsigned integer divide operations, in

the form of single instr uction iterative divides. The

following instructions and data sizes are supported:

1. DIVF – 16/16 signed fractional divide

2. DIV.sd – 32/16 signed divide

3. DIV.ud – 32/16 unsigned divide

4. DIV.sw – 16/16 signed divide

5. DIV.uw – 16/16 unsigned divide

The 16/16 divides are simila r to the 32/16 (same number

of iterations), but the dividend is eithe r zero-extended or

sign-extended during the first iteration.

The divide instructions must be executed within a

REPEAT loop. Any other form of execution (e.g. a series

of disc rete div ide ins tructions) will not function correctl y

because the instruction flow depends on RCOUNT.

The divi de instru ction does not autom aticall y set up th e

RCOUNT value, and it must, therefore, be explicitly

and correctly specified in the REPEAT instruction, as

shown in Table 2-1 (REPEAT will execute the target

instruction {operand value + 1} times). The REPEAT

loop coun t mus t be se t up for 18 ite rati ons of the DIV/

DIVF instruction. Thus, a complete divide operation

requires 19 cycles.

TABLE 2-1: DIVIDE INSTRUCTIONS

Note: The Divide flow is interruptible. However,

the user needs to save the context as

appropriate.

Instruction Function

DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1

DIV.sd Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1

DIV.ud Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1

DIV.sw Signed divide: Wm / Wn → W0; Rem → W1

DIV.uw Unsigned divide: Wm / Wn → W0; Rem → W1

dsPIC30F1010/202X

2.4 DSP Engine

The DSP engine consists of a high speed 17-bit x

17-bit mu ltiplier , a barrel shifter , and a 40-bit adder/sub-

tracter (with two target accumulators, round and

saturati on log ic ).

The DSP engine also has the capability to perform inher-

ent accumulator-to-accumulator operations, which

require no additional data. These instructions are ADD,

SUB and NEG.

The DSP engine has various options selected through

various bits in the CPU Core Configuration Register

(CORCON), as listed below:

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for ACCA (SATA).

5. Automatic saturation on/off for ACCB (SATB).

6. Automatic saturation on/off for writes to data

memory (SATDW).

7. Accumulator Saturation mode selection

(ACCSAT).

A block diagram of the DSP engine is shown in

Figure 2-2.

Note: For CORCON layout, see Table 3-3.

TABLE 2-2: DSP INSTRUCTION SUMMARY

Instruction Algebraic Operation ACC WB?

CLR A = 0 Yes

ED A = (x – y)2No

EDAC A = A + (x – y)2No

MAC A = A + (x * y) Yes

MAC A = A + x2No

MOVSAC No change in A Yes

MPY A = x * y No

MPY.N A = – x * y No

MSC A = A – x * y Yes

dsPIC30F1010/202X

FIGU RE 2-2: DSP E NGI NE BLO CK DI AGRA M

Zero Backfill

Sign-Extend

Barrel

Shifter

40-bit Accumulator A

40-bit Accumulator B Round

Logic

X Data Bus

To/From W Array

Adder

Saturate

Negate

16 16

40 40

Y Data Bus

Carry/Borrow Out

Carry/Borrow In

Multiplier/Scaler

17-bit

dsPIC30F1010/202X

2.4.1 MULTIPLIER

The 17x17-bit multiplier is capable of signed or

unsign ed ope ration an d can m ultiplex its output u sing a

scaler to support either 1.31 fractional (Q31) or 32-bit

integer results. Unsigned operands are zero-extended

into the 17th bit of the multiplier input value. Signed

operands are sign-extended into the 17th bit of the mul-

tiplier input value. The output of the 17x17-bit multiplier/

scaler is a 33-bit value, which is sign-extended to 40

bits. Integer data is inheren tly represented as a s igned

two’s complement value, where the MSB is defined as

a sign bit. Generally speaking, the range of an N-bit

two’s complement integer is -2N-1 to 2N-1 – 1. For a 16-

bit integ er, the da ta range is -32 76 8 (0x 800 0) to 3276 7

(0x7FFF), including 0. For a 32-bit integer, the data

range is -2,147,483,648 (0x8000 0000) to

2,147,48 3,6 45 (0x7 FFF FFFF).

When the multiplier is configured for fractional multipli-

cation, the data is represented as a two’s complement

fraction , where the M SB is define d as a sign b it and the

radix po int is im plied to lie just a fter the si gn bit (QX f or-

mat). The range of an N-bit two’s complement fraction

with this implied radix point is -1.0 to (1-21-N). For a

16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7FFF), including 0, and has a preci-

sion of 3 .01518 x10-5. In F ractional mode, a 16x 16 mul-

tiply operation generates a 1.31 product, which has a

precision of 4.65661x10-10.

The same multiplier is used to support the MCU multi-

ply instructions, which include integer 16-bit signed,

unsigned and mixed sign multiplies.

The MUL instruction may be directed to use byte or

word size d opera nds. By te opera nds wil l direct a 1 6-bit

result, and word operands will direct a 32-bit result to

the specified register(s) in the W array.

2.4.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/

subtracter with automatic sign extension logic. It can

select one of two accumulators (A or B) as its pre-

accumulation source and post-accumulation destina-

tion. For the ADD and LAC instructions, the data to be

accum ulated or l oaded ca n be optio nally sca led via th e

barrel shifter, prior to accumulation.

2.4.2.1 Adder/Subtracter, Overflow and

Saturation

The adder/subtracter is a 40-bit adder with an optional

zero input into one side and either true or complement

data into the other input. In the case of addition, the

carry/borrow input is active high and the other input is

true data (not complemented), whereas in the case of

subtrac tion, the carry/borrow input is active low and the

other input is complemented. The adder/subtracter

generates overflow Status bits SA/SB and OA/OB,

which are latched an d reflected in t he ST ATUS regi ster .

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is

destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overfl ow. This bit is set whenever all

the guard bits are not identical to each other.

The adder has an additional saturation block which

controls accumulator data saturation, if selected. It

uses the result of the adder, the overflow Status bits

described above, and the SATA/B (CORCON<7:6>)

and ACCSAT (CORCON<4>) mode control bits to

determine when and to what value to saturate.

Six STATUS register bits have been provided to

support saturation and overflow; they are:

1. OA:

ACCA overflowed into guard bits

2. OB:

ACCB overflowed into guard bits

3. SA:

ACCA saturated (bit 31 overflo w and saturatio n)

ACCA overflowed into guard bits and saturated

(bit 39 over flow and saturation)

4. SB:

ACCB saturated (bit 31 overflo w and saturatio n)

ACCB overflowed into guard bits and saturated

(bit 39 over flow and saturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data

passes through the adder/subtracter. When set, they

indicate that the most recent operation has overflowed

into the accumulator guard bits (bits 32 through 39).

The OA and OB bits can also optionally generate an

arithmetic warning trap when set and the correspond-

ing overflow trap flag enable bit (OVATE, OVBTE) in

the INTCON1 register (refer to Section 5.0 “Inter-

rupts”) is set. This allows the user to take immediate

action, for example, to correct system gain.

dsPIC30F1010/202X

The SA and SB bit s are modified each time da ta passes

through the adder/subtracter, but can only be cleared by

the user. When set, they indicate that the accumulator

has overflowed its maximum range (bit 31 for 32 -bit sat-

uration, or bit 39 for 40-bit saturation) and will be satu-

rated (if saturation is enabled). When saturation is not

enabled, SA and SB default to bit 39 overflow and thus

indicate that a cat astrophic overfl ow has occurred. If the

COVTE bit in the INTCON1 register is set, SA and SB

bits wil l generate an arithmetic w arning trap when

saturation is disabled .

The overflow and saturation Status bits can optionally

be viewed in the STATUS Register (SR) as the logical

OR of OA an d OB (in bit OAB) and the logical OR of SA

and SB (in bit SAB). Th is allows programm ers to check

one bit in the STATUS Register to determine if either

accumulator has overflowed, or one bit to determine if

either accumulator has saturated. This is useful for

complex number arithmetic, which typically uses both

the accumulators.

The device supports three Saturation and Overflow

modes.

1. Bit 39 Overflow and Saturation:

When bit 39 overflow and saturation occurs, the

saturation logic load s the maximally positive 9.31

(0x7FFFFFFFFF) or maximally negative 9.31

value (0x8000000000) into the target accumula-

tor. The SA or SB bit is set and remains set until

cleared by the user. This is referr ed to as ‘super

saturation’ and provides protection against erro-

neous data or unexpected algorithm problems

(e.g., gain calculations).

2. Bit 31 Overflow and Saturation:

When bit 31 overflow and saturation occurs, the

saturation logic then load s the maximally positive

1.31 value (0x007FFFFFFF) or maximally nega-

tive 1.31 value (0x0080000000) into the target

accumulator. The SA or SB bit is se t and remains

set until cleared by the user . When this Saturation

mode is in effect, the guard bits are not used (so

the OA, OB or OAB bits are never set).

3. Bit 39 Catastrophic Overflow

The bit 39 overflow Status bit from the adder is

used to set the SA or SB bit, which remain set

until cleared by the user. No saturation operation

is performed and the accumulator is allowed to

overflow (destroying it s sign). If the COVTE b it in

the INTCON1 register is set, a catastrophic

ove rflow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write Back’

The MAC class of instructions (with the exception of

MPY, MPY.N, ED and EDAC) can optionally write a

rounded version of the high word (bits 31 through 16)

of the acc umulator that is not targeted by the instruction

into dat a spac e memory. The write is perfo rmed ac ross

the X bus into combined X and Y addres s space. The

following addressing modes are supported:

1. W13, Registe r Dire ct:

The rounded contents of the non-target

accumulator are written into W13 as a 1.15

fraction.

2. [W13] + = 2, Register Indirect with Post-Incre-

ment: The rounded contents of the non-target

accum ulator are written into the addre ss pointed

to by W13 as a 1.15 fraction. W13 is then

incremented by 2 (fo r a wo rd wr ite).

2.4.2.3 Round Logic

The round logic is a combinational block, which per-

forms a conventional (biased) or convergent (unbiased)

round function during an accumulator write (store). The

Round mode is det ermined by the state of the RND bit

in the CORCON register. It generates a 16-bit, 1.15 data

value which is passed to the data space write saturation

logic. If rounding is not indicated by the instruction, a

truncated 1.15 data value is stored and the least

significant word (lsw) is simply discarded.

Conventional rounding takes bit 15 of the accumulator,

zero-extends it and adds it to the AC CxH w ord (bi t s 16

through 31 of the accumulator). If the ACCxL wo rd (bits

0 through 15 of the accumulator) is between 0x8000

and 0xFFFF (0x8000 included), ACCxH is incre-

mented. If ACCxL is between 0x0000 and 0x7FFF,

ACCxH is left unchanged. A consequence of this

algorith m is that over a su ccessio n of random roun ding

operations, the value will tend to be biased slightly

positive.

Convergent (or unbiased) rounding operates in the

same manner as conventional rounding, except when

ACCxL equals 0x8000. If this is the case, the LSb (bit

16 of the accumulator) of ACCxH is examined. If it is ‘1’,

ACCxH is inc remen ted. If it is ‘0’, ACCxH is not modi-

fied. Assuming that bit 16 is effectively random in

nature, th is s c hem e w i ll re mo ve any rou ndi ng b ias th at

may accumulate .

The SAC and SAC.R instructions store either a trun-

cated (SAC) or rounded (SAC.R) version of the cont ents

of the t arget accumul ator to data mem ory , via the X bu s

(subject to data saturation, see Section 2.4.2.4 “Data

Space Write Saturation”). Note tha t for th e MAC cl as s

of instructions, the accumulator write back operation

will fu nction in t he same ma nner , a ddressing combine d

MCU (X and Y) data space though the X bus. For this

class of instructions, the data is always subject to

rounding.

dsPIC30F1010/202X

2.4.2.4 Data Space Write Saturat ion

In addition to adder/sub tracter saturation, writes to data

space may also be saturated, but without affecting the

contents of the source accumulator. The data space

write saturation logic block accepts a 16-bit, 1.15 frac-

tional value from the round logic block as its input,

together with overflow status from the original source

(accumulator) and the 16-bit round adder. These are

combin ed and used t o sele ct the a ppropri ate 1.1 5 frac-

tional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data

(after roundi ng or trun ca tio n) is tes te d for ove rflo w and

adjusted accordingly. For input data greater than

0x007FF F, data writte n to memory i s forced to the max-

imum posit ive 1. 15 val ue, 0x7FFF. For i nput data le ss

than 0x FF8000, dat a wri tten to memo ry is f orced to the

maximum negative 1.15 value, 0x8000. The MSb of the

source (bit 39) is used to determine the sign of the

operand bei ng tes ted.

If the SATDW bit i n the CORCON register is not set , the

input data is always passed through unmodified under

all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 15-bit

arithmetic or logic right shifts, or up to 16-bit left shifts

in a single cycle. The source can be either of the two

DSP accumulators or the X bus (to support multi-bit

shifts of register or memory data).

The sh ifter requi res a s ign ed bi nary v al ue to de term in e

both the m agnitude (number of bits) and direction of the

shift operation. A positive value will shift the operand

right. A negative value will shift the operand left. A

value of ‘0’ will not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a

40-bit res ult for DSP shift ope rations an d a 16-bit resu lt

for MCU shift operations. Data from the X bus is pre-

sented to the barrel shifter between bit positions 16 to

31 for right sh ifts, and bit positio ns 0 to 15 for left sh ifts.

dsPIC30F1010/202X

NOTES:

dsPIC30F1010/202X

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

The program address space is 4M instruction words. It

is addressable by a 24-bit value from either the 23-bit

PC, table instruction Effective Address (EA), or data

space EA, when program space is mapped into data

space, as defined by Table 3-1. Note that the program

spa ce add ress i s increm ented b y tw o betwee n suc ces-

sive program words, in order to provide compatibility

with data space addressing.

User program space access is restricted to the lower

4M instruction word address range (0x000000 to

0x7FFFFE) , for all access es other than TBLRD/TBLWT,

which use TBLPAG<7> to determi ne user or conf igura-

tion space access. In Table 3-1, Read/Write instruc-

tions, b it 23 allows a ccess to the Devic e ID, the User ID

and the Configuration bits. Otherwise, bit 23 is always

clear.

FIGURE 3-1:

PROGRAM SPACE MEMORY

MAP F OR dsPIC 30F10 10/

202X

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

Note: The address map shown in Figure 3-1 is

conceptual, and the actual memory con-

figuration may vary across individual

devices depending on available memory.

Reset – Target Address

User Memory

Space

000000

7FFFFE

00007E

Ext. Osc. Fail Trap

000002

000080

User Flash

Progra m Mem ory

002000

001FFE

Address Erro r Trap

Stack Error Trap

Arithmetic Warn. Trap

Reserved

Vector 0

Vector 1

Vector 52

Vector 53

(4K instructions)

Reserved

(Read 0’s)

0000FE

000100

000014

Al ternate Vect or Table

Reset – GOTO Instruction

000004

Reserved

Device Configuration

Configuration Memory

Space

800000

F80000

Registers F8000E

F80010

DEVID (2) FEFFFE

FF0000

FFFFFE

Reserved F7FFFE

8005FE

800600

UNITID (32 instr.)

8005BE

8005C0

Reserved

Vector Tables

dsPIC30F1010/202X

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 3-2: DATA ACCESS FROM PROGR AM SPACE ADDRESS GENERATION

Access Type Access

Space Program Sp ac e Address

<23> <22:16> <15> <14:1> <0>

Instruction Access User 0 PC<22:1> 0

TBLRD/TBLWT User

(TBLPAG<7> = 0)TBLPAG<7:0> Data EA <15:0>

TBLRD/TBLWT Configuration

(TBLPAG<7> = 1)TBLPAG<7:0> Data EA <15:0>

Program Space Visibility User 0 PSVPAG<7:0> Data EA <14:0>

0Program Counter

23 bits

PSVPAG Reg

8 bits

15 bits

Program

Using

Select

TBLPAG Reg

8 bits

16 bits

Using

Byte

24-bit EA

1/0

Select

User/

Configuration

Table

Instruction

Program

Space

Counter

Using

Space

Select

Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.

Visibility

dsPIC30F1010/202X

3.1.1 DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

This arc hit ec ture f etc hes 24 -bi t w ide prog ram me mo ry.

Consequently, instructions are always aligned. How-

ever, as the architecture is modified Harvard, data can

also be present in prog ram space.

There are two methods by which program space can

be accessed; via special table instructions, or through

the rema ppi ng of a 16K word prog ram space page in to

the u pp e r half o f da ta space (s ee Section 3.1.2 “Data

Access from Program Memory Using Program

Space Visibility”). The TBLRDL and TBLWTL instruc-

tions of fer a direct method of readin g or writing the least

significant word (lsw) of any address within program

space, without going through data space. The TBLRDH

and TBLWTH instructions are the only method whereby

the upper 8 bits of a program space word can be

accessed as data.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit

word wide add res s s p ac es , res id ing sid e by si de, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the Least Significant

Data Word, and TBLRDH and TBLWTH access the

space which contains the Most Significant Data Byte.

Figure 3-2 shows h ow th e EA is cre ate d for ta ble op er-

ations and data space accesses (PSV = 1). Here,

P<23:0> refers to a program space word, whereas

D<15:0> refers to a data space word.

A set of Ta ble In str ucti ons is pro vid ed t o move byt e or

word sized data to and from program space.

1. TBLRDL: Table Read Low

Word: Read the lsw of the program address;

P<15:0> maps to D<15:0>.

Byte: Read one of the LSBs of the program

address;

P<7:0> maps to the destination byte when byte

select = 0;

P<15:8> m aps to the d estination byte when byte

select = 1.

2. TBLWTL: Table Write Lo w (re fer t o Section 7.0

“Flash Program Memory” for details on Flash

Programming).

3. TBLRDH: Table Read High

Word: Read the most significant word of the

program address;

P<23:16> maps to D<7:0>; D<15:8> always

be = 0.

Byte: Read one of the MSBs of the program

address;

P<23:16> maps to the destination byte when

byte select = 0;

The destination byte will always be = 0 when

byte select = 1.

4. TBLWTH: Table Wri te Hi gh (ref er to Section 7.0

“Flash Program Memory” for details on Flash

Programming).

FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFIC ANT W OR D)

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(Read as ‘0’).

TBLRDL.W

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

dsPIC30F1010/202X

FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE)

3.1.2 DATA ACCESS FROM PROGRAM

MEMORY USING PROGRAM

SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word program space page. This

provides transparent access of stored constant data

from X data space, without the need to use special

instructions (i.e., TBLRDL/H, TBLWTL/H instructions).

Program space access through the data space occurs

if the MSb of the data space EA is set and program

space visibility is enabled, by setting the PSV bit in the

Core Control register (CORCON). The functions of

CORCON are discussed in Section 2.4 “DSP

Engine”.

Data accesses to this area add an additional cycle to

the instruction being executed, since two program

memory fetch es are requ ire d.

Note that the upper half of addressable data space is

always part of the X data space. Therefore, when a

DSP ope ration uses p rogram sp ace mapp ing to acces s

this m em ory reg ion , Y d ata space should typic al ly co n-

tain state (variable) data for DSP operations, whereas

X data space should typically contain coefficient

(constant) da ta.

Although each dat a sp ace address, 0x8000 and higher ,

maps directly into a corresponding program memory

address (see Figure 3-5), only the lower 16-bits of the

24-bit program word are used to contain the data. The

upper 8 bits shoul d be progra mmed to forc e an illeg al

instruction to maintain machine robustness. Refer to

the “dsPIC30F/33F Programmer ’s Reference Manual”

(DS70157) for details on instruction encoding.

Note that by incrementing the PC by 2 for each pro-

gram memory word, the Least Significant 15 bits of

data space addresses directly map to the Least Signif-

icant 15 bits in the corresponding program space

address es. The remainin g bits are prov ided by the Pro-

gram Sp ace V is ibilit y Page regi ster, PSVPAG<7:0>, as

shown in Figure 3-5.

For instructions that use PSV which are executed

outside a REPEAT loop:

• The following instructions will require one instruc-

tion cycle in addition to the specified execution

time:

-MAC class of instructions with data operand

prefetch

-MOV instr ucti ons

-MOV.D instructions

• All other instructions will require two instruction

cycl es in addition to th e specified execution time

of the instruction.

For instructions that use PSV which are executed

inside a REPEAT loop:

• The follo wing inst ances will re quire two ins truction

cycl es in addition to th e specified execution time

of the instruction:

- Execution in the first iteration

- Execution in the last iteration

- Execution prior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interr upt is servi ced

• Any other iteration of the REPEAT loop will allow

the instruction, accessing data using PSV, to

execute in a single cycle.

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(Read as ‘0’)

TBLRDH.W

TBLRDH.B (Wn<0> = 1)

TBLRDH.B (Wn<0> = 0)

Note: PSV acc ess is tempo raril y disabl ed durin g

Table Reads/Writes.

dsPIC30F1010/202X

FIGU RE 3- 5 : DATA SPACE WI ND O W I NT O PROG R AM SPACE OP ER AT ION

3.2 Data Address Space

The core has two data spaces. The data spaces can be

considered either separate (for some DSP instruc-

tions), o r as o ne u nified lin ear a ddress ran ge (fo r MC U

instruc tions). The dat a spaces are accessed usi ng two

Address Generation Units (AGUs) and separate data

paths.

3.2.1 DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key element of th is ar chi tec tur e is th at

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent linear

addressing space, X and Y spaces have contiguous

addresses.

When executing any instruction other than one of the

MAC class of instructions, the X block consists of the

256 byte data address space (including all Y

addresses). When executing one of the MAC class of

instructions, the X block consists of the 256 bytes data

address space excluding the Y address block (for data

reads on ly). In other word s, all other i nstructions rega rd

the entire data memory as one composite address

space. The MAC class instructions extract the Y

address space from data space and address it using

EAs source d from W10 and W1 1. The remaining X data

space is addressed using W8 and W9. Both address

spaces are concurrently accessed only with the MAC

class instructions.

A data space memory map is shown in Figure 3-6.

23 15 0

PSVPAG(1)

EA<15> =

EA<15> = 1

Data

Space

Data Space Program Space

15 23

0x0000

0x8000

0xFFFF

0x00

0x100100

0x001FFE

Data Read

Upper half of Data

Space is mapped

into Program Space

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address

(i.e., it defines the page in program space to which the upper half of data space is being mapped).

0x001200

Address

Con cat enat i on

BSET CORCON,#2 ; PSV bit set

MOV #0x00, W0 ; Set PSVPAG register

MOV W0, PSVPAG

MOV 0x9200, W0 ; Access program memory location

; using a data space access

dsPIC30F1010/202X

FIGU RE 3-6 : DATA SPACE MEMO R Y MA P

0x0000

0x07FE

0x08FE

0xFFFE

LSB

Address

16 b i ts

LSBMSB

MSB

Address

0x0001

0x07FF

0x08FF

0xFFFF

0x8001 0x8000

Optionally

Mapped

into Program

Memory

0x09FF 0x09FE

0x0801 0x0800

0x0901 0x0900

Near

Data

SFR Space

512 bytes

SRAM Space

2560 bytes

Note: Unimplemented SFR or SRAM locations read as ‘0’.

Space

Unimplemented (X)

X Data

SFR Space

X Data RAM (X)

Y Data RAM (Y)

(Note)

256 bytes

(See Note)

0x0A00

dsPIC30F1010/202X

FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS

SFR SPACE

(Y SPACE)

X SPACE

SFR SPACE

UNUSED

X SPACE

Y SPACE

UNUSED

Non-MAC Class Ops (Read/Write) MAC Class Ops Read-Only

Indirect EA using any W Indirect EA using W10, W11

MAC Class Ops (W r i te)

Indirect EA using W8, W9

dsPIC30F1010/202X

3.2.2 DATA SPACES

The X data space is used by all instructions and sup-

ports all Addressing modes. There are separate read

and write data buses. The X read data bus is the return

data path for all instructions that view data space as

combined X and Y address space. It is also the X

address space data path for the dual operand read

instructions (MAC class). The X write data bus is the

only write path to data space for all instructions.

The X dat a sp ace als o suppo rts m odulo address ing for

all instructions, subject to Addressing mode restric-

tions. Bit-Reversed Addressing is only supported for

writes to X data space.

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,

EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to pro-

vide two concurrent data read paths. No writes occur

across the Y bus. This class of instructions dedicates

two W register pointers, W10 and W11, to always

address Y data space, independent of X data space,

whereas W8 and W9 always address X data space.

Note that during accumulator write back, the data

address space is considere d a c om bin ati on of X and Y

data spaces, so the write occurs across the X bus.

Consequently, the write can be to any address in the

entire data space.

The Y data space can only be used for the data

prefetch operation associated with the MAC class of

instructions. It also supports modulo addressing for

automat ed c irc ul ar bu f fe r s. Of c ours e, all othe r ins tru c-

tions ca n access the Y dat a address sp ace thro ugh the

X data path, as part of the composite linear space.

The boundary between the X and Y data spaces is

defined as shown in Figure 3-6 and is not user pro-

gramma ble. Shoul d an EA poin t to d ata out side it s own

assigned address space, or to a location outside phys-

ical mem ory, an all-zero word/byte wi ll be returne d. For

example, although Y address space is visible by all

non-MAC instructions using any Addressing mode, an

attempt by a MAC instruction to fetch data from that

space , using W 8 or W9 (X space p ointer s), wi ll ret urn

0x0000.

TABLE 3-2: EFFECT OF INVALID

MEMORY ACCESSES

All effective addresses are 16 bits wide and point to

bytes within the data space. Therefore, the data space

address range is 64 Kbytes or 32K words.

3.2.3 DATA SPACE WIDTH

The core data width is 16 bits. All internal registers are

organ ized as 16-bit wide words. Data space mem ory is

organized in byte addressable, 16-bit wide blocks.

3.2.4 DATA ALIGNMENT

To help maintain backward compatibility with PIC®

MCU devices and improve data space memory usage

efficiency, the dsPIC30F instruction set supports both

word and byte operation s. Data is al igned in dat a mem-

ory and registers as words, but all data space EAs

resolve to bytes. Data byte re ads will rea d the comp lete

word, whi ch contain s the byte, using the LSb of any EA

to determine which byte to select. The selected byte is

placed onto the LSB of the X data path (no byte

acces ses are possible fro m the Y data pa th as the MAC

class of instruction can only fetch words). That is, data

memory and registers are organized as two parallel

byte-wide entities with shared (word) address decode,

but separate write lines. Data byte writes only write to

the corresponding side of the array or register which

matches the byte address.

As a conse quence of this byte access ibility, all effec tive

address c alc ul atio ns (in cl udi ng tho se ge nera ted by th e

DSP operations, which are restricted to word sized

data) a re internally scale d to step through word-aligned

memory. For example, the core would recognize that

Post-Modified Register Indirect Addressing mode,

[Ws++], will result in a value of Ws + 1 for byte

operations and Ws + 2 for word operations.

All word accesses must be al igned to an even a ddress.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. Sh ould a mis-

aligned read or write be attempted, an address error

trap will be generated. If the error occurred on a read,

the instruction underway is completed, whereas if it

occurred on a write, th e instructi on will be execu ted but

the write will not occur. In either case, a trap will then

be exec uted, a llow ing the syste m and/ or user to exam-

ine the machine state prior to execution of the address

fault.

FIGURE 3-8: DATA ALIGNMENT

Attempted Operation Data Returned

EA = an unimplemented address 0x0000

W8 or W9 used to access Y data

spa ce in a MAC instru ction 0x0000

W10 or W11 used to access X

data space in a MAC instruction 0x0000

15 8 7 0

0001

0003

0005

0000

0002

0004

Byte 1 Byte 0

Byte 3 Byte 2

Byte 5 Byte 4

LSBMSB

dsPIC30F1010/202X

All byte loads into any W register are loaded into the

LSB. The MSB is not modified.

A Sign-Extend (SE) instruction is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

Zero-Extend (ZE) instruction on the appropriate

address.

Although m os t i ns truc tio ns are capab le of operating on

word or byte data sizes, it should be noted that some

instructions, including the DSP instructions, operate

only on words .

3.2.5 NEAR DATA SPACE

An 8 Kbyte ‘near ’ data space is reserved in X address

memory space between 0x0000 and 0x1FFF, which is

directly add res sab le via a 13-bit abso lute address fiel d

within all memory direct instructions. The remaining X

address space and all of the Y address space is

address able indirec tly. Addi tionally, the whole of X da ta

space is addressable using MOV instructions, which

support memory direct addressing with a 16-bit

address field.

3.2.6 SOFTWARE STACK

The dsPI C DSC de vice c ontain s a softwa re st ack. W15

is used as the Stack Pointer.

The Stack Pointer always points to the first available

free word and grows from lower addresses towards

higher ad dresses. It pre-dec rements for stack pops and

post-increments for stack pushes, as shown in

Figure 3-9. Note that for a PC push during any CALL

instruc tio n, the M SB o f t he PC i s ze ro-ex te nde d b efo re

the push, ensuring that the MSB is always clear.

Ther e is a Stack Pointer Limit register (S PLIM ) associ-

ated with the Stack Pointer. SPLIM is uninitialized at

Reset. As is the case for the Stack Pointer, SPLIM<0>

is forced to ‘0’, because all stack operations must be

word-aligned. Whenever an Effective Address (EA) is

generated using W15 as a source or destination

pointer, the address thus generated is compared with

the valu e i n SPL IM. If the c ont ents of the Stack Pointer

(W15) and the SPLIM register are equal and a push

operatio n is perform ed, a st ack error trap will no t occur.

The stack error trap will occur on a subsequent push

operation. Thus, for example, if it is desirable to cause

a stack error trap when the stack grows beyond

address 0x2000 in RAM, initialize the SPLIM with the

value, 0x1FFE.

Similarly, a S tack Pointer Underflow (st ack error) trap is

generated when the Stack Pointer address is found to

be less than 0x0800, thus preventing the stack from

interfering with the Special Function Register (SFR)

space.

A write to the SPLIM reg ister should not be immediately

follow ed by an ind irec t read ope rati on usi ng W15.

FIGURE 3-9: CALL ST ACK FRAME

3.2.7 DATA RAM PROTECTION

The dsPIC30F1010/202X devices support data RAM

protection features which enable segments of RAM to

be protec ted w hen us ed i n c onj unc ti on wi th Bo ot C od e

Segment Security. BSRAM (Secure RAM segment for

BS) is accessible only from the Boot Segment Flash

code when enabled. See Table 3-3 for the BSRAM

SFR.

Note: A PC push during exception processing

will concatenate the SRL register to the

MSB of the PC prior to the push.

PC<15:0>

000000000

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Toward s

Higher Addres s

PUSH: [W15++]

POP: [--W15]

0x0000

PC<22:16>

dsPIC30F1010/202X

TA BLE 3-3: CORE REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

W0 0000 W0/WREG 0000 0000 0000 0000

W1 0002 W1 0000 0000 0000 0000

W2 0004 W2 0000 0000 0000 0000

W3 0006 W3 0000 0000 0000 0000

W4 0008 W4 0000 0000 0000 0000

W5 000A W5 0000 0000 0000 0000

W6 000C W6 0000 0000 0000 0000

W7 000E W7 0000 0000 0000 0000

W8 0010 W8 0000 0000 0000 0000

W9 0012 W9 0000 0000 0000 0000

W10 0014 W10 0000 0000 0000 0000

W11 0016 W11 0000 0000 0000 0000

W12 0018 W12 0000 0000 0000 0000

W13 001A W13 0000 0000 0000 0000

W14 001C W14 0000 0000 0000 0000

W15 001E W15 0000 1000 0000 0000

SPLIM 0020 SPLIM 0000 0000 0000 0000

ACCAL 0022 ACCAL 0000 0000 0000 0000

ACCAH 0024 ACCAH 0000 0000 0000 0000

ACCAU 0026 Sign-Extension (ACCA<39>) ACCAU 0000 0000 0000 0000

ACCBL 0028 ACCBL 0000 0000 0000 0000

ACCBH 002A ACCBH 0000 0000 0000 0000

ACCBU 002C Sign-Extension (ACCB<39>) ACCBU 0000 0000 0000 0000

PCL 002E PCL 0000 0000 0000 0000

PCH 0030 — — — — — — — — —PCH0000 0000 0000 0000

TBLPAG 0032 — — — — — — — —TBLPAG0000 0000 0000 0000

PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000

RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu

DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu

DOSTARTL 003A DOSTARTL 0uuuu uuuu uuuu uuu0

DOSTARTH 003C — — — — — — — — —DOSTARTH0000 0000 0uuu uuuu

DOENDL 003E DOENDL 0uuuu uuuu uuuu uuu0

DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000

CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB

SATDW

ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000

Legend: u = uninitialized bit

dsPIC30F1010/202X

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

MODCON 0046 XMODEN YMODEN —— BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000

XMODSRT 0048 XS<15:1> 0uuuu uuuu uuuu uuu0

XMODEND 004A XE<15:1> 1uuuu uuuu uuuu uuu1

YMODSRT 004C YS<15:1> 0uuuu uuuu uuuu uuu0

YMODEND 004E YE<15:1> 1uuuu uuuu uuuu uuu1

XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu

DISICNT 0052 —— DISICNT<13:0> 0000 0000 0000 0000

BSRAM 0750 — — — — — — — — — — — — —

IW_BSR

IR_BSR

RL_BSR

0000 0000 0000 0000

TA BLE 3-3: CORE REGISTER MAP (CONTINUED)

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

Legend: u = uninitialized bit

dsPIC30F1010/202X

NOTES:

dsPIC30F1010/202X

4.0 ADDRESS GENERATOR UNITS

The dsPIC DSC core contains two independent

address generator un its: the X AGU and Y AGU. The Y

AGU supports word sized data reads for the DSP MAC

class of instructions only. The dsPIC DSC AGUs

support three types of data addressing:

• Linear Addressing

• Modulo (Circular) Addressing

• Bit-Revers ed Addre ss in g

Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-Reversed

Addressi ng is on ly appli cable to data s pace a ddresses .

4.1 Instruction Addressing Modes

The Addressing modes in Table 4-1 form the basis of

the Addressing modes o ptimized to support the specific

features of individual instructions. The Addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

4.1.1 FILE REGISTER INSTRUCTIONS

Most fil e re gis ter i ns truc tio ns use a 13-bi t ad dres s field

(f) to directly address data present in the first 8192

bytes of data memory (near data space). Most file

whic h is den oted as WREG in these i nstruc tions. The

destination is typically either the same file register, or

WREG (with the exception of the MUL instruction),

which w rites the re sult t o a re gister or regi ster p air. The

MOV instruction allows additional flexibility and can

access the entire data space.

TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.

decremented) by a constant value.

to form the EA.

dsPIC30F1010/202X

4.1.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Ope r and 1 is alwa ys a w orking regis ter (i. e., th e

Addressing mode can only be register direct), which is

referred to as Wb. Operand 2 can be a W register,

fetched from data memory, or a 5-bit literal. The result

location can be either a W register or an address

location. The following Addressing modes are

supported by MCU instructions:

• Register Direc t

• Register Indi rec t

• Register Indi rec t Post-mod ifi ed

• Register Indi rec t Pre- mo dif ied

• 5-bit or 10-bit Literal

4.1.3 MOVE AND ACCUMULATOR

INSTRUCTIONS

Move instructions and the DSP Accumulator class of

instructions provide a greater degree of addressing

flexibility than other instructions. In addition to the

Addressing modes supported by most MCU instruc-

tions, move and accumulator instructions also support

mode, also referred to as Register Indexed mode.

In summary, the following Addressing modes are

supported by move and accumulator instructions:

• Register Direc t

• Register Indi rec t

• Register Indi rec t Post-mod ifi ed

• Register Indi rec t Pre- mo dif ied

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Lite ral

• 16-bit Literal

4.1.4 MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also

referred to a s MAC instruction s, utilize a si mplified set of

Addressing modes to allow the user to effectively

manipulate the data pointers through register indirect

tables.

The two source operand prefetch registers must be a

member of the set {W8, W9, W10, W11}. For data

reads, W8 and W9 will always be directed to the X

RAGU and W10 and W11 will alway s be directed to th e

Y AGU. The effective addresses generat ed (before and

after modification) must, therefore, be valid addresses

within X data space for W8 and W9 and Y data space

for W10 and W11.

In summary, the following Addressing modes are

supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-modified by 2

• Register Indirect Post-modified by 4

• Register Indirect Post-modified by 6

• Register Indirect with Register Offset (Indexed)

4.1.5 OTHER INSTRUCTIONS

Besides the various Ad dressing mo des outlined above,

some i nstructio ns use li teral con sta nts of various sizes.

For example, BRA (branch) instructions use 16-bit

signed l iterals to spe cify the branch de stination dire ctly ,

whereas the DISI instruction uses a 14-bit unsigned

literal fiel d. In som e in stru cti ons , suc h as ADD Acc, the

source of an operand or result is implied by the opc ode

it self. Cert ain opera tions, such as NOP, do not have any

operands.

Note: Not all instructions support all the

Addressi ng modes given abo ve. Individual

instructions may support different subsets

of these Addressin g modes.

Note: For the MOV instructions, the Addressing

mode specified in the instruction can differ

for the source and destination EA. How-

ever, the 4-bit Wb (Registe r Offset) field is

shared between both source and

destination (but typically only used by

one).

Note: Not all instructions support all the

Addressi ng modes given abo ve. Individual

instructions may support different subsets

of these Addressin g modes.

Note: Register Indirect with Register Offset

Addressing is only available for W9 (in X

spac e) and W11 (in Y spac e).

dsPIC30F1010/202X

4.2 Modulo Addressing

Modulo addressing is a method of providing an auto-

mated means to support circular data buffers using

hardwa re. The ob jectiv e is to remo ve t he need for soft-

ware to perform data address boundary checks when

executing tightly looped code, as is typical in many

DSP algorithms.

Modulo addressing can operate in either data or pro-

gram space (since the data pointer mechanism is essen-

tially the same for both). One circular buffer can be

supported in each of the X (which also provides the

pointers into p rogram space) and Y d ata spaces. Modulo

addressing can operate on any W register poin ter. How-

ever, it is not advisable to use W14 or W15 for modulo

addressing, since these two registers are used as the

Stack Frame Pointer and Stack Pointer, respectiv ely.

In general, any particular circular buffer can only be

configu red to operate in one direct ion, as ther e are c er-

tain restrictions on the buffer start address (for incre-

menting buffers) or end address (for decrementing

buffers) based upon the dire ction of the buf fer.

The only exception to the usage restrictions is for buff-

ers which have a power-of-2 length. As these buffers

satisfy the start and end address criteria, they may

operate in a Bidirectional mode, (i.e., address bound-

ary checks will be performed on both the lower and

upper address boundaries).

4.2.1 START AND END ADDRESS

The modulo addressing scheme requires that a

starting and an end address be specified and loaded

into the 16-bit modulo buffer address registers:

XMODSRT, XMODEND, YMODSRT and YMODEND

(see Table 3-3).

The leng th of a ci rcular buf fer is not di rectly spec ified. It

is determined by the difference between the corre-

sponding start and end addresses. The maximum

possible length of the circular buffer is 32K words

(64 Kbytes).

4.2.2 W ADDRESS REGISTER

SELECTION

The Mod ulo an d Bi t-Rev ers ed Add ress in g Co ntro l re g-

ister M O DCON <1 5:0 > c on t ai ns enable fla gs as w ell a s

a W register field to specify the W address registers.

The XWM and YWM fields select which registers will

operate with mo dulo addressing. If XWM = 15, X RAGU

and X WAGU modulo addressing are disabled.

Similarly, if YWM = 15, Y AGU modulo addressing is

disabled.

The X Address Space Pointer W register (XWM) to

which modulo addressing is to be applied, is stored in

MODCON <3 :0> (s ee Table 3-3). Modulo ad dres si ng is

enabled for X data sp ace when XWM is set to any value

other than 15 and the XMODEN bit is set at

MODCON<15>.

The Y Address Space Pointer W register (YWM) to

which modulo addressing is to be applied, is stored in

MODCON<7:4>. Modulo addressing is enabled for Y

data space when YWM is set to any value other than 15

and the YMODEN bit is set at MODCON<14>.

Note: Y-space modulo addressing EA calcula-

tions assume word sized data (LSb of

every EA is always clear).

dsPIC30F1010/202X

FIGURE 4-1: MODULO ADDRESSI NG OPERATION EXAMPLE

0x1100

0x1163

Start Addr = 0x1100

End Addr = 0x1163

Length = 0x0032 words

Byte

Address MOV #0x1100,W0

MOV W0, XMODSRT ;set modulo start address

MOV #0x1163,W0

MOV W0,MODEND ;set modulo end address

MOV #0x8001,W0

MOV W0,MODCON ;enable W1, X AGU for modulo

MOV #0x0000,W0 ;W0 holds buffer fill value

MOV #0x1110,W1 ;point W1 to buffer

DO AGAIN,#0x31 ;fill the 50 buffer locations

MOV W0, [W1++] ;fill the next location

AGAIN: INC W0,W0 ;increment the fill value

dsPIC30F1010/202X

4.2.3 MODULO ADDRESSING

APPLICABILITY

Modulo addressing can be applied to the Effective

Address (EA) calculation associated with any W regis-

ter. It is important to realize that the address bound-

aries c he ck fo r ad dre sses le ss th an or greater tha n th e

upper (for incrementing buffers) and lower (for decre-

menting buffers) boundary addresses (not just equal

to). Address changes may, therefore, jump beyond

boundaries and still be adjusted correctly.

4.3 Bit-Reversed Addressing

Bit-Reversed Addressing is intended to simplify data

re-ordering for radix-2 FFT algorithms. It is supported

by t he X AGU for data writes only.

The modifier , which may be a constant value or register

contents, is regarded as having its bit order reversed.

The addres s sourc e and dest inat ion are ke pt in norma l

order. Thus, the only operand requiring reversal is the

modifier.

4.3.1 BIT-REVERSED ADDRESSING

IMPLEMENTATION

Bit-Reversed Addressing is enabled when:

1. BWM (W register selection) in the MODCON

not be accessed using Bit-Reversed

Addressing) and

2. the BREN bit is set in the XBREV register and

3. the Addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

If the length of a bit-reversed buffer is M = 2N bytes,

then the last ‘N’ bits of the data buffer start address

must be zero s.

XB<14:0> is th e b it-re vers ed ad dres s modifi er o r ‘p iv ot

point’ which is typically a constant. In the case of an

FFT computation, its value is equal to half of the FFT

dat a buffer size.

When enabled, Bit-Reversed Addressing will only be

executed for register indirect with pre-increment or

post-inc remen t addres sing an d word siz ed dat a wri tes.

It will no t functio n for any ot her Addres sing m ode or for

byte sized data, and normal addresses will be gener-

ated instea d. When Bit-R eversed Addr essin g is active,

the W Address Pointer will always be added to the

address modifier (XB) and the offset associated with

the register Indirect Addressing mode will be ignored.

In addition, as word sized data is a requirement, the

LSb of the EA is ignored (and always clear).

If Bit-Reversed Addressing has already been enabled

by setting the BREN (XBREV<15>) bit, then a write to

the XBREV register should not be immediately followed

by an indirect read operation using the W register that

has been designated as the bit-reversed pointer.

FIGURE 4-2: BIT-REVERSED ADDRES S EXAMPLE

Note: The m odu lo corr ected ef fective add res s i s

written back to the re giste r only when Pre-

Modify or Post-Modify Addressing mode is

used to compute the Effective Address.

When an address offset (e.g., [W7 + W2])

is used , m odu lo a dd res s c orrec ti on i s p er-

formed, but the contents of the register

remains unchanged.

Note: All Bit-Reversed EA calculations assume

word sized data (LSb of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

Note: Modulo addressing and Bit-Reversed

Addressing should not be enabled

together. In the event that the user

attempt s to do this , Bit-Reversed Addr ess-

ing wil l assume priori ty when activ e for the

X WAGU, and X WAGU modulo address-

ing will be disabled. However, modulo

addressing will continue to function in the

X RAGU.

b3 b2 b1 0

b2 b3 b4 0

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

Bit-Reversed Address

XB = 0x0008 for a 16 word Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4b11 b10 b9 b8

b11 b10 b9 b8

b15 b14 b13 b12

Sequenti al Addre ss

Pivot Point

dsPIC30F1010/202X

TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Normal

Address Bit-Reversed

Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0000 00000 0

0001 11000 8

0010 20100 4

0011 31100 12

0100 40010 2

0101 51010 10

0110 60110 6

0111 71110 14

1000 80001 1

1001 91001 9

1010 10 0101 5

1011 11 1101 13

1100 12 0011 3

1101 13 1011 11

1110 14 0111 7

1111 15 1111 15

Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value(1)

32768 0x4000

16384 0x2000

8192 0x1000

4096 0x0800

2048 0x0400

1024 0x0200

512 0x0100

256 0x0080

128 0x0040

64 0x0020

32 0x0010

16 0x0008

80x0004

40x0002

20x0001

Note 1: Modifier values greater than 256 words exceed the data memory available on the dsPIC30F1010/202X device

dsPIC30F1010/202X

5.0 INTERRUPTS

The dsPIC30 F1010/ 202X devic e has up to 35 in terrupt

sources and 4 processor exceptions (traps), which

must be arbitrated based on a priority scheme.

The CPU is responsible for reading the Interrupt Vec-

tor Table (IVT) and transferring the address contained

in the interrupt vector to the Program Counter (PC).

The interrupt vector is transferred from the program

data bus into the Program Counter, via a 24-bit wide

multiplexer on the input of the Program Counter.

The Interrupt Vector Table and Alternate Interrupt Vec-

tor Table (AIVT) are placed near the beginning of pro-

gram memory (0x000004). The IVT and AIVT are

shown in Figure 5-1.

The interrupt controller is responsible for pre-

processing the interrupts and processor exceptions,

prior to their being presented to the processor core.

The peripheral interrupts and traps are enabled, priori-

tized and controlled using centralized special function

registers:

• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>

All interrupt request flags are maintained in these

three registers. The flags are set by their respec-

tive peripherals or external signals, and they are

cleared via software.

• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>

All interrupt enable control bits are maintained in

these three registers. These control bits are used

to individually enable interrupts from the

peripherals or external signals.

• IPC0<15:0>... IPC11<7:0>

The user-as s ign abl e prio rity lev el assoc iate d with

eac h of these i nterrupts is held centrally in these

twelve registe rs.

• IPL<3:0> The current CPU priority level is explic-

itly stored in the IPL bits. IPL<3> is present in the

CORCON reg ister , whereas IPL<2:0 > are present

in the STATUS Register (SR) in the processor

core.

• INTCON1< 15: 0>, IN TCO N2<15:0>

Global interru pt co ntrol fu nctio ns are deriv ed from

these two registers. INTCON1 contains the con-

trol and status flags for the processor exceptions.

The INTCON2 r egister controls the external inter-

rupt request signal behavior and the use of the

alternate vector table.

• The INTTREG register contains the associated

interrupt vector number and the new CPU inter-

rupt priority level, which are latched into vector

number (VECNUM<6:0>) and Interrupt level

(ILR<3:0>) b it field s in the INTT REG regi ster. The

new interrupt priority level is the priority of the

pending interrupt.

All interrupt sources can be user assigned to one of 7

priority levels, 1 through 7, via the IPCx registers.

Each interrupt source is associated with an interrupt

vector, as shown in Figure 5-1. Levels 7 and 1 repre-

sent the highest and lowest maskable priorities,

respectively.

If the NSTDIS bit (INTCON1<15>) is set, nesting of

interrupts i s prev en ted . Th us , i f a n i nte rrupt is curre ntl y

being serviced, processing of a new interrupt is

preve nte d, e ven if th e ne w inte rrup t is of hi gher priorit y

than the one currently being serviced.

Certain interrupts have specialized control bits for

features like edge or level triggered interrupts, inter-

rupt-on-change, etc. Control of these features remains

within the peripheral module that generates the

interrupt.

The DISI instruction can be used to disable the

processing of interrupts of priorities 6 and lower for a

certain number of instructions, during which the DISI bit

(INTCON2<14>) remains set.

When an interrupt is serviced, the PC is loaded with the

address stor ed in the vecto r locati on in Program Mem-

ory that cor respond s to the interrupt. Ther e are 63 dif-

fer ent vect ors with in the I VT (ref er to Fig ure 5-1). T hese

vectors are contained in locations 0x000004 through

0x0000FE of program memory (refer to Figure 5-1).

These l ocations cont ain 24-bit addresses , and, in order

to preserve robustness, an address error trap will take

place should the PC attempt to fetch any of these

words during normal execution. This prevents execu-

tion of random data as a result of accidentally decre-

menting a PC into vector space, accidentally mapping

a data space address int o vector spac e, or the PC roll-

ing over to 0x000000 after reaching the end of imple-

mented program memory space. Execution of a GOTO

instruction to this vector space will also generate an

address error trap.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157). Note: Interrupt flag bits get set whe n an Interru pt

conditi on occ urs, regar dless o f the s tate of

its corresponding enable bit. User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

Note: Assigning a priority level of 0 to an inter-

rupt source is equivalent to disabling that

interrupt.

Note: The IPL bits become read-only whenever

the NSTDIS bit has been set to ‘1’.

dsPIC30F1010/202X

5.1 Interrupt Priority

The user-a ssig nable In terrupt Prio rity (IP<2:0>) b its for

each ind ividual interrupt source are located in the Least

Significant 3 bits of each nibble, within the IPCx

as a ‘0’. These bits define the priority level assigned to

a particular interrupt by the user.

Since more than one interrupt request source may be

assigned to a specific user specified priority level, a

means is provided to assign priority within a given level.

This method is called “Natural Order Priority” and is

final.

Natural order priority is dete rmined by the po sition of an

interrupt in the vector table, and only affects interrupt

operation when multiple interrupts with the same user-

assigned priority become pending at the same time.

Table 5-1 lists the interrupt numbers and interrupt

sources for the dsPIC DSC devices and their

associated vector numbers.

The ability for the user to assign every interrupt to one

of sev en priority l ev els i mp lie s that the u se r c an as sig n

a very high overall priority level to an interrupt with a

low natural order priority. The INT0 (external interrupt

0) may be assigned to priority level 1, thus giving it a

very low effective priority.

TABLE 5-1: dsPIC30F1010/202X

INTERRUPT VECTOR TABLE

Note: The user selectable priority levels start at

0, as the l owest priori ty, and le vel 7, as th e

highest priority.

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the

lowest priority.

2: The natural order priority number is the

same as the INT number.

INT

Number Vector

Number Interrupt Source

Highest Natural Order Priority

0 8 INT 0 – External Interrupt 0

1 9 IC1 – Input Ca pture 1

2 10 OC1 – Output Compare 1

3 11 T1 – Timer 1

4 12 Reserved

5 13 OC2 – Output Compare 2

6 14 T2 – Timer 2

7 15 T3 – Timer 3

8 16 SPI1

9 17 U 1RX – UART1 Recei ver

10 18 U1TX – UART1 Transmitt er

11 19 ADC – ADC Convert Done

12 20 NVM – NVM Write Complete

13 21 SI 2C – I2C™ Slav e Eve nt

14 22 MI2C – I2C M as te r Ev ent

15 23 Reserved

16 24 I N T1 – Extern al In te rrupt 1

17 25 I N T2 – Extern al In te rrupt 2

18 26 PW M Special Event Trigger

19 27 PWM Gen#1

20 28 PWM Gen#2

21 29 PWM Gen#3

22 30 PWM Gen#4

23 31 Reserved

24 32 Reserved

25 33 Reserved

26 34 Reserved

27 35 C N – I nput Chang e Not i fic at io n

28 36 Reserved

29 37 Analog Co m parator 1

30 38 Analog Co m parator 2

31 39 Analog Co m parator 3

32 40 Analog Co m parator 4

33 41 Reserved

34 42 Reserved

35 43 Reserved

36 44 Reserved

37 45 ADC Pair 0 Conversion Done

38 46 ADC Pair 1 Conversion Done

39 47 ADC Pair 2 Conversion Done

40 48 ADC Pair 3 Conversion Done

41 49 ADC Pair 4 Conversion Done

42 50 ADC Pair 5 Conversion Done

43 51 Reserved

44 52 Reserved

45-53 53-61 Reserved

Lowest Natural Order Priority

dsPIC30F1010/202X

5.2 Reset Sequence

A Reset is not a true exception, because the interrupt

controll er is not involv ed in the Reset proce ss. The pro-

cessor initializes its registers in response to a Reset,

which forces the PC to zero. The processor t hen begins

program execution at location 0x000000. A GOTO

instruction is stored in the first program memory loca-

tion, im media tel y follo wed by th e addres s t arget for th e

GOTO instruction. The processor executes the GOTO to

the speci f ie d add res s and then begi ns op erat ion at the

specified target (start) address.

5.2.1 RESET SOURCES

In addition to External Reset and Power-on Reset

(POR), there are 6 sources of error conditions which

‘trap’ to the Reset vector.

• Watchdog Time-out:

The watchdog has timed out, indicating that the

process or is no longer ex ecu tin g the corre ct flo w

of code.

• Uninitialized W Register Trap:

An attempt to use an uninitialized W register as

an Address Pointer will cause a Reset.

• Illegal Instruction Trap:

Attempted execution of any unused opcodes will

result in an illegal instruction trap. Note that a

fetch of an illegal instruction does not result in an

illegal instruction trap if that instruction is flushed

prior to execution due to a flow change.

• Trap Lockout:

Occurrence of multiple Trap conditions

simultaneously will cause a Reset.

5.3 Traps

Traps can be considered as non-maskable interrupts

indicating a software or hardware error, which adhere

to a predefined priority as shown in Figure 5-1. They

are intended to provide the user a means to correct

errone ous o pera tio n d urin g debug and w he n o pera ting

within the application.

Note that many of these trap conditions can only be

detected when th ey occur. Consequentl y, the ques tion-

able instruction is allowed to complete prior to trap

exception processing. If the user chooses to recover

from the error, the result of the erroneous action that

caused the trap may have to be corrected.

There are 8 fixed priority levels for traps: Level 8

through Le ve l 15, whic h impl ies tha t the IPL3 i s alw ays

set during processing of a trap.

If the us er is n ot cur rentl y execu ting a trap, a nd he s et s

the IP L<3:0> bit s to a value of ‘0111’ (Level 7), t hen al l

interr upts are disabled, b ut traps c an still b e processed.

5.3.1 TRAP SOURCES

The following traps are provided with increasing prior-

ity. However, since all traps can be nested, priority has

little effect.

Math Error Trap:

The Math Error trap executes under the following four

circumstances:

1. Should an attempt be made to divide by zero,

the divide operation will be aborted on a cycle

boundary and the trap taken.

2. If enabled, a Math Error trap will be taken when

an arithmetic operation on either accumulator A

or B causes an overflow from bit 31 and the

accumulator guard bits are not utilized.

3. If enabled, a Math Error trap will be taken when

an arithmetic operation on either accumulator A

or B causes a catastrophic overflow from bit 39

and all saturation is disabled.

4. If the shift amount specified in a shift instruction

is greater than the maximum allowed shift

amount, a trap will occur.

Note: If the user does not intend to take correc-

tive acti on in the event of a T rap Error co n-

dition, these vectors must be loaded with

the address of a default handler that sim-

ply contains the RESET instruction. If, on

the ot her hand, one of the vector s cont ain-

ing an invalid address is called, an

address error trap is generated.

dsPIC30F1010/202X

Address Error Trap:

This trap is initiated when any of the following

circumstances occurs:

1. A misaligned data word access is attempted.

2. A data fetch from our unimplemented data

memory location is attempted.

3. A data access of an unimplemented program

memory location is attempted.

4. An instruction fetch from vector space is

attempted.

5. Execution of a “BRA #literal” instruction or a

“GOTO #literal” ins truc ti on, w he re literal

is an u nimplem ented pr ogram me mory addr ess.

6. Executing instructions after modifying the PC to

point to unimplemented program memory

addresses. The PC may be modified by loading

a value into the stack and executing a RETURN

instruction.

Stack Error Trap:

This trap is initiated under the following conditions:

1. The Stack Pointer is loaded with a value which

is greater than the (user-programmable) limit

value written into the SPLIM register (stack

overflow).

2. The Stack Pointer is loaded with a value which

is less than 0x0800 (simple stack underflow).

Oscillato r Fail Trap:

This trap is initiated if the external oscillator fails and

operation becomes reliant on an internal RC backup.

5.3.2 HARD AND SOFT TRAPS

It is possible that multiple traps can become active

within the same cycle (e.g., a misaligned word stack

write to an overflowed address). In such a case, the

fixed priority shown in Figure 5-1 is implemented,

whic h may requir e the user t o check if oth er traps are

pending, in order to completely correct the fault.

‘Soft’ traps incl ude exceptions of priority lev el 8 through

level 11, inclusive. The arithmetic error trap (level 11)

falls into this category of traps.

‘Hard’ traps include exceptions of priority level 12

through level 15, inclusive. The address error (level

12), stack error (level 13) and oscillator error (level 14)

traps fall into this category.

Each hard trap that occurs must be acknowledged

before code execution of any type may continue. If a

lower priority hard trap occurs while a higher priority

trap is pending, acknowledged, or is being processed,

a hard trap conflict will occur.

The devic e is automatic ally Reset in a hard trap conflict

condition. The TRAPR Status bit (RCON<15>) is set

when the Reset occurs, so that the condition may be

detected in software.

FIGURE 5-1: TRAP VECTORS

Note: In the MAC class of instructions, wherein

the data space is split into X and Y data

space, unimplemented X space includes

all of Y space, and unimplemented Y

space includes all of X space.

Address Error Trap Vector

Oscillator Fail Trap Vector

Stack Error Trap Vector

Reser ved Vector

Math E rror Trap Vector

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Reser ved Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

Math E rror Trap Vector

Decreasing

Priority

0x000000

0x000014

Reserved

Stack Error Trap Vector

Reser ved Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

IVT

AIVT

0x000080

0x00007E

0x0000FE

Reserved

0x000094

Reset - GOTO Instruction

Reset - GOTO Addr ess 0x000002

Reserved 0x000082

0x000084

0x000004

Reser ved Vector

dsPIC30F1010/202X

5.4 Interrupt Sequence

All inte rrupt event flags are sampled in the be ginning of

each instruction cycle by the IFSx registers. A pending

interr upt reque st (IRQ) i s indic ated by the flag bit being

equal t o a ‘1’ in an IFSx register . The IRQ will cause an

interrupt to occur if the corresponding bit in the interrupt

enable (IECx) register is set. For the remainder of the

instruction cycle, the priorities of all pending interrupt

requests are evaluated.

If there is a pending IRQ with a priority level greater

than the current processor priority level in the IPL bits,

the processor will be interrupted.

The processor then stacks the current Program

Counter and the low byte of the processor STATUS

of the STATUS register contains the processor priority

level at the time, prior to the beginning of the interrupt

cycle. The processor then loads the priority level for

this interrupt into the STATUS register. This action will

disab le al l lower prior ity i nterr upts un til th e comp letion

of the Interrupt Service Routine (ISR).

FIGURE 5-2: INTERRUPT STACK

FRAME

The RETFIE (Return from Interrupt) instruction will

unstack the Program Counter and status registers to

return the processor to its state prior to the interrupt

sequence.

5.5 Alternate Vector Table

In Program Me mory , the IVT is followe d by the AIVT, as

shown in Figure 5-1. Access to the Alternate Vector

Table is provided by the ALTIVT bit in the INTCON2

tion processes will use the alternate vectors instead of

the defa ult vectors. The alternate vectors are organized

in the same manner as the default vectors. The AIVT

supports emulation and debugging efforts by providing

a means to switch between an application and a sup-

port environment, without requiring the interrupt vec-

tors to be reprogrammed. This feature also enables

switching between applications for evaluation of

diffe rent software algorithms at run time.

If the AIVT is not required, the program memory allo-

cated to the AIVT may be used for other purposes.

AIVT is not a protected section and may be freely

programmed by the user.

5.6 Fast Context Saving

A context saving option is available using shadow reg-

isters. Shadow registers are provided for the DC, N,

OV, Z and C bits i n SR, and th e registe rs W0 throu gh

W3. The shadows are only one level deep. The shadow

registers are accessible using the PUSH.S and POP.S

inst ruc tion s onl y.

When the processor vectors to an interrupt, the

PUSH.S instruction can be used to store the current

value of the aforementioned registers into their

respective shadow registers.

If an ISR of a certain priority uses the PUSH.S and

POP.S instructions for fast context saving, then a

higher priority IS R shou ld no t inc lude the s ame ins truc-

tions. Users must save the key registers in software

during a lower priorit y interrupt, if t he higher prio rity ISR

uses fast context saving.

5.7 External Interrupt Requests

The interrupt controller supports three external inter-

rupt request signals, INT0-INT2. These inputs are edge

sensitive; they require a low-to-high or a high-to-low

transition to generate an interrupt request. The

INTCON2 re gister has thre e bits, INT0EP-INT2EP, that

select the polarity of the edge detection circuitry.

5.8 Wake-up from Sleep and Idle

The interrupt controller may be used to wake-up the

processor from either Sleep or Idle modes, if Sleep or

Idle mode is active when the interrupt is generated.

If an enabled interrupt request of sufficient priority is

received by the interrupt controller, then the standard

interrupt request is presented to the processor. At the

same time, the processor will wake-up from Sleep or

Idle and begin execution of the Interrupt Service

Routine needed to process the interrupt request.

Note 1: The user can always lower the priority

level by writing a new value into SR. The

Interrupt Service Routine must clear the

interrupt flag bits in the IFSx register

before lowering the processor interrupt

priority, in order to avoid recursive

interrupts.

2: The IPL3 bit (CORCON<3>) is always

clear when interrupts are being pro-

cessed. It is set only during execution of

traps.

015

W15 (befor e CALL

)

W15 (after CALL)

Stack Grows Towards

Higher Address

PUSH : [W15++]

POP : [--W15]

0x0000

PC<15:0>

SRL IPL3 PC<22:16>

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE

bit 15 bit 8

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled

0 = Interrupt nesting is enabled

bit 14 OVAERR: Accumulator A Overflow Trap Flag bit

1 = Trap was caused by overfl ow of Accumulator A

0 = Trap was not caused by overflow of Accumulator A

bit 13 OVBERR: Accumulator B Overflow Trap Flag bit

1 = Trap was caused by overfl ow of Accumulator B

0 = Trap was not caused by overflow of Accumulator B

bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit

1 = Trap was caused by catastrophic overflow of Accumulator A

0 = Trap was not caused by catastrophic overflow of Accumulator A

bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit

1 = Trap was caused by catastrophic overflow of Accumulator B

0 = Trap was not caused by catastrophic overflow of Accumulator B

bit 10 OVATE: Accumulator A Overflow Trap Enable bit

1 = Trap overflow of Accumulator A

0 = Trap disabled

bit 9 OVBTE: Accumul ator B Overflow Trap Enable bit

1 = Trap overflow of Accumulator B

0 = Trap disabled

bit 8 COVTE: Catastrophic Overflow Trap Enable bit

1 = Trap on catastrophic overflow of Accumulator A or B enabled

0 = Trap disabled

bit 7 SFTACERR: Shift Accumulator Error Status bit

1 = Math error trap was caused by an invalid accumulator shift

0 = Math error trap was not caused by an invalid accumulator shift

bit 6 DIV0ERR: Arithmetic Error Status bit

1 = Math error trap was caused by a divided by zero

0 = Math error trap was not caused by an invalid accumulator shift

bit 5 Unimplemented: Read as ‘0’

bit 4 MATHERR: Arithmetic Error Status bit

1 = Overflow trap has occurred

0 = Overflow trap has not occurred

bit 3 ADDRERR: Address Error Trap Status bit

1 = Address error trap has occurred

0 = Address error trap has not occurred

dsPIC30F1010/202X

bit 2 STKERR: Stack Error Trap Status bit

1 = Stack error trap has occurred

0 = Stack error trap has not occurred

bit 1 OSCFAIL: Oscillator Failure Trap Status bit

1 = Oscillator failure trap has occurred

0 = Oscillator failure trap has not occurred

bit 0 Unimplemented: Read as ‘0’

dsPIC30F1010/202X

R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

ALTIVT DISI — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — INT2EP INT1EP INT0EP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit

1 = Use alternate vector table

0 = Use standard (default) vector table

bit 14 DISI: DISI Instruction Status bit

1 = DISI instruction is active

0 = DISI instruction is not active

bit 13-3 Unimplemented: Read as ‘0’

bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

dsPIC30F1010/202X

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T3IF T2IF OC2IF — T1IF OC1IF IC1IF INT0IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14 MI2CIF: I2C Master Events Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 13 SI2CIF: I2C Slav e Even t s Interrup t Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12 NVMIF: Nonvolatile Memory Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 11 ADIF: ADC Conversion Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 10 U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 9 U1RXIF: UART1 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 8 SPI1IF: SPI1 Eve nt Interru pt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 7 T3IF: Timer3 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 T2IF: Timer2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 Unimplemented: Read as ‘0’

bit 3 T1IF: Timer1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

dsPIC30F1010/202X

bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 INT0IF: External Interrupt 0 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0

AC3IF AC2IF AC1IF — CNIF — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— PWM4IF PWM3IF PWM2IF PWM1IF PSEMIF INT2IF INT1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 AC3IF: Analog Comparator #3 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 14 AC2IF: Analog Comparator #2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 13 AC1IF: Analog Comparator #1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12 Unimplemented: Read as ‘0’

bit 11 CNIF: Input Change Notif ica tio n Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 10-7 Unimplemented: Read as ‘0’

bit 6 PWM4IF: Pulse Width Modulation Generator #4 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 PWM3IF: Pulse Width Modulation Generator #3 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 PWM2IF: Pulse Width Modulation Generator #2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 3 PWM1IF: Pulse Width Modulation Generator #1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 2 PSEMIF: PWM Special Event Match Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 INT2IF: External Interrupt 2 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 INT1IF: External Interrupt 1 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

dsPIC30F1010/202X

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-00 R/W-0

— — — — — ADCP5IF ADCP4IF ADCP3IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0

ADCP2IF ADCP1IF ADCP0IF — — — —AC4IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10 ADCP5IF: ADC Pair 5 Conversion Done Interrupt Flag Status b it

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 9 ADCP4IF: ADC Pair 4 Conversion Done Interr upt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 8 ADCP3IF: ADC Pair 3 Conversion Done Interr upt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 7 ADCP2IF: ADC Pair 2 Conversion Done Interr upt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 ADCP1IF: ADC Pair 1 Conversion Done Interr upt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 ADCP0IF: ADC Pair 0 Conversion Done Interr upt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4-1 Unimplemented: Read as ‘0’

bit 0 AC4IF: Analog Comparator #4 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

dsPIC30F1010/202X

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T3IE T2IE OC2IE — T1IE OC1IE IC1IE INT0IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14 MI2CIE: I2C Master Events Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 13 SI2CIE: I2C Slave Events Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 12 NVMIE: Nonvolatile Memory Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 11 ADIE: ADC Conversion Complete Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 10 U1TXIE: UART1 Transmitter Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 9 U1RXIE: UART1 Receiver Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 8 SPI1IE: SPI1 Event Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 7 T3IE: Timer3 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 6 T2IE: Timer2 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 5 OC2IE: Output Compare Channel 2 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 4 Unimplemented: Read as ‘0’

bit 3 T1IE: Timer1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

dsPIC30F1010/202X

bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 0 INT0IE: External Interrupt 0 Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0

AC3IE AC2IE AC1IE — CNIE — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— PWM4IE PWM3IE PWM2IE PWM1IE PSEMIE INT2IE INT1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 AC3IE: Analog Comparator #3 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 14 AC2IE: Analog Comparator #2 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 13 AC1IE: Analog Comparator #1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 12 Unimplemented: Read as ‘0’

bit 11 CNIE: Input Change Notification Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 10-7 Unimplemented: Read as ‘0’

bit 6 PWM4IE: Pulse Width Modulation Generator #4 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 5 PWM3IE: Pulse Width Modulation Generator #3 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 4 PWM2IE: Pulse Width Modulation Generator #2 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 3 PWM1IE: Pulse Width Modulation Generator #1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 2 PSEMIE: PWM Special Event Match Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 1 INT2IE: External Interrupt 2 Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 0 INT1IE: External Interrupt 1 Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

dsPIC30F1010/202X

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — ADCP5IE ADCP4IE ADCP3IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0

ADCP2IE ADCP1IE ADCP0IE — — — —AC4IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10 ADCP5IE: ADC Pair 5 Conversion done Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 9 ADCP4IE: ADC Pair 4 Conversion done Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 8 ADCP3IE: ADC Pair 3 Conversion done Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 7 ADCP2IE: ADC Pair 2 Conversion done Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 6 ADCP1IE: ADC Pair 1 Conversion done Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 5 ADCP0IE: ADC Pair 0 Conversion done Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 4-1 Unimplemented: Read as ‘0’

bit 0 AC4IE: Analog Comparator #4 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

dsPIC30F1010/202X

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T1IP<2:0> — OC1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC1IP<2:0> — INT0IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Prior ity bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

dsPIC30F1010/202X

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T3IP<2:0> — T2IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—OC2IP<2:0>— — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T3IP<2:0>: Timer3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 T2IP<2:0>: Timer2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

dsPIC30F1010/202X

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— ADIP<2:0> — U1TXIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U1RXIP<2:0> — SPI1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 ADIP<2:0>: ADC Conversion Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SPI1IP<2:0>: SPI1 Event Interrupt Priori ty bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

dsPIC30F1010/202X

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — —MI2CIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

—SI2CIP<2:0>— NVMIP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 MI2CIP<2:0>: I2C Master Events Interrupt Priori ty bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SI2CIP<2:0>: I2C Slave Even ts Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 NVMIP<2:0>: Nonvol ati le Me mo ry Interru pt Priori ty bit s

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

dsPIC30F1010/202X

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— PWM1IP<2:0> — PSEMIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— INT2IP<2:0> — INT1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 PWM1IP<2:0>: PWM Generator #1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 PSEMIP<2:0>: PWM Special Event Match Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

dsPIC30F1010/202X

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — PWM4IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— PWM3IP<2:0> — PWM2IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 PWM4IP<2:0>: PWM Generator #4 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 PWM3IP<2:0>: PWM Generator #3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 PWM2IP<2:0>: PWM Generator #2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

dsPIC30F1010/202X

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—CNIP<2:0>— — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11-0 Unimplemented: Read as ‘0’

dsPIC30F1010/202X

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— AC3IP<2:0> — AC2IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— AC1IP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 AC3IP<2:0>: Analog Comparator 3 Inte rrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 AC1IP<2:0>: Analog Comparator 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

dsPIC30F1010/202X

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — AC4IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 AC4IP<2:0>: Analog Comparator 4 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

dsPIC30F1010/202X

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— ADCP2IP<2:0> — ADCP1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— ADCP0IP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 ADCP1IP<2:0>: ADC Pair 1 Conversion Done Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 ADCP0IP<2:0>: ADC Pair 0 Conversion Done Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

dsPIC30F1010/202X

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — ADCP5IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— ADCP4IP<2:0> — ADCP3IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Re ad as ‘0’

bit 10 - 8 ADCP5IP<2:0>: ADC Pair 5 Conversion Done Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 ADCP4IP<2:0>: ADC Pair 4 Conversion Done Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

dsPIC30F1010/202X

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — —ILR<3:0>

bit 15 bit 8

U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

— VECNUM<6:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-8 ILR: New CPU Interrupt Priority Level bits

1111 = CPU Interrupt Priority Level is 15

•

0001 = CPU Interrupt Priority Level is 1

0000 = CPU Interrupt Priority Level is 0

bit 7 Unimplemented: Read as ‘0’

bit 6-0 VECNUM: Vector Number o f Pending Interrupt bits

0111111 = Interrupt Ve ctor pending is number 135

•

0000001 = Interrupt Ve ctor pending is number 9

0000000 = Interrupt Ve ctor pending is number 8

dsPIC30F1010/202X

TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP

SFR

Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

INTCON1

0080

NSTDIS

OVAERR OVBERR COVAERR

COVBERR

OVATE OVBTE COVTE

SFTACERR

DIV0ERR —

MATHERR

ADDRERR

STKERR OSCFAIL —

0000 0000 0000 0000

INTCON2

0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP

INT0EP

0000 0000 0000 0000

IFS0 0084 — MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF — T1IF OC1IF IC1IF INT0IF

0000 0000 0000 0000

IFS1 0086 AC3IF AC2IF AC1IF —CNIF— — — — PWM4IF PWM3IF PWM2IF PWM1IF PSEMIF INT2IF INT1IF

0000 0000 0000 0000

IFS2 0088 — — — — — ADCP5IF ADCP4IF ADCP3IF ADCP2IF ADCP1IF ADCP0IF — — — —AC4IF

0000 0000 0000 0000

IEC0 0094 — MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE — T1IE OC1IE IC1IE INT0IE

0000 0000 0000 0000

IEC1 0096 AC3IE AC2IE AC1IE — CNIE — — — — PWM4IE PWM3IE PWM2IE PWM1IE PSEMIE INT2IE INT1IE

0000 0000 0000 0000

IEC2 0098 — — — — — ADCP5IE ADCP4IE ADCP3IE ADCP2IE ADCP1IE ADCP0IE — — — —AC4IE

0000 0000 0000 0000

IPC0 00A4 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0>

0100 0100 0100 0100

IPC1 00A6 — T31P<2:0> — T2IP<2:0> —OC2IP<2:0>— — — —

0100 0100 0100 0000

IPC2 00A8 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0>

0100 0100 0100 0100

IPC3 00AA — — — — —MI2CIP<2:0> —SI2CIP<2:0>— NVMIP<2:0>

0000 0100 0100 0100

IPC4 00AC — PWM1IP<2:0> — PSEMIP<2:0> — INT2IP<2:0> — INT1IP<2:0>

0100 0100 0100 0100

IPC5 00AE — — — — — PWM4IP<2:0> — PWM3IP<2:0> — PWM2IP<2:0>

0000 0100 0100 0100

IPC6 00B0 — CNIP<2:0> — — — — — — — — — — — —

0100 0000 0000 0000

IPC7 00B2 — AC3IP<2:0> —AC2IP<2:0> —AC1IP<2:0>— — — —

0100 0100 0100 0000

IPC8 00B4 — — — — — — — — — — — — — AC4IP<2:0>

0000 0000 0000 0100

IPC9 00B6 — ADCP2IP<2:0> — ADCP1IP<2:0> — ADCP0IP<2:0> — — — —

0100 0100 0100 0000

IPC10 00B8 — — — — — ADCP5IP<2:0> — ADCP4IP<2:0> — ADCP3IP<2:0>

0000 0100 0100 0100

INTTREG

00E0 — — — —ILR<3:0>— VECNUM<6:0>

0000 0000 0000 0000

Note: Refer to the “dsPIC30F/33F Family Reference Manual” (DS70157) for descriptions of register bit fields.

dsPIC30F1010/202X

NOTES:

dsPIC30F1010/202X

6.0 I/O PORTS

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared between the peripherals and

the parallel I/O ports.

All I/O input ports feature Schmitt Trigger inputs for

improved noise immunity.

6.1 Parallel I/O (P I O ) P o rts

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

may be read, but the output driver for the parallel port

bit will be disabled. If a peripheral is enabled, but the

peripheral is not actively driving a pin, that pin may be

driven by a port.

All port pins have three registers directly associated

with the operation of the port pin. The data direction

or an output. If the data direction bit is a ‘1’, t hen the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Writes to the latch, write the latch (LATx). Reads from

the port (PORTx), read the port pins, and writes to the

port pins, write the latch (LATx).

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LATx and

TRISx registers and the port pin will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs.

A Parallel I/O (PIO) port that shares a pin with a periph-

eral is, in general, subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has own ership of the outp ut dat a and co ntrol si gnals of

the I/O pad cell. Figure 6-1 shows how ports are shared

with o ther periphe rals, and th e associa ted I/O cell (pad)

to which they are connected. Table 6-1 and Table 6-2

show the register formats for the shared ports, PORTA

through PORTF, for the dsPIC30F1010/2020 and

PORTA through POR TG for the ds PIC30F2023 devic e,

respectively.

FIGURE 6-1: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

WR LAT +

TRIS Latch

I/O P a d

WR Port

Data Bus

Data Latch

Read LAT

Read Po rt

Read TRIS

W R TRIS

Peripheral Ou tput Data Output Enable

Peripheral In put D ata

I/O Cell

Peripheral Module

Peripheral Ou tput Enable

PIO Module

Output Multiplexers

Output Data

Inp u t Data

Peripheral Module Enable

dsPIC30F1010/202X

6.2 Configuring Analog Port Pins

The use of the ADPC FG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) will be

converted.

When read ing the POR T register, all pins confi gured as

analog in put channel w ill read as cleare d (a low lev el).

Pins configured as digit al inputs will not convert an ana-

log input. Analog levels on any pin that is defined as a

digital input (including the ANx pins), may cause the

input buffer to consume current that exceeds the

device specifications.

6.2.1 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be a NOP.

EXAMPLE 6-1: PORT WR ITE/READ

EXAMPLE

6.3 Input Change Notification

The input change notification function of the I/O ports

allows the dsPIC30F1010/202X devices to generate

interrupt requests to the processor in response to a

change-of-state on selected input pins. This feature is

capable of detecting input change-of-states even in

Sleep mode, when the clocks are disabled. There are

8 external signals (CN0 through CN7) that can be

selected (enabled) for generating an interrupt request

on a c hange-o f-state.

There are two control registers associated with the CN

module. The CNEN1 register contain the CN interrupt

enable (CNxIE) control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

Each CN pin also has a weak pull-up connected to it.

The pull-ups act as a current source that is connected

to the pin and eliminate the need for external resistors

when push button or keypad devices are connected.

The pull-ups are enabled separately using the CNPU1

PUE) bits for each of the CN pins. Setting any of the

control bits enables the weak pull-ups for the

corresp onding pi ns.

MOV 0xFF00, W0; Configure PORTB<15:8>

; as inputs

MOV W0, TRISBB; and PORTB<7:0> as outputs

NOP ; Delay 1 cycle

BTSS PORTB, #13; Next Instruction

Note: Pull-ups on change notification pins should

always be disabled whenever the port pin is

configured as a digital output.

dsPIC30F1010/202X

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

TABLE 6-1: dsPIC30F1010/2020 PORT REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit

12 Bit

11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TRISA 02C0 — — — — — —TRISA9 — — — — — — — — — 0000 0010 0000 0000

PORTA 02C2 — — — — — —RA9 — — — — — — — — — 0000 0000 0000 0000

LATA 02C4 — — — — — —LAT9 — — — — — — — — — 0000 0000 0000 0000

TRISB 02C6 — — — — — — — — TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0000 0000 0011 1111

PORTB 02C8 — — — — — — — — RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000

LATB 02CA — — — — — — — — LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000

TRISD 02D2 — — — — — — — — — — — — — — —TRISD00000 0000 0000 0001

PORTD 02D4 — — — — — — — — — — — — — — — RD0 0000 0000 0000 0000

LATD 02D6 — — — — — — — — — — — — — — —LATD00000 0000 0000 0000

TRISE 02D8 — — — — — — — — TRSE7 TRSE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 0000 0000 1111 1111

PORTE 02DA — — — — — — — — RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000

LATE 02DC — — — — — — — — LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 0000 0000 0000 0000

TRISF 02DE — — — — — — — TRISF8 TRISF7 TRISF6 — — — — — — 0000 0001 1100 0000

PORTF 02E0 — — — — — — — RF8 RF7 RF6 — — — — — — 0000 0000 0000 0000

LATF 02E2 — — — — — — — LATF8 LATF7 LATF6 — — — — — — 0000 0000 0000 0000

dsPIC30F1010/202X

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

TABLE 6-2: dsPIC30F2023 PORT REGISTER MAP

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit

12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TRISA 02C0 —— — —

TRISA11 TRISA10

TRIS9 TRISA8 — — — — — — — — 0000 1111 0000 0000

PORTA 02C2 — — — — RA11 RA10 RA9 RA8 — — — — — — — — 0000 0000 0000 0000

LATA 02C4 — — — — LATA11 LATA10 LATA9 LATA8 — — — — — — — — 0000 0000 0000 0000

TRISB 02C6 — — — —

TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRIS6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

0000 1111 1111 1111

PORTB 02C8 — — — — RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000

LATB 02CA — — — — LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000

TRISD 02D2 — — — — — — — — — — — — — — TRISD1 TRISD0 0000 0000 0000 0011

PORTD 02D4 — — — — — — — — — — — — — — RD1 RD0 0000 0000 0000 0000

LATD 02D6 — — — — — — — — — — — — — — LATD1 LATD0 0000 0000 0000 0000

TRISE 02D8 — — — — — — — —

TRSE7 TRSE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0

0000 0000 1111 1111

PORTE 02DA — — — — — — — —RE7RE6

RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000

LATE 02DC — — — — — — — —LATE7LATE6

LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 0000 0000 0000 0000

TRISF 02DE TRISF15 TRISF14 — — — — —TRISF8

TRISF7 TRISF6

— —

TRISF3

TRISF2 — — 1100 0001 1100 1100

PORTF 02E0 RF15 RF14 — — — — — RF8 RF7 RF6 — — RF3 RF2 — — 0000 0000 0000 0000

LATF 02E2 LATF15 LATF14 — — — — — LATF8 LATF7 LATF6 — — LATF3 LATF2 — — 0000 0000 0000 0000

TRISG 02E4 — — — — — — — — — — — —

TRISG3

TRISG2 — — 0000 0000 0000 1100

PORTG 02E6 — — — — — — — — — — — — RG3 RG2 — — 0000 0000 0000 0000

LATG 02E8 — — — — — — — — — — — — LATG3 LATG2 — — 0000 0000 0000 0000

TABLE 6-3: dsPIC30F1010/202X INPUT CHANGE NOTIFICATION REGISTER MAP

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit

12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

CNEN1 0060 —— — — — — — —

CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE

0000 0000 0000 0000

CNPU1 0064 — — — — — — — —

CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

0000 0000 0000 0000

dsPIC30F1010/202X

7.0 FLASH PR OGRAM MEMORY

The dsPIC30F family of devices contains internal

program Flash memory for executing user code. There

are two methods by which the user can program this

memory:

1. In-Circuit Serial Programming™ (ICSP™)

programming capability

2. Run-Time Self-Programming (RTSP)

7.1 In-Circui t Serial Programming

(ICSP)

dsPIC30F devices can be serially programmed while i n

the end ap plica tion ci rcuit. Th is is s imply do ne wit h two

lines for Programming Clock and Programming Data

(which are named PGC and PGD respectively), and

three other lines for Power (VDD), Ground (VSS) and

Master Cl ear (MCLR ). This allows customers to manu-

facture boards with unprogrammed devices, and then

program the microcontroller just before shipping the

product. This also allows the most recent firmware or a

custom firmware to be programmed.

7.2 Run-Time Self-Programming

(RTSP)

RTSP is accomplished using TBLRD (table read) and

TBLWT (table wr ite) ins tru cti ons .

With RTSP, the user may erase program memory 32

instruc tions (96 by tes ) at a tim e an d c an wr it e pro gram

memory data 32 instructions (96 bytes) at a time.

7.3 Table Instruction Operation Summary

The TBLRDL and the TBLWTL instructions are used to

read or write to bits <15:0> of program memory.

TBLRDL and TBLWTL can access program memory in

Word or Byte mode.

The TBLRDH and TBLWTH instruc tions are us ed to read

or write to bits <23:16> of program memory. TBLRDH

and TBLWTH can access program memory in Word or

Byte mode.

A 24-bit program memory address i s formed usin g bit s

<7:0> of the TBLPAG register and the Effective

Address (EA) from a W register specified in the table

instruction, as shown in Figure 7-1.

FIGURE 7-1: ADDRESSING FOR TABLE AND NVM REGISTERS

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

0Program Counter

24 bi ts

NVMADRU Reg

8 bit s 16 bit s

Program

Using

TBLPAG Reg

8 bits

Wor k i ng Re g EA

16 bits

Using

Byte

24-bit EA

1/0

Select

Table

Instruction

NVMADR

Addressing

Counter

Using

NVMADR Reg EA

User/Configuration

Space Select

dsPIC30F1010/202X

7.4 RTSP Operation

The dsPIC30F Flash program memory is organized

into rows and panels. Each row consists of 32 instruc-

tions, or 96 bytes. Each panel consists of 128 rows, or

4K x 24 instru ctions. RTSP allows the user to erase one

row (32 instructions) at a time and to program 32

instructions at one time. RTSP may be used to program

multiple program memory panels, but the table pointer

must be changed at each panel boundary.

Each panel of program memory contains write latches

that hold 32 instructions of programming data. Prior to

the actual programming operation, the write data must

be loaded into the panel write latches. The data to be

programmed into the panel is loaded in sequential

order into the write latches; instruction ‘0’, instruction

‘1’, etc. The instruction words loaded must always be

from a group of 32 boundary.

The basi c sequence for R TSP programming is to set up

a table point er, then do a se ries o f TBLWT instructions

to load th e wri te latc hes. Program ming is perfo rmed by

setting the special bits in the NVMCON register. 32

TBLWTL and four TBLWTH instructions are required to

load the 32 instructions. If multiple panel programming

is required, the table pointer needs to be changed and

the next set of multiple write latches written.

All of the table write operations are single-word writes

(2 instruction cycles), because only the table latches

are written. A programming cycle is required for

programming each row.

The Flash Program Memory is readable, writable and

erasable during normal operation over the entire VDD

range.

7.5 Control Registers

The four SFRs used to read and write the program

Flash memory are:

•NVMCON

• NVMADR

• NVMADRU

• NVMKEY

7.5.1 NVMCON REGISTER

The NVMCON register controls which blocks are to be

erased, which memory type is to be programmed and

the start of the programming cycle.

7.5.2 NVMADR REGISTER

The NVMADR register is used to hold the lower two

bytes of the effective address. The NVMADR register

captures the EA<15 :0> of the last table instru ct ion that

has been executed and selects the row to write.

7.5.3 NVMADRU REGISTER

The NVMADRU register is used to hold the upper byte

of the effective address. The NVMADRU register cap-

tures the EA<23:16> of the last table instruction that

has been exec uted.

7.5. 4 NVMKEY REGISTER

NVMKEY is a write-only register that is used for write

protection. To start a programming or an erase

sequence, the user must consecutively write 0x55 and

0xAA to the NVMKEY register. Refer to Section 7.6

“Programming Operations” for further details.

Note: The user can also directly write to the

NVMADR and NVMADRU registers to

specify a program memory address for

erasing or programming.

dsPIC30F1010/202X

7.6 Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. A progra mming operati on is nominally 2 ms ec in

duration and the processor stalls (waits) until the oper-

ation is finished. Setting the WR bit (NVMCON<15>)

starts the operation, and the WR bit is automatically

cleared when the operation is finished.

7.6.1 PROGRAMMING ALGORITHM FOR

PROGRAM FLASH

The user can erase and program one row of program

Flash memory at a time. The general process is:

1. Read one row of program Flash (32 instruction

words) and store into data RAM as a data

“image”.

2. Update the data image with the desired new

data.

3. Erase pr ogram Flash row.

a) Setup NVMCON register for multi-word,

program Flash, erase and set WREN bit.

b) Write address of row to be erased into

NVMADRU/NVMDR.

c) Write ‘55’ to NVMKEY.

d) Writ e ‘AA’ to NVMKEY.

e) Set the WR bit. This will begin erase cycle.

f) CPU will stall for the duration of the erase

cycle.

g) The WR bit is cleared when erase cycle

ends.

4. Write 32 instruction words of data from data

RAM “image” into the program Flash write

latches.

5. Program 32 instruction words into program

Flash.

a) Setup NVMCON register for multi-word,

progra m Flash, program and set WREN bit.

b) Write ‘55’ to NVMKEY.

c) Write ‘AA’ to NVMKEY.

d) Set the WR bit. This will begin program

cycle.

e) CPU will stall for duration of the program

cycle.

f) The WR bit is cleared by the hardware

when program cycle ends.

6. Repeat step s 1 through 5 as needed to program

desired amount of program Flash memory.

7.6.2 ERASING A ROW OF PROGRAM

MEMORY

Example 7-1 show s a code seque nce that can be used

to erase a row (32 instructions) of program memory.

EXAMPL E 7-1: ER ASIN G A ROW OF PROGRAM MEMO RY

; Setup NVMCON for erase operation, multi word write

; program memory selected, and writes enabled

MOV #0x4041,W0 ;

MOV W0,NVMCON ; Init NVMCON SFR

; Init pointer to row to be ERASED

MOV #tblpage(PROG_ADDR),W0 ;

MOV W0,NVMADRU ; Initialize PM Page Boundary SFR

MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA<15:0> pointer

MOV W0, NVMADR ; Intialize NVMADR SFR

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

dsPIC30F1010/202X

7.6.3 LOADING WRITE LATCHES

Example 7-2 shows a sequence of instructions that

can be used to load the 96 bytes of write latches. 32

TBLWTL and 32 TBLWTH instructions are needed to

load the writ e latches selected by the table pointer.

EXAMPLE 7-2: LOADING WRITE LATCHES

7.6.4 INITIATING THE PROGRAMMING

SEQUENCE

For protec tion, the w rite i nitiate sequenc e for N VMKEY

must be used to allow any erase or program operation

to procee d. After the prog ramming comm and has bee n

executed, the user must wait for the programming time

until programming is complete. The two instructions

following the start of the programming sequence

should be NOPs.

EXAMPLE 7-3: INITIATING A PROGRAMMIN G SEQUENCE

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV #0x0000,W0 ;

MOV W0,TBLPAG ; Initialize PM Page Boundary SFR

MOV #0x6000,W0 ; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV #LOW_WORD_0,W2 ;

MOV #HIGH_BYTE_0,W3 ;

TBLWTL W2,[W0] ; Write PM low word into program latch

TBLWTH W3,[W0++] ; Write PM high byte into program latch

; 1st_program_word

MOV #LOW_WORD_1,W2 ;

MOV #HIGH_BYTE_1,W3 ;

TBLWTL W2,[W0] ; Write PM low word into program latch

TBLWTH W3,[W0++] ; Write PM high byte into program latch

; 2nd_program_word

MOV #LOW_WORD_2,W2 ;

MOV #HIGH_BYTE_2,W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

•

; 31st_program_word

MOV #LOW_WORD_31,W2 ;

MOV #HIGH_BYTE_31,W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

Note: In Example 7-2, the contents of the upper byte of W3 have no effect.

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

dsPIC30F1010/202X

TABLE 7-1: NVM REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit

11 Bit

10 Bit 9 Bit 8 Bit 7 Bit 6 Bi t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS

NVMCON 0760 WR WREN WRERR — — — —TWRI — PROGOP<6:0> 0000 0000 0000 0000

NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu

NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu

NVMKEY 0766 — — — — — — — — KEY<7:0> 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F1010/202X

NOTES:

dsPIC30F1010/202X

8.0 TIMER1 MODULE

This section describes the 16-bit General Purpose

Timer1 module and associated operational modes.

Figure 8-1 depicts the simplified block diagram of the

16-bit Timer1 Module.

The f ollowin g sec tions provid e a det ail ed descripti on of

the operational modes of the timers, including setup

and control registers along with associated block

diagrams.

The T imer1 mo dule is a 16-bit timer which can serv e as

the time count er for the rea l-time clo ck, o r operate as a

free runnin g interva l timer/c ounter . The 16-bit tim er has

the following modes:

• 16-bit Timer

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter

Further, the following operational characteristics are

supported:

• Timer gate operation

• Selectable prescaler set tings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit period register match or falling

edge of external gate signal

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit SFR, T1CON. Figure 8-1

presents a block diagram of the 16-bit timer module.

16-bit T imer Mode: In t he 16-bi t T imer m ode, the timer

increments on every instruction cycle up to a match

value, preloaded into the period register PR1, then

resets to 0 and continues to count.

When the CPU goes into the Idle mode, the timer will

stop incrementing, unless the TSIDL (T1CON<13>)

bit = 0. If TSIDL = 1, t he timer module log ic will resum e

the incrementing sequence upon termination of the

CPU Idle mode.

16-bit Synchronous Counter Mode: In the 16-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal,

which is synchronized with the internal phase clocks.

The timer counts up to a match v alue preloaded in PR1,

then resets to 0 and continues.

When the CPU goes into the Idle mode, the timer will

stop incrementing, unless the respective TSIDL bit = 0.

If TSIDL = 1, the timer module logic will resume the

incrementing sequence upon termination of the CPU

Idle mode.

16-bit Asynchronous Counter Mode: In the 16-bit

Asynchronous Counter mode, the timer increments on

every rising edge of the applied external clock signal.

The timer counts up to a match v alue preloaded in PR1,

then reset s to ‘0’ and continues.

When the timer is configured fo r the Asynchronous mode

of operation and the CPU goes into the Idle mode, the

timer w ill s to p incremen ti ng if TSIDL = 1.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note: Timer1 is a ‘Ty pe A’ timer. Please refer to

the specifications for a Type A timer in

Section 21.0 “Electrical Characteris-

tics” of this document.

dsPIC30F1010/202X

FIGURE 8-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)

8.1 Timer Gate Operation

The 16-bi t timer can be pl aced in the Ga ted Ti me Accu-

mulation mode. This mode allows the internal TCY to

increm ent the respec tive timer when the gate input si g-

nal (T1CK pin) is asserted high. Control bit TGATE

(T1CON<6>) must be set to enable this mode. The

timer must be enabled (TON = 1) and the timer clock

source se t to interna l (TCS = 0).

When the CPU goes into the Idle mode, the timer will

stop incrementing, unless TSIDL = 0. If TSIDL = 1, the

timer will resume the incrementing sequence upon

termination of the CPU Idle mode.

8.2 Timer Prescaler

The input clock (FOSC/2 or external clock) to the 16-bit

Timer, has a prescale option of 1:1, 1:8, 1:64, and

1:256 selected by control bits TCKPS<1:0>

(T1CON< 5:4 >). T he pres ca le r counter i s c le are d whe n

any of the following occurs:

• a write to the TMR1 register

• cl earing of the TON bit (T1C ON<1 5>)

• device Re set su ch as POR

However, if the timer is disabled (TON = 0), then the

timer prescaler cannot be reset since the prescaler

clock is halted.

TMR1 is not cleared when T1CON is written. It is

cleared by writin g to the TMR1 register.

8.3 T imer Operation During Sleep

Mode

During CPU Sleep mode, the timer will operate if:

• The timer module is enabled (TON = 1) and

• The timer clock s ource is selected as extern al

(TCS = 1) and

• The TSYNC bit (T1CON<2>) is asser ted to a logic

‘0’, which defines the external clock source as

asynchronous

When all three conditions are true, the timer will

continu e to co unt up to th e perio d regist er and be res et

to 0x0000.

When a ma tch betwe en the ti me r and the period regis -

ter occurs, an interrupt can be generated, if the

respective timer interrupt enable bit is asserted.

TON

Sync

PR1

T1IF

Equal Comparator x 16

TMR1

Reset

Event Flag

TSYNC

TGATE

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

T1CK

TCS

1 X

0 1

TGATE

0 0

Gate

Sync

dsPIC30F1010/202X

8.4 Timer Interrupt

The 16-bit tim er ha s the ab ili ty to ge nerate an interru pt

on period match. When the timer count matches the

period reg ister , th e T1IF bit is asserted and an interrupt

will be generated, if enabled. The T1IF bit must be

cleared in software. The timer interrupt flag T1IF is

located in the IFS0 control register in the Interrupt

Controller.

When the Gated Time Accumulation mode is enabled,

an interr upt will al so be generat ed on the f alling edge of

the gate signal (at the end of the accumulation cycle).

Enabling an interrupt is accomplished via the respec-

tive timer interrupt enable bit, T1IE. The timer interrupt

enable bit is located in the IEC0 control register in the

Interrupt Controller.

dsPIC30F1010/202X

TABLE 8-1: TIMER1 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR1 0100 Timer 1 Registe r uuuu uuuu uuuu uuuu

PR1 0102 Period Register 1 1111 1111 1111 1111

T1CON 0104 TON —TSIDL— — — — — — TGATE TCKPS<1:0> —TSYNCTCS —0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) f or descriptions of register bit fields.

dsPIC30F1010/202X

9.0 TIMER2/3 MODULE

This section describes the 32-bit General Purpose

Timer module (Timer2/3) and associated operational

modes. Figure 9-1 depic ts the simpli fie d block dia gram

of the 32-bi t Ti mer2/3 module. Fig ure 9-2 and Figure 9-

3 show Timer2/3 configured as two independent 16-bit

timers: Timer2 and Timer3, respectively.

The Timer2/3 module is a 32-bit timer, which can be

configu red as two 16-bit timers , with sele ct able oper at-

ing modes. These timers are utilized by other

peripheral modules such as:

• Input Capture

• Output Compare/Simple PWM

The following sections provide a detailed description,

including setup and control registers, along with asso-

ciated bl oc k dia gram s for the ope rati ona l mod es of the

timers.

The 32-bit timer has the following modes:

• Two independent 16-bit timers (Timer2 and

Timer3) wit h all 16-bit op erat ing modes (except

Asynchronous Counter mode)

• Single 32-bit Timer operation

• Single 32-bit Synchronous Counter

Further, the following operational characteristics are

supported:

• ADC Event Trigger

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation during Idle and Sleep modes

• Interrupt on a 32-bit Period Register Match

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit T2CON and T3CON

SFRs.

For 32-bit timer/counter operation, Timer2 is the least

signifi cant word and Tim er3 is the mos t significant wo rd

of the 32-bit timer.

16-bit Mode: In the 16-bit mode, Timer2 and Timer3

can be configured as two independent 16-bit timers.

Each time r can be set up in either 16-b it T imer mod e or

16-bit Synchronous Counter mode. See Section 8.0

“Timer1 Module” for details on these two operating

modes.

The only functional difference between Timer2 and

Timer3 is that Timer2 provides synchronization of the

clock prescaler output. This is useful for high-freque ncy

external clock inputs.

32-bit T imer Mode: In t he 32-bi t T imer m ode, the timer

increments on every instruction cycle up to a match

value, pre loade d into the combi ned 32-bi t period regis-

ter PR3/PR2, th en rese ts to ‘ 0’ and conti nues to c ount.

For synchronous 32-bit reads of the Timer2/Timer3

pair, reading the least significant word (TMR2 register)

will cause the most significant word to be read and

latched into a 16-bit holding register, termed

TMR3HLD.

For synchronous 32-bit writes, the holding register

(TMR3HLD) must first be written to. When followed by

a write to the TMR2 re gister, the c ontents of TMR3H LD

will be transferred and latched into the MSB of the

32-bit timer (TMR3).

32-bit Synchronous Counter Mode: In the 32-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal,

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in the

combi ne d 32 -bi t per i od re gi st er, PR3/PR 2 , th en re se ts

to ‘0’ and continues.

When the timer is configured for the Synchronous

Counter mode of operation and the CPU goes into the

Idle mode, the timer will stop incrementing, unless the

TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer

module logic will resume the incrementing sequence

upon termination of the CPU Idle mode.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note: The dsPIC30F1010 device does not fea-

ture T ime r3. T imer2 is a ‘Type B’ ti mer and

Timer3 is a ‘Type C’ timer. Please refer to

the appro pri ate tim er typ e i n Section 21.0

“Electri cal Characteristics” of this

document.

Note: For 32-bit timer operation, T3CON control

bits are ignored. Only T2CON control bits

are used for setup and control. Timer 2

clock and gate inputs are utilized for the

32-bit timer module, but an interrupt is

generated with the Timer3 interrupt flag

(T3IF) and th e interrupt is en abled with the

Timer3 interrupt enable bit (T3IE).

dsPIC30F1010/202X

FIGU RE 9-1: 32-BI T T IM E R2 /3 B LOC K DI AG R AM

TMR3 TMR2

T3IF

Equal Comparator x 32

PR3 PR2

Reset

LSB

MSB

Event Flag

Note: Timer Configuration bit T32, (T2CON<3>) must be s et to ‘1’ fo r a 32-bit timer /coun ter operation. All control

bits are respective to the T2CON register.

Data Bus<15:0>

TMR3HLD

Read TMR2

Write TMR2 16

TGATE(T2CON<6>)

(T2CON<6>)

TGATE

TON TCKPS<1:0>

Prescaler

1, 8, 64, 256

TCY

TCS

1 X

0 1

TGATE

0 0

Gate

T2CK

Sync

ADC Event Trigger

Sync

dsPIC30F1010/202X

FIGURE 9-2: 16-BIT TIMER2 BLOCK DIAGRAM

FIGURE 9-3: 16-BIT TIMER3 BLOCK DIAGRAM

TON

Sync

PR2

T2IF

Equal Comparator x 16

TMR2

Reset

Event Flag

TGATE

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

TCS

1 X

0 1

TGATE

0 0

Gate

T2CK

Sync

TON

PR3

T3IF

Equal Comparator x 16

TMR3

Reset

Event Flag

TGATE

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

TCS(1)

1 X

0 1

TGATE(2)

0 0

ADC Event Trigger

Sync

Note: The dsPIC30F202X does not have an external pin input to TIMER3. The following modes should not be used:

1. TCS = 1

2. TCS = 0 and TGATE = 1 (gated time accumulation)

dsPIC30F1010/202X

9.1 Timer Gate Operation

The 32-bi t timer can be pl aced in the Ga ted Ti me Accu-

mulation mode. This mode allows the internal TCY to

increm ent the respec tive timer when the gate input si g-

nal (T2CK pin) is asserted high. Control bit TGATE

(T2CO N<6>) mus t be set to en able this mode . When in

this mode, Timer2 is the originating clock source. The

TGATE setting is ign ored for T imer3. The tim er must be

enabled (TON = 1) and the timer clock source set to

internal (TCS = 0).

The falling edge of the external signal terminates the

count ope rati on, bu t does not res et the time r. The user

must reset the timer in order to start counting from zero.

9.2 ADC Event Trigger

When a matc h occurs betwe en the 32-bit timer (TM R3/

TMR2) and the 32-bit combined period register (PR3/

PR2), a special ADC trigger event signal is generated

by Timer3.

9.3 Timer Prescaler

The in put cloc k (FOSC/2 or external clock) to the timer

has a prescale option of 1:1, 1:8, 1:64, and 1:256

selected by control bits TCKPS<1:0> (T2CON<5:4>

and T3CON<5:4>). For the 32-bit timer operation, the

origina ting clock so urce is Timer2. The prescaler oper-

ation for Timer3 is not applicable in this mode. The

prescaler counter is cleared when any of the following

occurs:

• a write to the TMR2/TMR3 register

• clearing either of the TON (T2CON<15> or

T3CON<15>) bits to ‘0’

• device Re set su ch as POR

However, if the timer is disabled (TON = 0), then the

Timer 2 prescaler cannot be reset, since the prescaler

clock is halted.

TMR2/TMR3 is not cleared when T2CON/T3CON is

written.

9.4 T imer Operation During Sleep

Mode

During CPU Sleep mode, the timer will not operate,

because the internal clocks are disabled.

9.5 T imer Interrupt

The 32-bit timer module can generate an interrupt on

period ma tch, or on the fa lling edge of the externa l gate

signal. When the 32-bit timer count matches the

respective 32-bit period register, or the falling edge of

the external “gate” signal is detected, the T3IF bit

(IFS0<7>) is asserted and an interrupt will be gener-

ated if enabled. In this mode, the T3IF interrupt flag is

used as the source of the interrupt. The T3IF bit must

be cleared in sof tw are.

Enabling an interrupt is accomplished via the

respective timer interrupt enable bit, T3IE (IEC0<7>).

dsPIC30F1010/202X

TABLE 9-1: TIMER2/3 REGISTER MAP

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit

10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR2 0106 Timer2 Register uuuu uuuu uuuu uuuu

TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) uuuu uuuu uuuu uuuu

TMR3 010A Timer3 Regist er uuuu uuuu uuuu uuuu

PR2 010C Period Register 2 1111 1111 1111 1111

PR3 010E Period Register 3 1111 1111 1111 1111

T2CON 0110 TON —TSIDL— — — — — — TGATE TCKPS<1:0> T32 —TCS —0000 0000 0000 0000

T3CON 0112 TON —TSIDL— — — — — — TGATE TCKPS<1:0> ——TCS —0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F1010/202X

NOTES:

dsPIC30F1010/202X

10.0 INPUT CAPTURE MODULE

This section describes the Input Capture module and

associated operational modes. The features provided

by this module are useful in applications requiring Fre-

quency (Period) and Pulse measurement. Figure 10-1

depicts a block diagram of the Input Capture module.

Input capture is useful for such modes as:

• Frequency/Period/Pulse Measurements

• Additional source s of External Interrupts

The key operational features of the Input Capture

module are:

• Simple Capture Event mode

• Timer2 and Timer3 mode selection

• Interrupt on input capture event

These operating modes are determined by setting the

appropriate bits in the ICxCON register (where x =

1,2,...,N). The dsPIC DSC devices contain up to 8

capture channels, (i.e., the maximum value of N is 8).

FIGURE 10-1: INPUT CAPTURE MODE BLOCK DIAGRAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note: The dsPIC30F1010 devices does not fea-

ture a Input Capture module. The

dsPIC30F202X devices have one capture

input – IC1. The naming of this capture

channel is intentional and preserves soft-

ware compatibility with other dsPIC DSC

devices.

ICxBUF

Prescaler

ICx

ICM<2:0>

Mode Select

Note: Where ‘ x’ i s sh ow n, re fere nce is m ade to t he regis ters o r bits as soc ia ted to t he respe cti ve i npu t

capture ch annels 1 through N.

Set Flag

ICxIF

ICTMR

T2_CNT T3_CNT

Edge

Detection

Logic

Clock

Synchronizer

1, 4, 16

From General Purpose Timer Module

16 16

FIFO

R/W

Logic

ICI<1:0>

ICBNE, ICOV

ICxCON Interrupt

Logic

Set Flag

ICxIF

Data Bus

dsPIC30F1010/202X

10.1 Simple Capture Event Mode

The simple capture events in the dsPIC30F product

family are:

• Capture every falling edge

• Capture every rising edge

• Capture every 4th rising edge

• Capture every 16th rising edge

• Capture every rising and falling edge

These simple Input Capture modes are configured by

setting the appropriate bits ICM<2:0> (ICxCON<2:0>).

10.1.1 CAPTURE PRESCALER

There are four input capture prescaler settings, speci-

fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the

capture c hanne l is turn ed of f, the pr escal er coun ter will

be cleared. In addition, any Reset will clear the

prescaler counter.

10.1.2 CAPTURE BUFFER OPERATION

Each capture channel has an associated FIFO buffer,

which is four 16-bit words deep. There are two status

flags, which provide status on the FIFO buffer:

• ICBFNE – Input Capture Buffer Not Empty

• IC OV – Input Capture Ov erfl ow

The ICBFNE will be set on the fir st input ca ptu r e event

and remain set until all capture events have been read

from the FIF O. As each word is read fro m the FIFO, th e

remaining words are advanced by one position within

the buffer.

In the event that the FIFO is full with four capture

events and a fifth capture event occurs prior to a read

of the FIFO, an Overflow condition will occur and the

ICOV bit will be s et to a logic ‘1’. The fifth capture event

is lost and is not stored in the FIFO. No additional

events will be captured until all four events have been

read from the buffer.

If a FIFO read is performed after the last read and no

new capture event has been received, the read will

yield indeterminate results.

10.1.3 TIMER2 AND TIMER3 SELECTION

MODE

The inp ut capture modu le c onsist s of up to 8 input cap-

ture chann els. Each channel can select between on e of

two timers for the time base, Timer2 or Timer3.

Selection of the timer resource is accomplished

through SFR bit ICTMR (ICxCON<7>). Timer3 is the

default timer resource available for the input capture

module.

10.1.4 HALL SENSOR MODE

When the input capture module is set for capture on

every ed ge, risi ng and fal ling, ICM <2:0> = 001, the fol-

lowing operations are performed by the input capture

logic:

• The input capture interrupt flag is set on every

edge, rising and falling.

• The Interrupt on Capture mode setting bits,

ICI<1:0>, are ignored, since every capture

generates an interrupt.

• A Captur e Overflow condition is not generated in

this mode.

dsPIC30F1010/202X

10.2 Input Capture Operation During

Sleep and Idle Modes

An input capture event will generate a device wake-up

or interrupt, if enabled, if the device is in CPU Idle or

Sleep mode.

Independent of the timer being enabled, the input

capture module will wake-up from the CPU Sleep or

Idle mode when a capture event occurs, if ICM<2:0> =

111 and the inte rrupt enab le bit is ass erte d. The same

wake-u p can gen erate an int errupt, if the conditi ons for

processing the interrupt have been satisfied. The

wake-up feature is useful as a method of adding extra

external pin interrupts.

10.2.1 INPUT CAPTURE IN CPU SLEEP

MODE

CPU Sleep mode allows input capture module opera-

tion with reduced functionality. In the CPU Sleep

mode, the ICI<1:0> bits are not applicable, and the

input capture module can only function as an external

inter rupt so urc e.

The capture module must be configured for interrupt

only on the rising edge (ICM<2:0> = 111), in order for

the input capture module to be used while the device

is in Sleep m ode. Th e pre scale s etting s of 4:1 or 16: 1

are not applicable in this mode.

10.2.2 INPUT CAPTURE IN CPU IDLE

MODE

CPU Idle mode allows input capture module operation

with full functionality. In the CPU Idle mode, the Inter-

rupt mode selected by the ICI<1:0> bits are applicable,

as well as the 4:1 and 16:1 capture prescale settings,

which are defined by control bits ICM<2:0>. This mode

requires the selected timer to be enabled. Moreover, the

ICSIDL bit must be asserted to a logic ‘0’.

If the input capture module is defined as ICM<2:0> =

111 in CPU Idle mode, the input capture pin will serve

only as an external interrupt pin.

10.3 Input Capture Interrupts

The inpu t captur e channe ls have the a bility to generate

an interrupt, based upon the selected number of cap-

ture even ts. Th e s ele cti on num be r is se t by c ontrol bits

ICI<1:0> (ICxCON<6:5>).

Each chan nel provide s an interrupt flag (ICxI F) bit. The

respective capture channel interrupt flag is located in

the corresponding IFSx STATUS register.

Enabling an interrupt is accomplished via the respec-

tive capture channel interrupt enable (ICxIE) bit. The

capture interrupt enable bit is located in the

corresponding IEC Control register.

dsPIC30F1010/202X

TABLE 10-1: INPUT CAPTURE REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu

IC1CON 0142 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F1010/202X

11.0 OUTPUT COMPARE MODULE

This section describes the Output Compare module

and associated operational modes. The features pro-

vided by this module are useful in applica tions requiring

operational modes such as:

• Generation of Variable Width Output Pulses

• Pow er Fact or Correction

Figure 11-1 depicts a block diagram of the Output

Compare module.

The key operational features of the Output Compare

module include:

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Output Compare during Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

These operating modes are determined by setting

the appropriate bit s in the 16-b it OCxCO N SFR (where

x = 1 and 2).

OCxRS and OCxR in the figure represent the Dual

Compare registers. In the Dual Compare mode, the

OCxR register is used for the f irst comp are and O CxRS

is used for the second compare.

FIGU RE 11-1: OUTPUT COMPARE MO DE BLOC K DIAG RAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

OCxR

Comparator

Output

Logic QS

OCM<2:0>

Output Enable

OCx

Set Fla g bit

OCxIF

OCxRS

Mode Select

Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare

channels 1 and 2.

OCTSEL 01

T2P2_MATCH

TMR2<15:0 TMR3<15:0> T3P3_MATCH

From General Pupose

OCFLTA

Timer Module

dsPIC30F1010/202X

11.1 T imer2 and Timer3 Selecti on Mode

Each output compare channel can select between one

of two 16-bit timers: Timer2 or Timer3.

The selection of the timers is controlled by the OCTSEL

bit (OCxCON<3> ). T im er2 is the de fault ti mer reso urce

for the Output Compare module.

11.2 Simple Output Compare Match

Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 001,

010 or 011, the selected output compare channel is

configured for one of three simple Output Compare

Match modes:

• Compare forces I/O pin low

• Compare forces I/O pin high

• Compare toggles I/O pin

The OCxR reg is ter i s us ed in th es e m ode s. Th e O C xR

selected incrementing timer count. When a compare

occurs, o ne of these C ompare Match modes oc curs. If

the counter resets to zero before reaching the value in

OCxR, the state of the OCx pin remains unchanged.

11.3 Dual Output Compare Match Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 100

or 101, the selec ted outp ut compare channel is co nfig-

ured for one of two Dual Output Compare modes,

which are:

• Single Output Pulse mode

• Conti nuous Output Pulse mode

11.3.1 SINGLE PULSE MODE

For the use r to confi gure the modul e for the ge ner ation

of a single output pulse, the following steps are

required (assuming the timer is off):

• Determine instruction cycle time TCY.

• Calcu la te d es ired pulse w id t h v al ue based on TCY.

• Calcu late ti me to s tart pulse from ti mer st a rt valu e

of 0x0000.

• Write pulse width start and stop times into OCxR

and OCxRS compare registers (x denotes

channel 1, 2).

• Set timer period register to value equal to, or

greater than, value in OCxRS compare register.

• Set OCM<2:0> = 100.

• Enable timer, TON (TxCON<15>) = 1.

To initiate another single pulse, issue another write to

set OCM<2:0> = 100.

11.3.2 CONTINUOUS PULSE MODE

For the use r to confi gure the modul e for the ge neratio n

of a continuous stream of output pulses, the following

steps are required:

• Determine instruction cycle time TCY.

• Calculate desired pulse value based on TCY.

• Calcu late timer to st art pulse width from timer sta rt

value of 0x0000.

• Write pulse width start and stop times into OCxR

and OCxRS (x denotes channel 1, 2) compare

registers, respectively.

• Set timer period register to value equal to, or

greater than, value in OCxRS compare register.

• Set OCM<2:0> = 101.

• Enable timer, TON (TxCON<15>) = 1.

11.4 Sim p le PW M Mo d e

When control bits OCM<2:0> (OCxCON<2:0>) = 110

or 111, the se lected output co mp are chan nel is co nfig-

ured for th e PWM mode of opera tion. When co nfigured

for the PWM mode of operation, OCxR is the Ma in latch

(read-only) and OCxRS is the secondary latch. This

enables glitchless PWM transitions.

The user must perform the following steps in order to

configure the output compare module for PWM

operation:

1. Set the PWM pe riod by writing to the appropriate

period register.

2. Set the PWM duty cy cle by writ ing to the OCxRS

3. Configure the output compare module for PWM

operation.

4. Set the TMRx prescale value and enable the

Timer, TON (TxCON<15>) = 1.

dsPIC30F1010/202X

11.4.1 PWM PERIO D

The PWM peri od is spe cified by writing to the PRx reg-

ister. The PWM period can be calculated using

Equation 11-1.

EQUATION 11-1: PWM PERIOD

PWM frequency is defined as 1/[PWM period].

When the selected TMRx is equal to its respective

period register, PRx, the following four events occur on

the next increment cycle:

• TMRx is cleared.

• The OCx pin is set.

- Exception 1: If PWM duty cycle is 0x0000,

the OCx pin will remain low.

- Exception 2: If duty cy cle is greater tha n PRx,

the pin will remain high.

• The PWM duty cycle is latched from OCxRS into

OCxR.

• The corresponding timer interrupt flag is set.

See Figure 11-1 for key PWM period comparisons.

Timer3 is referred to in the figure for clarity.

11.4.2 PWM WITH FAULT PROTECTION

INPUT PIN

When control bits OCM<2:0> (OCxCON<2:0>) = 111,

Fault prote ction is enab led via the OCFLTA pin. If th e a

logic ‘ 0’ is detect ed on the OCF L TA pin, the outpu t pins

are placed in a high-impedance state. The state

remains until:

• the external Fault condition has been removed

and

• the PWM mode is reenabled by writing to the

appropriate control bits

As a result of the Fa ult condition, the OCxIF interrupt is

asserte d, and an interrupt will be genera ted, if enabled.

Upon detection of the Fault condition, the OCFLTx bit

in the OCxCON register is asserted high. This bit is a

read-only bit and will be cleared on ce the extern al Fault

condition has been removed, and the PWM mode is

reenabled by writing the appropriate mode bits,

OCM<2:0> in the OCx C ON register.

1 1.5 Output Compare Operation During

CPU Sleep Mode

When the CPU enters the Sleep mode, all internal

clocks are stopped. Therefore, when the CPU enters

the Sleep state, the output compare channel will drive

the pin to the active state that was observed prior to

entering the CPU Sleep state.

For example, if the pin was high when the CPU

entered the Sleep state, the pin will remain high. Like-

wise, if the pin was low when the CPU entered the

Sleep state, the pin will remain low. In either case, the

output compare module will resume operation when

the device wakes up.

1 1.6 Output Compare Operation During

CPU Idle Mode

When the CPU enters the Idle mode, the output

compare module can operate with full functionality.

The output compare channel will operate during the

CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at

logic ‘ 0’ and th e selected time base (Timer2 or Timer3)

is enabled and the TSIDL bit of the selected timer is

set to logic ‘0’.

PWM period = [(PRx) + 1] • 4 • TOSC •

(TMRx prescale value)

dsPIC30F1010/202X

FIGURE 11-1: PWM OUTPUT TIMING

11.7 Output Compare Interrupts

The outpu t compare channels ha ve the abilit y to gener-

ate an interrupt on a compare match, for whichever

Match mode has been selected.

For all modes except the PWM mode, when a compare

event occurs, the respective interrupt flag (OCxIF) is

asserte d an d an in terru pt w ill b e ge nerated, if e na ble d.

The OCxIF bit is located in the corresponding IFS

STA TUS re gister, and must be clea red in so ftware. The

interrupt is enabled via the respective compare inter-

rupt enable (OCxIE) bit, located in the corresponding

IEC Control registe r.

For the PWM mode, when an e vent occurs, the res pec-

tive timer interrupt flag (T2IF or T3IF) is asserted and

an interrupt will be generated, if enabled. The IF bit is

located in the IFS0 STATUS register, and must be

cleared in software. The interrupt is enabled via the

respective timer interrupt enable bit (T2IE or T3IE),

located in the IEC0 Control register. The output com-

pare i nterrupt flag is ne ver set durin g the PWM mode of

operation.

Period

Duty Cycle

TMR3 = Duty Cycle (OCxR) TMR3 = Duty Cycle (OCxR)

TMR3 = PR3

T3IF = 1

(Interrupt Flag)

OCxR = OCxRS

TMR3 = PR3

(Interrupt Flag)

OCxR = OCxRS

T3IF = 1

dsPIC30F1010/202X

TABLE 11-1: OUTPUT COMPARE REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

OC1RS 0180 Output Compare 1 Slave Register 0000 0000 0000 0000

OC1R 0182 Output Compare 1 Master Register 0000 0000 0000 0000

OC1CON 0184 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000

OC2RS 0186 Output Compare 2 Slave Register 0000 0000 0000 0000

OC2R 0188 Output Compare 2 Master Register 0000 0000 0000 0000

OC2CON 018A ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F1010/202X

NOTES:

dsPIC30F1010/202X

12.0 POWER SUPPLY PWM

The Power Supply PWM (PS PWM) module on the

dsPIC30F1010/202X device supports a wide variety of

PWM modes and output formats. This PWM module is

ideal for power conversion applications such as:

• DC/DC converters

• AC/DC power supplies

• Uninterruptable Power Supply (UPS)

12.1 Features Overview

The PS PWM module incorporates these features:

• Four PWM generators with eight I/O

• Four Independent time bases

• Duty cycle resolut ion of 1.1 nsec @ 30 MI PS

• Dead-time resolution of 4.2 nsec @ 30 MIPS

• Phase-shift resolution of 4.2 nsec @ 30 MIPS

• Frequency resolution of 8.4 nsec @ 30 MIPS

• Supported PWM modes:

- Standard Edge-Aligned PWM

- Complementary PWM

- Push-Pull PWM

- Multi-Phase PWM

- Variable Phase PWM

- Fixed Off-Time PWM

- Current Reset PWM

- Current-Limit PWM

- Independent Time Base PWM

• On-the-Fly chang es to:

- PWM frequency

- PWM duty cycle

- PWM phase shift

• Output ove rrid e cont rol

• Independent current-limit and Fault inputs

• Special event comparator for scheduling other

peripheral events

• Each PWM generator has comparator for

triggering ADC conversions.

Figure 12-1 conceptualizes the PWM module in a sim-

plified block diagram. Figure 12-2 illustrates how the

module hardware is partitioned for each PWM output

pair for the Complementary PWM mode. Each func-

tional unit of the PWM module is discussed in

subsequent sections.

The PWM modu le contai ns four PWM generators . The

module has eight PWM output pins: PWM1H, PWM1L,

PWM2H, PWM2L, PWM3H, PWM3L, PWM4H and

PWM4L. For complementary outputs, these eight I/O

pins are grouped into H/L pairs.

12.2 Description

The PWM module is designed for applications that

require (a) high resolution at high PWM frequencies,

(b) the ability to drive standard push-pull or half bridge

convert ers o r (c) the ability to c r ea te m ul ti -p has e PWM

outputs.

Two commo n, me diu m-p ower converter topol og ies a re

Push-Pull and Half-Bridge. These designs require the

PWM output signal to be switched between alternate

pins, as provided by the Push-Pull PWM mode.

Phase-shifted PWM describes the situation where

each PWM generator provides outputs, but the phase

relationship between the generator outputs is

specifiable and changeable.

Multi-Phase PWM is often used to improve DC-DC

convert er lo ad tran sient res pon se , an d reduce th e s iz e

of output filter capacitors and inductors. Multiple DC/

DC converters are often operated in parallel but phase

shifted in time. A single PWM output operating at 250

KHz has a period of 4 µsec. But an array of four PWM

channel s, stag gered by 1 µsec each, y ields an effectiv e

switc hing f requenc y of 1 MH z. Mu lti-pha se PWM appli-

cations typically use a fixed-phase relationship.

Variable Phase PWM is useful in Zero Voltage Transi-

tion (ZVT) po wer conv erters. Here t he PWM duty cycl e

is always 50%, and the power flow is controlled by

varying the relative phase shift between the two PWM

generators.

Note: The PLL must be enabled for the PS PWM

module to function. This is achieved by using the

FNOSC<1:0> bits in the FOSCSEL Configuration

dsPIC30F1010/202X

FIGU RE 12-1: SIM PL I FI ED CO N CE PTU AL BL OCK D I AG RA M OF P OW ER SU P PL Y P WM

MUX

Latch

Comparator

Timer

PDC2

Phase

MUX

Latch

Comparator

Timer

PDC3

Phase

MUX

Latch

Comparator

Timer

PDC4

Phase

MUX

Latch

Comparator

Timer

PDC1

PWMCONx

LEBCONx

Channel 1

Dead-time Generator

PTCON

SEVTCMP

Comparator Special Event

IOCONx

PWM enable and mode control

Channel 3

Dead-time Generator

Channel 4

Dead-time Generator

ALTDTRx, DTRx Dead-time Control

Special Event

Postscaler

SFLTX

PWM3L

PWM3H

PWM2L

PWM2H

16-bit Data Bus

PWM1L

PWM1H

FLTCONx

Pin and mode control

MDC

ADC Trigger Control

Master Duty Cycle Reg

Fault mode and pin control

Pin override control

Special event

PTPER

T imer Period

PWM GEN #1

PWM GEN #2

PWM GEN #4

PTMR

Master Time Base

Phase

PWM GEN #3

Channel 2

Dead-time Generator

PWM4L

PWM4H

PWM User, Current Limit and Fault Override and Routing Logic

Fault CLMT Override Logic

Trigger

comparison value

IFLTX

Fault Control

Logic

TRGCONx

Control for blanking external input signals

External T ime Base

Synchronization SYNCO

SYNCI

© 2006 Microchip Technology Inc. Preliminary DS70178C-page 109
dsPIC30F1010/202X
FIGURE 12-2: PARTITIONED OUTPUT PAIR, COMPLEMENTARY PWM MODE
12.3 Control Registers
The following registers control the operation of the
Power Supply PWM Module.
• PTCON: P WM Time Base Control Register
• PTPER: Primary Time Base Register
• SEVTCMP: PWM Special Event Compare Regis-
ter
• MDC: PWM Master Duty Cycle Register
• PWMCONx: PWM Control Register
• PDCx: PWM Generator Duty Cycle Register
• PHASEx: PWM Phase-Shift Register 
(PWM Period Register when module is 
configured for individual period mode)
• DTRx: PWM Dead-Time Register
• ALTDTRx: PWM Alternate Dead-Time Register
• TRGCONx: PWM TRIGGER Control Register
• IOCONx: PWM I/O Control Register
• FCLCONx: PWM Fault Current-Limit Control 
Register
• TRIGx: PWM Trigger Compare Value Register
• LEBCONx: Leading Edge Blanking Control Register
PWM Duty Cycle Register
Duty  Cycle Comparator
Fault Overri de Values
Channel override values
Fault Pin Assignment Logic
Fault  Pin
  
PWMXH
PWMXL
TMR < PDC PWM
Override 
Logic
Dead 
Time 
Logic
Fault Active
Phase Offset
M
U
X
M
U
X
Timer/Counter

dsPIC30F1010/202X

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SYNCEN SYNCSRC<2:0> SEVTPS<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PTEN: PWM Module Enable bit

1 = PWM module is enabled

0 = PWM module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit

1 = PWM time base halts in CPU Idle mode

0 = PWM time base runs in CPU Idle mode

bit 12 SESTAT: Special Event Interrupt Status bit

1 = Special Event Interrupt is pending

0 = Special Event Interrupt is not pending

bit 11 SEIEN: Special Event Interrupt Enable bit

1 = Special Event Interrupt is enabled

0 = Special Event Interrupt is disabled

bit 10 EIPU: Enable Immediate Period Updates bit

1 = Active Period register is updated immediately

0 = Act ive P eriod register updat es occur on P WM cycle boundaries

bit 9 SYNCPOL: Synchronize Input Polarity bit

1 = SYNCIN polarity is inverted (low active)

0 = SYNCIN is high active

bit 8 SYNCOEN: Primary Time Base Sync Enable bit

1 = SYNCO output is enabled

0 = SYNCO output is disabled

bit 7 SYNCEN: External Time Base Synchronization Enable bit

1 = External synchronization of primary time base is enabled

0 = External synchronization of primary time base is disabled

bit 6-4 SYNCSRC<2:0>: Sync Source Selection bits

000 = SYNCI

001 = Reserved

111 = Reserved

bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

| |

1111 = 1:16 Postscale

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTPER <15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

PTPER <7:3> — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Primary Time Base (PTMR) Period Value bits

bit 2-0 Unimplemented: Read as ‘0’

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SEVTCMP <15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

SEVTCMP <7:3> — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Special Event Compare Count Value bits

bit 2-0 Unimplemented: Read as ‘0’

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

MDC<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

MDC<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 Master PWM Duty Cycle Value bits(1)

Note 1: The minimum value for this register is 0x0008 and the maximum value is 0xFFEF.

HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS

bit 15 bit 8

R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

DTC<1:0> — — — — XPRES IUE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 FLTSTAT: Fault Interrupt Status

1 = Fault Interrupt is pending

0 = No Fault Interrupt is pending

This bit is cleared by setting FLTIEN = 0.

Note: Software must clear the interrupt status here, and the corresponding IFS bit in Interrupt

Controller.

bit 14 CLSTAT: Current-Limit Interrupt Status bit

1 = Current-limit interrupt is pending

0 = No current-limit interrupt is pending

This bit is cleared by setting CLIEN = 0.

Note: Software must clear the interrupt status here, and the corresponding IFS bit in Interrupt

Controller.

bit 13 TRGSTAT: Trigger Interrupt Status bit

1 = Trigger interrupt is pending

0 = No trigger interrupt is pending

This bit is cleared by setting TRGIEN = 0.

bit 12 FLTIEN: Fault Interrupt Enable bit

1 = Fault interrupt enabled

0 = Fault interrupt disabled and FLTSTAT bit is cleared

dsPIC30F1010/202X

bit 11 CLIEN: Current-Limit Interrupt Enable bit

1 = Current-limit interrupt enabled

0 = Current-limit interrupt disabled and CLSTAT bit is cleared

bit 10 TRGIEN: Trigger Interrupt Enable bit

1 = A trig ger event generates an interru pt reque s t

0 = Trigger event interrupts are disabled and TRGSTAT bit is cleared

bit 9 ITB: Independent Time Base Mode bit

1 = Phasex register provides time base period for this PWM generator

0 = Primary time base provides timing for this PWM generator

bit 8 MDCS: Master Duty Cycle Register Select bit

1 = MDC register provides duty cycle information for this PWM generator

0 = DCx register provides duty cycle information for this PWM generator

bit 7-6 DTC<1:0>: Dead-time Control bits

00 = Positive dead time actively applied for all output modes

01 = Negative dead time actively applied for all output modes

10 = Dead-time function is disabled

11 = Reserved

bit 5-2 Unimplemented: Read as ‘0’

bit 1 XPRES: External PWM Reset Control bit

1 = Current-limit source resets time base for this PWM generator if it is in independent time base

mode

0 = External pins do not affect PWM time base

bit 0 IUE: Immediate Update Enable bit

1 = Updates to the active PDC registers are immediate

0 = Updates to the active PDC registers are synchronized to the PWM time base

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDCx<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDCx<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PWM Generator #x Duty Cycle Value bits(1)

Note 1: The minimum value for this register is 0x0008 and the maximum value is 0xFFEF.

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PHASEx<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

PHASEx<7:2> — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-2 PHASEx<15:2>: PWM Phase-Shift Value or Independent T ime Base Period for this PWM Generator bits

Note: If used as an independent time base, bits <3:2> are not used.

bit 1-0 Unimplemented: Read as ‘0’

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

——DTRx<13:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

DTRx<7:2> — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13-2 DTRx<13:2>: Unsigned 12-bit Dead-Time Value bits for PWMx Dead-Time Unit bits

bit 1-0 Unimplemented: Read as ‘0’

dsPIC30F1010/202X

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— ALTDTRx<13:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

ALTDTR <7:2> — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13-2 ALTDTRx<13:2>: Unsigned 12-bit Dead-Time Value bits for PWMx Dead-Time Unit

bits

bit 1-0 Unimplemented: Read as ‘0’

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TRGDIV<2:0> — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

——TRGSTRT<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 TRGDIV<2:0>: Trigger Output Divider bits

000 = Trigger output for every trigger event

001 = Trigger output for every 2nd trigger event

010 = Trigger output for every 3rd trigger event

011 = Trigger output for every 4th trigger event

100 = Trigger output for every 5th trigger event

101 = Trigger output for every 6th trigger event

110 = Trigger output for every 7th trigger event

111 = Trigger output for every 8th trigger event

bit 12-6 Unimplemented: Read as ‘0’

bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits

This value specifies the ROLL counter value needed for a match that will then enable the trigger

pos tscaler logic to begin counting trig ger events.

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> — OSYNC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PENH: PWMH Output Pin Ownership bit

1 = PWM module controls PWMxH pin

0 = GPIO module controls PWMxH pin

bit 14 PENL: PWML Output Pin Ownership bit

1 = PWM module controls PWMxL pin

0 = GPIO module controls PWMxL pin

bit 13 POLH: PWMH Output Pin Polarity bit

1 = PWMxH pin is low active

0 = PWMxH pin is high active

bit 12 POLL: PWML Output Pin Polarity bit

1 = PWMxL pin is low active

0 = PWMxL pin is high active

bit 11-10 PMOD<1:0>: PWM #x I/O Pin Mode bits

00 = PWM I/ O pin pair is in the Complementary Output mode

01 = PWM I/O pin pair is in the Independent Output mode

10 = PWM I/O pin pair is in the Push-Pull Output mode

11 = Reserved

bit 9 OVRENH: Override Enable for PWMxH Pin bit

1 = OVRDAT<1> provides data for output on PWMxH pin

0 = PWM generator provides data for PWMxH pin

bit 8 OVRENL: Overri de En able for PW MxL Pin bit

1 = OVRDAT<0> provides data for output on PWMxL pin

0 = PWM generator provides data for PWMxL pin

bit 7-6 OVRDAT<1:0>: Data for PWMxH,L Pins if Override is Enabled bits

If OVERENH = 1 then OVR DAT<1> provides data for PWMx H

If OVERENL = 1 then OVRDAT<0> provides data for PWMxL

bit 5-4 FLTDAT<1:0>: Data for PWMxH,L Pins if FLTM ODE is Enabled bits

If Fault active, then FLTDAT<1> provides data for PWMxH

If Fault active, then FLTDAT<0> provides data for PWMxL

bit 3-2 CLDAT<1:0>: Data for PWMxH,L Pins if CLMODE is Enabled bits

If current limit active, then CLDAT<1> provides data for PWMxH

If current limit active, then CLDAT<0> provides data for PWMxL

bit 1 Unimplemented: Read as ‘0’

bit 0 OSYNC: Output Override Synchronization bit

1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base

0 = Output overrides via the OVDDAT<1:0> bits occur on next clock boundary

dsPIC30F1010/202X

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — CLSRC<3:0> CLPOL

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CLMODE FLTSRC<3:0> FLTPOL FLTMOD<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-9 CLSRC<3:0>: Current-Limit Control Signal Source Select for PWM #X Generator bits

0000 = Analog Comparator #1

0001 = Analog Comparator #2

0010 = Analog Comparator #3

0011 = Analog Comparator #4

0100 = Reserved

0101 = Reserved

0110 = Reserved

0111 = Reserved

1000 = Shared Fault #1 (SFLT1)

1001 = Shared Fault #2 (SFLT2)

1020 = Shared Fault #3 (SFLT3)

1011 = Shared Fault #4 (SFLT4)

1100 = Reserved

1101 = Independent Fault #2 (IFLT2)

1110 = Reserved

1111 = Independent Fault #4 (IFLT4)

bit 8 CLPOL: Current-Limit Polarity for PWM Generator #X bit

1 = The selected current-limit source is low active

0 = The selected current-limit source is high active

bit 7 CLMODE: Current-Limit Mode Enable for PWM Generator #X bit

1 = Current-limit function is enabled

0 = Current-limit function is disabled

dsPIC30F1010/202X

bit 6-3 FLTSRC<3:0>: Fault Control Signal Source Select for PWM Generator #X bits

0000 = Analog Comparator #1

0001 = Analog Comparator #2

0010 = Analog Comparator #3

0011 = Analog Comparator #4

0100 = Reserved

0101 = Reserved

0110 = Reserved

0111 = Reserved

1000 = Shared Fault #1 (SFLT1)

1001 = Shared Fault #2 (SFLT2)

1020 = Shared Fault #3 (SFLT3)

1011 = Shared Fault #4 (SFLT4)

1100 = Reserved

1101 = Independent Fault #2 (IFLT2)

1110 = Reserved

1111 = Independent Fault #4 (IFLT4)

bit 2 FLTPOL: Fault Polarity for PWM Generator #X bit

1 = The selected Fault source is low active

0 = The selected Fault source is high active

bit 1-0 FLTMOD<1:0>: Fault Mo de for PWM Ge nerator #x bits

00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition)

01 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle)

10 = Reserved

11 = Fault input is disabled

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TRGCMP<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

TRGCMP<7:3> — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 TRGCMP<15:3>: Trigger Contro l Value bits(1)

Registe r co nt ai ns the com p a re v alu e for PWMx tim e b as e for g ene rati ng a trigger to th e ADC mod ule

for initiating a sample and conversion process, or generating a trigger interrupt.

bit 2-0 Unimplemented: Read as ‘0’

Note 1: The minimum usable value for this register is 0x0008

A value of 0x0000 does not produce a trigger.

If the TRIG x v al ue i s b ein g c alc ul ated base d on duty c yc le va lue , y ou mus t e nsu re th at a mi nimum TRIGx

value is written into the register at all times.

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

LEB<7:3> — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PHR: PWMH Rising Edge Trigger Enable bit

1 = Rising edge of PWMH will trigger LEB counter

0 = LEB ignores rising edge of PWMH

bit 14 PHL: PWMH Falling Edge Trigger Enable bit

1 = Falling edg e of PWMH will trig ger LE B counter

0 = LEB ignores falling edge of PWMH

bit 13 PLR: PWML Risi ng Edge Trigger Enable bit

1 = Rising edge of PWML will trigger LEB counter

0 = LEB ignores rising edge of PWML

bit 12 PLF: PWML Falling Edge Trigger Enable bit

1 = Falling edge of PWML will trigger LEB counter

0 = LEB ignores falling edge of PWML

bit 11 FLTLEBEN: Fault Input Leading Edge Blanking Enable bit

1 = Leading Edge Blanking is applied to selected Fault Input

0 = Leading Edge Blanking is not applied to selected Fault Input

bit 10 CLLEBEN: Current-Limit Leading Edge Blanking Enable bit

1 = Leading Edge Blanking is applied to selected Current-Limit Input

0 = Leading Edge Bl ankin g is no t appl ied to selec ted Curre nt-Lim it Input

bit 9-3 LEB: Leading Edge Blanking for Current-Limit and Fault Inputs bits

Value is 8 nsec increments

bit 2-0 Unimplemented: Read as ‘0’

dsPIC30F1010/202X

12.4 Module Functionality

The PS PWM module is a very high-speed design that

provides capabilities not found in other PWM genera-

tors. The module supports these PWM modes:

• Standard Edge-Aligned PWM mode

• Complementary PWM mode

• Push-Pull PWM mode

• Multi-Phase PWM mode

• Variable Phase PWM mode

• Current-L im it PWM mode

• Constant Off-time PWM mode

• Current Reset PWM mode

• Independent Time Base PWM mode

12.4.1 STANDARD EDGE-ALIGNED PWM

MODE

S tandard Edge-Aligned mode (Fi gure 12-3) is the basic

PWM mode used by many power converter topologies

such as “Buck”, “Boost” and “Forward”. To create the

edge-aligned PWM, a timer/counter circuit counts

upward from zero to a sp ecified m aximum v alue for the

Period. Another register contains the value for Duty

Cycle, which is constantly compared to the timer

(Period) value. While the timer/counter value is less

than or equal to the duty cycle value, the PWM output

signal is asserted. When the timer value exceeds the

duty cycle value, the PWM signal is deasserted. When

the timer is greater than the period value, the timer is

reset, and the process repeats.

FIGURE 12-3: EDGE-ALIGNED PWM

12.4.2 COMPLEMENTARY PWM MODE

Complem entary PWM is generat ed in a manner s imilar

to st andard Edge-Aligned PWM. Complementary mode

provides a second PWM output signal on the PWML

pin that is the complement of the primary PWM signal

(PWMH). Complementary mode PWM is shown in

Figure 12-4.

FIGURE 12-4: COMPLEMENT ARY PWM

12.4.3 PUSH-PULL PWM MODE

The Push-Pull mode sho wn in Figur e 12-5 is a vers ion

of the standard Edge-Aligned PWM mode where the

active PWM signal is alternately outputted on one of

two PWM pins. There is no complementary PWM out-

put avai lable. This mode is u seful in tra nsformer-ba sed

power converters. Transformer-based circuits must

avoid any direct currents that will cause their cores to

saturate. The Push-Pull mode ensures that the duty

cycle of the two phases is identical, thus yielding a net

DC bias of zero.

FIGURE 12-5: PUSH-PULL PWM

Period

Duty Cycle

Period

Timer

Value

Timer Resets

PWMH

Value

Duty Cycle Match

Period

Duty Cycle

Period

Timer

Value

Timer Rese ts

PWMH

Value

PWML (P eriod)-( Dut y Cycle)

Duty Cycle Match

Period

Duty Cycle

Period

Timer

Value

Timer Resets

PWMH

Value

PWML Duty Cycle

Duty Cycle Match

dsPIC30F1010/202X

12.4.4 MULTI-PHASE PWM MODE

Multi-Phase PWM, as shown in Figure 12-6, uses

phase-shift values in the Phase registers to shift the

PWM outputs relative to the primary time base.

Because the phase-shift values are added to the pri-

mary time base, the phase-shifted outputs occur earlier

than a PWM cha nnel that s pec if ies ze ro phase sh ift . In

Multi-Ph ase mod e, the spec ifi ed ph as e shi ft is fi xed by

the application’s design.

FIGURE 12-6: MULTI-PHASE PWM

12.4.5 VARIABLE PHASE PWM MODE

Figure 12-7 shows the waveforms for Variable Phase-

Shift PWM . Power-converte r circuits const antly chang e

the phase shift among PWM channels as a means to

control the flow of power, in contrast to most PWM cir-

cuit s that vary the duty cy c le o f PWM s ign al s to contro l

power flow. Often, in variable phase applications, the

PWM duty cycle is maintained at 50%. The phase-shift

value should be updated when the PWM signal is not

asserte d. Complement ary output s are availabl e in V ari-

able Phase-Shift mod e.

FIGURE 12-7: VARIABLE PHASE PWM

12.4.6 CURRENT-LIMIT PWM MODE

Figure 12-8 shows Cycle-by-Cycle Current-Limit

mode. This mode truncates the asserted PWM signal

when the selected external Fault signal is asserted.

The PWM output values are specified by the Fault

override bits (FLTDAT<1:0>) in the IOCONx register.

The override output remains in effect until the begin-

ning of the next PWM cycle. This mode is sometimes

used in Power Factor Correction (PFC) circuits where

the inductor current controls the PWM on time. This is

a constant frequency PWM mode.

FIGURE 12-8: CYCLE-BY-CYCLE

CURRENT-LIMIT PWM

MODE

Duty Cycle

PWM2H

Duty Cycle

PWM4H

Duty Cycle

PWM3H

Duty Cycle

PWM1H

Period

Phase4

Phase2

Phase3

PTMR=0

Duty CyclePWM1H

Period

Duty Cycle

Phase2 (old value)

Duty Cycle

PWM2H

Phase2 (new value)

Duty Cycle

Period

Timer

Value

PWMH

Value

FLTx Negates PWM

Duty Cycle

Programmed

Duty

Cycle

Programmed

Duty Cycle

PWMH Duty Cycle

Actual Actual

FLTx Negates PWM

dsPIC30F1010/202X

12.4.7 CONSTANT OFF-TIME PWM

Constant Off-Time mode is shown in Figure 12-9.

Constant Off-Time PWM is a variable-frequency mode

where the actual PWM period is less than or equal to

the specified period value. The PWM time base is

externally reset some time after the PWM signal duty

cycle value has been reached, and the PWM signal ha s

been deasserted. This mode is implemented by

enabling the On-Time PWM mode (Current Reset

mode) and using the complementary output.

FIGURE 12-9: CONSTANT OFF-TIM E

PWM

12.4.8 CURRENT RESET PWM MODE

Current Reset PWM is shown in Figure 12-10. Current

Reset PWM uses a Variable-Frequency mode where

the actual PWM period is less tha n or equal to the spec-

ified period value. The PWM time base is externally

reset some time after the PWM signal duty cycle value

has bee n reached and t he PWM si gnal h as been d eas-

serted. Current Reset PWM is a constant on-time PWM

mode.

FIGURE 12-10: CURRENT RESET PWM

Typically, in the converter application, an energy stor-

age inductor is charged with current while the PWM

signal is asserted, and the inductor current is dis-

charged by the load when the PWM signal is deas-

serted. In this application of current reset PWM, an

external c urre nt me asu r ement circ uit de term in es whe n

the induc tor is discha rged, and then generates a si gnal

that the PWM module uses to reset the time base

counter. In Curren t Reset mode, com pl em en t ary

outputs are available.

12.4.9 INDEPENDENT TIME BASE PWM

Independent Time Base PWM, as shown in

Figure 12-11, is often used when the dsPIC DSC is

controlling different power converter subcircuits such

as the Power Factor Correction circuit, which may use

100 kHz PWM, and the full-bridge forward converter

section may use 250 kHz PWM.

FIGURE 12-11: INDEPENDENT TIME

BASE PWM

Duty Cycle

Period

Timer

Value

Programmed Period

PWML

Value

External Timer Reset

Duty Cycle

Actual Period

External Timer Reset

Note: Duty Cycle represents off time

Duty Cycle

Period

Timer

Value

Programmed Per iod

PWMH

Value

External Timer Reset

Duty Cycle

Actual Period

External Timer Rese

Programmed Period

Duty Cycle

PWM2H

Duty Cycle

PWM4H

Duty Cycle

PWM3H

Duty Cycle

PWM1H

Period 4

Period 2

Period 3

Period 1

Note: With independent time bases,

PWM signals are no longer

phase related to each other.

dsPIC30F1010/202X

12.5 Primary PWM Time Base

There is a Primary Time Base (PTMR) counter for the

enti re P WM mo du le , In ad d it i on , ea ch P WM ge ne rat o r

has an individual time base counter.

The PTMR determines when the individual time base

counters are to update their duty cycle and phase-shift

registers. The master time base is also responsible for

generati ng the Specia l Even t Triggers a nd tim er-based

interrupts. Figure 12-12 shows a block diagram of the

primary time base logic.

FIGURE 12-12: PTMR BLOCK DIAGRAM

The primary time base may be reset by an external

signal specified via the SYNCSRC<2:0> bits in the

PTCON register. The external reset feature is enabled

via the SYNCEN bit in the PTCON register. The pri-

mary time base reset feature supports synchronization

of the primary time base with another SMPS dsPIC

DSC device or other circuitry in the user ’s application.

The primary time base logic also provides an output

signal w hen a per iod matc h o cc urs tha t c an be us ed to

synchronize an external device such as another

SMPS dsPIC DSC.

12.5.1 PTMR SYNCHRONIZATION

Because absolute synchronization is not possible, the

user should program the time base period of the sec-

ondary (slave) device to be slightly larger than the pri-

mary device time base to ensure that the two time

bases will reset at the same time.

12.6 Primary PWM Time Base Roll

Counter

The primary time base has an additional 6-bit counter

that counts the period matches of the primary time

base. This ROLL counter enables the PWM genera-

tors to stagger their trigger events in time to the ADC

module. This counter is not accessible for reading.

Each PWM generator has six bi ts (TRG STRT<5:0>) in

the TRGCONx registers. These bits are used to spec-

ify the start enable for each TRIGx postscaler con-

trolled by the TRGDIV<2:0> bits in the TRGCONx

registers.

The TRGDIV bits specify how frequently a trigger

pulse is generated, and the ROLL bits specify when

the sequence begins. Once the TRIG postscaler is

enabled, the ROLL bits and the TRGSTRT bits have

no further effect until the PWM module is disabled and

then reenabl ed.

The purpose of the ROLL counter and the TRGSTRT

bits is to all ow th e use r to s pre ad the s ys tem wo rk load

over a series of PWM cycles.

An additional use of the ROLL counter is to allow the

internal FRC oscillator to be varied on a PWM cycle

basis to reduce peak EMI emissions generated by

switching transistors in the power conversion

application.

The ROLL counter is cleared when the PWM module

is disabl ed (P TEN = 0), and the TRIGx posts ca ler s a r e

disabled, requiring a new ROLL versus TRGSTRT

match to begin counting again.

12.7 Individual PWM Time Base(s)

Each PWM generator also has its own PWM time

base. Figure 12-13 shows a block diagram for the indi-

vidual time base circuits. With a time base per PWM

generator, the PWM module can generate PWM out-

puts that are phase shifted relative to each other, or

totally independent of each other. The individual PWM

timers (TMRx) provide the time base values that are

compared to the duty cycle registers to create the

PWM signals. The user may initialize these individual

time base counters before or during operation via the

phase-shift registers. The primary (PTMR) and the

individual timers (TMRx) are not user readable.

PTMR

PERIOD

Equality Comparator

Clk

Reset

PR_MATCH

dsPIC30F1010/202X

FIGURE 12-13: TMRx BLOCK DIAGRAM

Normally, the Primary Time Base (PTMR) provides

synchronization control to the individual timer/counters

so they count in lock-step unison.

If the PWM phase-shi ft fea ture is us ed , t hen the PTMR

provides the synchronization signal to each individual

timer/counter that causes them to reinitialize with their

individual phase-shift values.

If a PWM generator is operating in Independent Time

Base mode, the individual timer/counters count

upward until their count values match the value stored

in their phase registers, then they reset and the cycle

repeats.

The primary time base and the individual time bases

are implemented as 13-bit counters. The timers/

counters are clocked at 120 MHz @ 30 MIPS, which

provides a frequency resolution of 8.4 nsec.

All of the timer/counters are enabled/disabled by set-

ting/clearing the PTEN bit in the PTCON SFR. The

timers are cleared when the PTEN bit is cleared in

software.

The PTPER register sets the counting period for

PTMR. The user must write a 13-bit value to

PTPER<15:3>. When the value in PTMR<15:3>

matches the value in PTPER<15:3>, the primary time

base is reset to ‘0’, and the individual time base

counters are reinitialized to their phase values (except

if in Independent Time Base mode).

12.8 PWM Period

PTPER holds the 13-bit value that specifies the count-

ing period for the primary PWM time base. The timer

period can be updated at any time by the user. The

PWM period can be determined from the following

formula:

Period Duration = (PTPER + 1)/120 MHz @ 30 MIPS

12.9 PWM Frequency and Duty Cycle

Resolution

The PWM Duty cycle resolution is 1.05 nsec per LSB

@ 30 MIPS. Th e PWM pe rio d res ol uti on i s 8. 4 n sec @

30 MIPS. Table 12-1 shows the duty cycle resolution

versus PWM frequencies for 30 MIPS execution speed.

TABLE 12-1: AVAILABLE PWM

FREQUENCIES AND

RESOLUTIONS @ 30 MIPS

TABLE 12-2: AVAILABLE PWM

FREQUENCIES AND

RESOLUTIONS @ 20 MIPS

Notice the reduction in available resolution for a given

PWM frequency is due to the reduced clock rate and

the fact that the LSB of duty cy cl e res olu tio n is deri ve d

from a fixed-delay element. At operating frequencies

below 30 MIPS, the contribution of the fixed-delay

element to the output resolution becomes less than

1 LSB.

For frequency resonant mode power conversion appli-

cations, it is desirable to know the available PWM fre-

quency resolution. The available frequency resolution

varies with the PWM frequency. The PWM time base

clock s at 120 MHz @ 30 MIPS . The follow i ng e qua tio n

provides the frequency resolution versus PWM period:

Frequency Resolution = 120 MHz/(Period)

where Period = PTPER<15:3>

TMRx

PTPER

Comparator

Clk

Reset

MUX

PHASEx

ITBx

15 3 15 3

15 3

MIPS PWM Duty

Cycle

Resolution PWM Frequency

30 16 bits 14.6 KHz

30 15 bits 29.3 KHz

30 14 bits 58.6 KHz

30 13 bits 117.2 KHz

30 12 bits 234.4 KHz

30 11 bits 468.9 KHz

30 10 bits 937.9 KHz

30 9 bits 1.87 MHz

30 8 bits 3.75 MHz

MIPS PWM Duty

Cycle

Resolution PWM Frequency

20 14 bits 39 KHz

20 12 bits 156 KHz

20 10 bits 624 KHz

20 8 bits 2.5 MHz

dsPIC30F1010/202X

12.10 PWM Duty Cycle Comparison

Units

The PWM module has two to four PWM duty cycle

generators. Three to five 16-bit special function regis-

ters are used to specify duty cycle values for the PWM

module:

• MDC (Master Duty Cycle)

• PDC1, ..., PDC4 (Duty Cycle)

Each PWM generator has its own duty cycle register

(PDCx), and there is a Master Duty Cycle (MDC) reg-

ister. The MDC register can be used instead of individ-

ual duty cycle registers. The MDC register enables

multiple PWM generators to share a common duty

cycle register to reduce the CPU overhead required in

updating multiple duty cycle registers. Multi-phase

power converters are an application where the use of

the MDC feature saves valuable processor time.

The value in each duty cycle register determines the

amount of time that the PWM output is in the active

state. The PWM time base counters are 13 bits wide

and increment twice per instruction cycle. The PWM

output is asserted when the timer/counter is less than

or equal to the Most Significant 13 bits of the duty

cycle register value. Each of the duty cycle registers

allows a 16-bit duty cycle to be specified. The Least

Significant 3 bits of the duty cycle registers are sent to

additional logic for further adjustment of the PWM

signal edge.

Figure 12-14 i s a block diagram of a duty cycle

comparison unit.

FIGURE 12-14: DUTY CYCLE

COMPARISON

The duty c ycle v alues can be updated at an y time. The

updat ed dut y cycle values option ally c an be hel d until

the next rollover of the primary time base before

becoming active.

12.11 Complementary PWM Outputs

Complementary PWM Output mode provides true and

inverted PWM output s on the pa ir of PWM output pins.

The com plem ent PWM signal is ge nerated by in vertin g

the active PWM signal. Complementary outputs are

normally available with all of the different PWM modes

except Push-Pull PWM and Independent PWM Output

modes.

12.12 Independent PWM Outputs

Independent PWM Output mode simply replicates the

active PWM output signal on both output pins

associated with a PWM generator.

12.13 Duty Cycle Limits

The duty cycle generators are limited to the range of

allowable values. A value of 0x0008 is the minimum

duty cyc le value that will produc e an output pulse. Thi s

value represents 8.4 nsec at 30 MIPS. This minimum

range limitation is not a problem in a real world appli-

cation because of the slew-rate limitation of the PWM

output buffers, external FET drivers, and the power

transis tors . Th e a ppl ic ati on co ntrol loop req uire s larg er

duty cycle values to achieve minimum transistor on

times.

The maximum duty cycle value is also limited to

0xFFEF.

The user is responsible for limiting the duty cycle

values to the allowable range of 0x0008 to 0xFFEF.

PDCx Register

TMRx

Compare Logic PWMx signal

MUX

MDC Register

MDCx select

Clk

Note: A duty c ycle of 0x0000 w ill p roduce a zero

PWM output, and a 0xFFFF duty cycle

value will produce a high on the PWM

output.

dsPIC30F1010/202X

12.14 Dead-Time Generation

Dead time refers to a programmable period of time,

specif ied by the Dead-T ime Reg ister (DTR) or th e ALT-

DTR register, which prevent a PWM output from being

asserted until its complementary PWM signal has been

deasserted for the s pecifie d time. Fi gure 12-15 shows

the insertion of dead time in a complementary pair of

PWM outputs. Figure 12-16 shows the four dead-time

units that each have their own dead-time value.

Dead-ti me genera tion can b e provide d when any of the

PWM I/O pin pairs are operating in any output mode.

Many power-converter circuits require dead time

because the power transistors cannot switch instanta-

neously. To prevent current “shoot-through” some

amount of time must be provided between the turn-off

event o f on e PWM o utpu t in a c om pl em entary pair and

the turn-on event of the other transistor.

The PWM m odule can also provide negative dead t ime.

Negati ve dea d tim e i s th e for ced ov erla p of the PWMH

and PWML signals. There are certain converter tech-

niques that require a limited amount of

current “shoot-through”.

The dead-time feature can be disabled for each PWM

generator. The dead-time functionality is controlled by

the DTC<1:0> bit s in the PWM CON regis te r.

FIGURE 12-15 : DEAD- TIME INSERTIO N

FOR COMPLEMENTARY

PWM

FIGURE 12-16: DEAD-TIME CONTROL

UNITS BLOCK DIAGRAM

12.14.1 DEAD-TIME GENERATORS

Each complementary output pair for the PWM module

has 12-bit down counters to produce the dead-time

insertion. Each dead-time unit has a rising and falling

edge detector connected to the duty cycle comparison

output.

Depend in g o n w h eth er t he edg e is ris in g o r fa lli ng, one

of the transitions on the complementary outputs is

delayed until the associated timer counts down to

zero. A timing diagram indicating the dead-time inser-

tion for one pair of PWM outputs is shown in

Figure 12-15.

12.14.2 AL TERNATE DEAD-TIME SOURCE

The alternate dead time refers to the dead time speci-

fied by the ALTDTR register that is applied to the com-

plementary PWM output. Figure 12-17 shows a dual

dead-time insertion using the ALTDTR register.

Note: If zer o dead time is required, the dead time

feature must be explicitly disabled in the

DTC<1:0> bit in the PWMCON register

PWM1H

PWM1L

tda tda

PWM

Generator #1

Output

DTR1 Dead-Ti me Unit

PWM1 in

PWM1H

PWM1L

ALTDR1

DTR2 Dead-Ti me Unit

PWM2 in

PWM2H

PWM2L

ALTDTR2

DTR3 Dead-Time Unit

PWM3 in

PWM3H

PWM3L

ALTDTR3

DTR4 Dead-Time Unit

PWM4 in

PWM4H

PWM4L

ALTDTR4

dsPIC30F1010/202X

FIGURE 12-17: DUAL DEAD-TIME

WAVEFORMS 12.14.3 DEAD-TIME RANGES

The amount of dead time provided by each dead-time

unit is se lected by specifyi ng a 12-bi t unsigned value in

the DTRx registers. The 12-bit dead-time counters

clock at four times the instruction execution rate. The

Least Significant one bit of the dead-time value are

processed by the Fine Adjust PWM module.

Table 12-3 shows example dead-time ranges as a

function of the device operating frequency.

TABLE 12-3: EXAMPLE DEAD-TIME

RANGES

12.14.4 DEAD-TIME INSERTION TIMING

Figure 12-18 shows how the dead-time insertion for

complementary signals is ac com pl is hed.

12.14.5 DEAD-TIME DISTORTION

For small PWM du ty cycles, the ratio of dead time to the

active PWM time may become large. In this case, the

inserted dead time introduces distortion into wave-

forms produced by the PWM module. The user can

ensure that dead-time distortion is minimized by keep-

ing the PWM du ty cycle at least three times larger tha n

the dead time.

A simila r effect oc c urs for duty cycl es at or nea r 100% .

The maximum du ty cycle used in the ap plication should

be chosen such that the minimum inactive time of the

signal is at least three times larger than the dead time.

FIGURE 12-18: DEAD-TIME INSERTION (PWM OUTPUT SIGNAL TIMING MAY BE DELAYED)

PWMH

PWML

PWMH

No dead time

Positive dead time

Negative dead ti me

DTRx ALTDTRx

MIPS Resolution Dead-Time Range

30 4.16 ns 0-17. 03 µsec

20 6.25 ns 0-25.59 µsec

90 12345678

CLOCK

PTMR

DUTY CYCLE REG

RAW PWMH

RAW PWML

PWMH OUTPUT

PWML OUTPUT

DEAD-TIME VALUE

1<10:4>

<15:4>

dsPIC30F1010/202X

12.15 Configuring a PWM Channel

Example 12-1 is a code example for configuring PWM

channel 1 to operate in complementary mode at 400

kHz, with a dead-time value of approximately 64 nsec.

It is assumed that the dsPIC30F1010/202 X is operating

on the internal fast RC oscillator with PLL in the high-

frequency range (14.55 MHz input to the PLL,

assuming industrial temperature rated part).

12.16 Speed Limits of PWM Output

Circuitry

The PWM output I/O buffers, and any attached circuits

such as FET drivers and power FETs, have limited

slew-rate capability. For very small PWM duty cycles,

the PWM output signal is low-pass filtered; no pulse

makes it through all of the circuitry.

A similar effect happens for duty cycle values near

100%. Before 100% duty cycle is reached, the output

PWM signal appears to saturate at 100%.

Users need to take such behavior into account in their

applications. In normal power conversion applications,

duty cycle values near 0% or 100% are avoided

because to reach these values is to operate in a Dis-

continuous mode or a Saturated mode where the

control loop may be non functional.

12.17 PWM Special Event Trigger

The PWM module has a Special Event Trigger that

allows A/D conversions to be s ynchroni zed to the PWM

time base. The A/D sampling and conversion time can

be programmed to occur at any point within the PWM

period. The Special Event Trigger allows the user to

minim ize the delay b etween the time when A/D conver-

sion results are acquired and the time when the duty

cycle value is updated.

The Special Event Trigger is based on the primary

PWM time base.

The PWM Special Event Trigger has one register

(SEVTCMP) and four additional control bits

(SEVTPS<3:0> in PTCON) to control it s operation. The

PTMR value that causes a Special Event Trigger is

loaded into the SEVTCMP register.

12.17.1 SPECIAL EVENT TRIGGER ENABLE

The PWM module alway s produces Spe cial Event T ri g-

ger pulses. This signal can optionally be used by the

ADC module.

12.17.2 SPECIAL EVENT TRIGGER

POSTSCALER

The PWM Sp ecia l Ev ent Trigge r ha s a pos tscal er that

allows a 1:1 to 1:16 postscale ratio. The postscaler is

configured by writing the SEVTPS<3:0> control bits in

the PTCON register.

The special event output postscaler is cleared on the

following events:

• Any write to the SEVTCMP register.

• Any devi ce reset.

12.18 Individual PWM Triggers

The PWM m odule als o features an additi onal ADC tri g-

ger outpu t for each PWM generator . This feature is very

useful when the PWM generators are operating in

Independent Time Base mode.

A block diagram of a trigger circuit is shown in

Figure 12-19. The user specifies a match value in the

TRIGx register . When the local time base counter value

matches the TRIGx value, an ADC trigger signal is

generated.

Trigger signals are always gene rate d reg ardl es s of th e

TRIGx v alue a s lon g as t he TR IGx value is le ss th an or

equal to the PWM period value for the local time base.

If the TRG IEN bit is se t in the PWMCONx reg ister , then

an interrupt request is generated.

The individual trigger outputs can be divided per the

TRGDIV<2:0> bits in the TRGCONx registers, which

allows the trigger signals to the ADC to be generated

once for every 1, 2, 3 ..., 7 trigger events.

The trigger divider allows the user to tailor the ADC

sample rates to the requirements of the control loop.

dsPIC30F1010/202X

EXAMPLE 12-1: CODE EXAMP LE FOR CONFIGURING PWM CHANNEL 1

mov #0x0400, w0 ; PWM Module is disabled, continue operation in

mov w0, PTCON ; idle mode, special event interrupt disabled,

; immediate period updates enabled, no external

; synchronization

; Set the PWM Period

mov #0x094D, w0 ; Select period to be approximately 2.5usec

mov w0, PTPER ; PLL Frequency is ~480MHz. This equates to a

; clocke period of 2.1nsec. The PWM period and

; duty cycle registers are triggered on both +ve

; and -ve edges of the PLL clock. Therefore,

; one count of the PTPER and PDCx registers

; equals 1.05nsec.

; So, to achieve a PWM period of 2.5usec, we

; choose PTPER = 0x094D

mov #0x0000, w0 ; no phase shift for this PWM Channel

mov w0, PHASE1 ; This register is used for generating variable

; phase PWM

; Select individual Duty Cycle Control

mov #0x0001, w0 ; Fault interrupt disabled, Current Limit

mov w0, PWMCON1 ; interrupt disabled, trigger interrupt,

; disabled, Primary time base provides timing,

; DC1 provides duty cycle information, positive

; dead time applied, no external PWM reset,

; Enable immediate duty cycle updates

; Code for PWM Current Limit and Fault Inputs

mov #0x0003, w0

mov w0, FCLCON1 ; Disable current limit and fault inputs

; Code for PWM Output Control

mov #0xC000, w0 ; PWM1H and PWM1L is controlled by PWM module

mov w0, IOCON1 ; Output polarities are active high, override

; disabled

; Duty Cycle Setting

mov #0x04A6, w0 ; To achieve a duty cycle of 50%, we choose

mov w0, PDC1 ; the PDC1 value = 0.5*(PWM Period)

; The ON time for the PWM = 1.25usec

; The Duty Cycle Register will provide

; positive duty cycle to the PWMxH outputs

; when output polarities are active high

; (see IOCON1 register)

; Dead Time Setting

mov #0x0040, w0 ; Dead time ~ 67nsec

mov w0, DTR1 ; Hex(40) = decimal(64)

; So, Dead time = 64*1.05nsec = 67.2nsec

; Note that the last 2 bits are unimplemented,

; therefore the dead time register can achieve a

; a resolution of about 4nsec.

mov w0, ALTDTR1 ; Load the same value in ALTDTR1 register

bset PTCON, #15 ; turn ON PWM module

Note: This code example does not illustrate configuration of various fault modes for the PWM module.

It is intended as a quick start guide for setting up the PWM Module.

dsPIC30F1010/202X

FIGURE 12-19: PWM TRIGGER BLOCK DIAGRAM

12.19 PWM Interrupts

The PWM module can generate interrupts based on

inter nal timing or based on exte rnal sig nals v ia the c ur-

rent-lim it and Fault input s. The primary time base mo d-

ule can generate an interrupt request when a special

event occurs. Each PWM generator module has its

own interrupt request signal to the interrupt controller.

The interrupt for each PWM generator is an OR of the

trigger event interrupt request, the current-limit input

event or the Fault input event for that module.

There are four interrupt request signals to the interrupt

control plus another interrupt request from the primary

time base on special events.

12.20 PWM Ti me Base Interrupts

The PWM module can generate interrupts based on

the primary time base and/or the individual time bases

in each PWM generator. The interrupt timing is speci-

fied by the Special Event Comparison Register

(SEVTCMP) for the primary time base, and by the

TRIGx registers for the individual time bases in the

PWM generator modules.

The primary time base special event interrupt is

enabl ed via t he SEI EN bit in the PTCON r egist er. The

indivi dual time bas e in terru pts generated by the trigger

logic in each PWM generator are controlled by the

TRGIEN bit in the PWMCONx registers.

12.21 PWM Fault and Current-Li m it Pins

The PWM modu le support s mult iple Fa ult pins for each

PWM generator. These pins are labeled SFLTx

(Shared Fault) or IFLTx (Individual Fault). The Shared

Fault pins can be seen and used by any of the PWM

generators. The Individual Fault pins are usable by

specific PWM generators.

Each PWM generator can have one pin for use as a

cycle-by-cycle current limit, and another pin for use as

either a c ycle-by-cycl e current limit or a latching curre nt

Fault disable function.

12.22 Leading Edge Blanking

Each PWM generator supports “Leading Edge Blank-

ing” of the current-limit and Fault inputs via the

LEB<9:3> bits and the PHR, PHF, PLR, PLF, FLTLE-

BEN and CLLEBEN bits in the LEBCONx registers.

The purpose of leading edge blanking is to mask the

transients that occur on the application printed circuit

board when the power transistors are turned on and off.

The LEB bi ts suppo rt the bl ankin g (igno ring) o f the c ur-

rent-lim it and Fau lt input s for a period of 0 to 102 4 nsec

in 8.4 nsec increments following any specified rising or

falling edge of the coarse PWMH and PWML signals.

The coarse PWM signal (signal prior to the PWM fine

tuning) has resolution of 8.4 nsec (at 30 MIPS), w hich

is the same time resolution as the LEB counters.

The PHR, PH F, PLR and PLF bit s sel ect w hich ed ge of

the PWMH and PLWL signals will start the blanking

timer. If a new selected edge triggers the LEB timer

while the timer is still active from a previously selected

PWM edge, the timer reinitializes and continues

counting.

PTMRx

Compare Logic

Clk

TRIGx Register

TRGDIV<2:0>

Pulse

Divider PWMx Trigger

15 3

PDI

TRIGx Write

dsPIC30F1010/202X

The FLTLEBEN and CLLEBEN b its en able the a pplica-

tion of the blanking period to the selected Fault and

current-limit inputs.

The LEB duration @ 30 MIPS =

(LEB<9:3> + 1)/120 MHz.

There is a blan king period of fse t of 8.4 nsec . Therefo re

a LEB<9:3> value of zero yields an effective blanking

period of 8.4 ns.

If a current-limit or Fault inputs are active at the end of

the previo us PWM c ycle, and they ar e sti ll active at the

start of the new PWM cycle and the dead time is non-

zero, the Fault or current limit will be detected

regardless of the LEB counter configuration.

12.23 PWM Fault Pins

Each PWM generator can select its own Fault input

source from a selection of up to 12 Fault/current-limit

pins. In the FCLCONx registers, each PWM generator

has control bits that specify the source for its Fault input

signal. These are the FLTSRC<3:0> bits. Additionally,

each PWM generator has a FLTIEN bit in the PWM-

CONx register that enables the generation of Fault

interrupt requests. Each PWM generator has an asso-

ciated F ault Polarity bit (FLTPOL) in the FC LCONx reg-

ister that selects the active level of the selected Fault

input.

The Fault pins actually serve two different purposes.

First is generation of Fault overrides for the PWM out-

puts. The action of overriding the PWM outputs and

generati ng an in terrupt i s perform ed as ynchro nousl y in

hardwa re so that Fault ev ents can be managed quic kly .

Second, th e Fault pin inpu t s c an b e us ed to imp le me nt

either Current-Limit PWM mode or Current Force

mode.

PWM Fault condition states are available on the FLT-

ST AT bit in the PWMCONx registers. The FL TSTA T bit s

displays the Fault IRQ latch if the FIE bit is set. If Fault

interrupts are not enabl ed, then the FSTA Tx bit s display

the status of the selected FLTx input in positive logic

format. Whe n the Fault input pi ns are not used in asso-

ciation with a PWM generator, these pins become

general purpose I/O or interrupt input pins.

The FLTx pins are normally active high. The FLTPOL

bit in FCLCONx registers, if set to one, invert the

selected Fault input signal so that it is an active low.

The Fault pi ns are also rea dable throug h the PORT I/O

logic when the PWM module is enabled. This allows

the user to poll the state of the Fault pins in software.

Figure 12-20 is a diagram of the PWM Fault control

logic.

FIGURE 12-20 : PWM FAULT CONTROL LOGIC DIAGRAM

PWMx

Generator

FLTDAT<1:0>

PWMxH,L

Signals 2

MUX

Analog C om parato r 1

Analog Comparator 2

Analog Comparator 3

Analog Comparator 4

FLTSRC<3:0>

CMP1x

CMP2x

CMP3x

CMP4x

SFLT1

SFLT2

SFLT3

SFLT4

IFLT2

IFLT4

PWMxH,L

Fault

Mode

Selection

Logic

Shared Fault # 1

Shared Fault # 2

Shared Fault # 3

Shared Fault # 4

Independent Fault # 2

Independent Fault # 4

FLTSTAT

FLTMOD<1:0>

PTMR

FLTMOD<1:0> = 00 – FLTSTAT signal is latched until Reset in software

FLTMOD<1:0> = 01 – FLTSTAT signal is Reset by PTMR every PWM cycle

FLTMOD<1:0> = 11 – FLTSTAT signal is disabled

Analog Comparator

Module

‘0000’

‘0001’

‘0010’

‘1000’

‘1001’

‘1010’

‘1011’

‘1101’

‘1111’

‘0011’

dsPIC30F1010/202X

12.23.1 FAULT INTERRUPTS

The FLTIENx bits in the PWMCONx registers deter-

mine if an interrupt will be generated when the FLTx

input is asserted high. The FLTMOD bits in the

FCLCONx register determines how the PWM genera-

tor and its outputs respond to the selected Fault input

pin. The FLTDAT<1:0> bits in the IOCONx registers

supply the da ta value s to be assi gned t o th e PWMx H,L

pins in the advent of a Fault.

The Fault pin logic can operate separately from the

PWM logic as an external interrupt pin. If the faults are

disabled from affecting the PWM generators in the

FCLCONx register , then the Fault pin can be used as a

general purp os e inter r upt pin .

12.23.2 FAULT STATES

The IOCONx register has two bits that determine the

state of each PWMx I/O pin when they are overridden

by a Fault input. When these bits are cleared, the

PWM I/O pin is driven to the inactive state. If the bit is

set, the PWM I /O pin i s driv en to t he acti ve stat e. The

active and ina ctive sta tes are re ferenc ed to the polarit y

defined for each PWM I/O pin (HPOL and LPOL

polarity control bits).

12.23.3 FAULT INPUT MODES

The Fault input pin has two modes of operation:

•Latched Mode: When the Fault pi n is asserted,

the PWM outputs go to the states defined in the

FLTDAT bits in the IOCONx registers. The PWM

outputs remain in this state until the Fault pin is

deasserted AND the corresponding interrupt flag

has be en cleare d in soft ware. When both o f th ese

actions have occurred, the PWM outputs return to

normal operation at the beginning of the next

PWM cycle boundary. If the FLTSTAT bit is

cleared before t he F ault cond ition e nds, th e PWM

module waits until the Fault pin is no longer

asserted to restore the outputs. Software can

clear the FLTSTAT bit by writing a zero to the

FLTIEN bit.

•Cycle-by-Cycle Mode: When the Fault inpu t pin

is asserted, the PWM outputs remain in the deas-

serted PWM state for as long as the Fault pin is

asserted. For Complementary Output modes,

PWMH is low (deasserted) and PWML is high

(asserted). After the Fault pin is driven high, the

PWM outputs return to normal operation at the

beginning of the following PWM cycle.

The oper ating mod e for each Fault input pin is selecte d

using the FLTMOD<1:0> control bits in the FCLCONx

12.23.4 FAULT ENTRY

The response of the PWM pins to the Fault input pins

is always asynchronous with respect to the device

clock signals. That is, the PWM outputs should imme-

diately go to the states defined in the FLTDAT register

bits wit hout a ny in teracti on from the dsPIC D SC device

or software.

Refer to Section 12.28 “Fault and Current-Limit

Override Issu es with Dead-Time Logic” for informa-

tion regarding data sensiti vity and beh avior in response

to current-limit or Fault events.

12.23.5 FAULT EXIT

The restora tion of th e PWM si gnals after a Fau lt condi-

tion has e nded must occ ur at a PWM cycle bo undary to

ensure proper synchronization of PWM signal edges

and manual signal overrides. The next PWM cycle

begins when the PTMRx value is zero.

12.23.6 FAULT EXIT WITH PTMR DISABLED

There is a special case for exiting a Fault condition

when the PWM time base is disabled (PTEN = 0).

When a Fault input is programmed for Cycle-by-Cycle

mode, the PWM outputs are immediately restored to

normal operation when the Fault input pin is deas-

serted. The PWM outputs should return to their default

programmed values. (The time base is disabled, so

there is no reason to wait for the beginning of the next

PWM cycle.)

When a Fault input is programmed for Latched mode,

the PWM outputs are restored immediately when the

Fault input pin is deasserted AND the FSTAT bit has

been cleared in software.

12.23.7 FAULT PIN SOFTWARE CONTROL

The Fault pin can be controlled manually in software.

Since the Fault input is shar ed with a POR T I/O pin, th e

PORT pin can be configured as an output by clearing

the corres pondin g TRIS bit. Whe n the PORT bit for the

pin is cleared, the Fault input will be activated.

Note: The user should use caut ion when co ntrol-

ling the Fault inputs in software. If the

TRIS bi t for the Fau lt pin is cleared and the

PORT bit is set high, then the Fault input

cannot be driven externally.

dsPIC30F1010/202X

12.24 PWM Current-Limit Pins

Each PWM generator can select its own current-limit

input source from up to12 current-limit/Fault pins. In the

FCLCONx registers, each PWM generator has control

bits (CLSRC<3:0>) that specify the source for its cur-

rent-limit input signal. Additionally, each PWM genera-

tor has a CLIEN bit in the PWMCONx register that

enables the generation of current-limit interrupt

requests. Each PWM generator has an associated

Fault polarity bit CLPOL in the FCLCONx register.

Figure 12-21 is a diagram of the PWM Current-Limit

control log ic .

The current-limit pins actually serve two different pur-

poses. They can be used to implement either Current-

Limit PWM mode or Current Reset PWM mode.

1. When the CLIEN bit is set in the PWMCONx

registers, the PWMxH,L outputs are forced to

the values specified by the CLDAT<1:0> bits in

the IOCONx register, if the sel ected curre nt-limit

input signal is as serted.

2. When the CLMOD bit is zero AND the XPRES

bit in the PWMCONx register is ‘01’ AND the

PWM generator is in Independent Time Base

mode (ITB = 1), then a current-limit signal

resets the time base for the affected PWM gen-

erator. This behavior is called Current Reset

mode, which is used in some Power Factor

Correction (PFC) applications.

12.24.1 CURRENT-LIMIT INTERRUPTS

The state of the PWM current-limit conditions is avail-

able on the CLSTAT bits in the PWMCONx registers.

The CLSTAT bits display the current-limit IRQ flag if

the CLIEN bit is set. If current-limit interrupts are not

enabled , th en the CLSTAT bits displ ay the st atus o f the

selected current-limit inputs in positive logic format.

When the current-limit input pin associated with a

PWM generator is not used, these pins become

general purpose I/O or interrupt input pins.

The current-limit pins are normally active high. If set to

‘1’, the CLPOL bit in FCLCONx registers inverts the

selected current-limit input signal to active high.

The interrupts generated by the selected current-limit

signals are combined to create a single interrupt

request signal to the interrupt controller, which has its

own interrupt vector, interrupt flag bit, interrupt enable

bit and interrupt priority bits associated with it.

The Fault pi ns are also rea dable throug h the PORT I/O

logic when the PWM module is enabled. This allows

the user to poll the state of the Fault pins in software.

FIGURE 12-21: PWM CURRENT-LIMIT CONTROL LOGIC DIAGRAM

PWMx

Generator

CLDAT<1:0>

PWMxH,L

Signals 2

MUX

Analog C ompar ato r 1

Analog Comparator 2

Analog Comparator 3

Analog C om parato r 4

CLSRC<3:0>

CMP1x

CMP2x

CMP3x

CMP4x

SFLT1

SFLT2

SFLT3

SFLT4

IFLT2

IFLT4

PWMxH,L

Shared Fault # 1

Shared Fault # 2

Shared Fault # 3

Shared Fault # 4

Independent Fault # 2

Independent Fault # 4

CLSTATXPRES

PWM Period

Reset

Analog Comparator

Module

‘0000’

‘0001’

‘0010’

‘1000’

‘1001’

‘1010’

‘1011’

‘1101’

‘1111’

‘0011’

CLMOD

dsPIC30F1010/202X

12.25 Simultaneous PWM Faults and

Current Limits

The current-limit override function, if enabled and

active, forces the PWMxH,L pins to the values speci-

fied by the CLDAT<1:0> bits in the IOCONx registers

UNLESS the Fault fun ction is enabled and active. If the

selected Fault input is active, the PWMxH,L outputs

assume the values specified by the FLTDAT<1:0> bits

in the IOCONx registers.

12.26 PWM Fault and Current- Limit TRG

Outputs To ADC

The Fault an d current-limit source selection fields in the

FCLCON x registers (FLTSRC<3:0> and CL SRC<3:0>)

control multiplexers in each PWM generator module.

The control multiplexers select the desired Fault and

current-limit signals for their respective modules. The

selected Fault and current-limit signals are also avail-

able to the ADC module as trigger signals that initiate

ADC sampling and conversion operations.

12.27 PWM Output Override Prior ity

If the PWM mo dule is enable d, the priority of PWMx pi n

ownership is:

1. PWM Generator (lowest priority)

2. Output Overri de

3. Current-L imit Ov erri de

4. Fault Override

5. PENx (GPIO/PWM) ownership (highest priority)

If the PWM module is disabled, the GPIO module

controls the PWMx pins.

12.28 Fault and Current-Limit Override

Issues with Dead-Ti me Logic

The PWMxH and PWMxL outputs are immediately

driven low (deasserted) as specified by the

CLDAT<1:0> and the FLTDAT<1:0> bits when a

current-limit or a Fault event occurs.

The ove rrid e d ata is ga ted with the PWM sign al s g oin g

into the dead-time logic block, and at the output of the

PWM module, just ahead of the PWM pin output

buffers.

Many applications require fast response to current

shutdown for accurate current control and/or to limit

circuitry damage to Fault currents.

Some applications will set the complementary

PWM outputs high in synchronous rectifier

designs when a Fault or current-limit event

occurs. If the CLDAT or FLTDAT bits are set to ‘1’,

and their associated event occurs, then these

asserted outputs will be delayed by clocked logic

in the dead-time circuitry.

12.29 Asserting Outputs via Current

Limit

It is possible to use the CLDAT bits to assert the

PWMxH,L outputs in response to a current-limit event.

Such behavior could be used as a current “force” fea-

ture in resp ons e to an ex tern al curre nt or vol t ag e mea-

suremen t that indi cates a s udden sharp inc rease in th e

load on the power-converter output. Forcing the PWM

“ON” could be viewed as a “Feed-Forward” term that

allows quick system response to unexpected load

inc reases with out waiti ng for th e digital cont rol loo p to

respond.

12.30 PWM Immediate Update

For high-performance PWM control-loop applications,

the user may want to force the duty cycle updates to

occur immediately. Setting the IUE bit in the

PWMCONx register enables this feature.

In a clos ed-loop co ntrol appli catio n, any dela y between

the sensing of a system’s state and the subsequent

outputting of PWM control signals that drive the appli-

cation reduces the loop stability. Setting the IUE bit

minimi zes the d elay between w riting the d uty cycle re g-

isters and the response of the PWM generators to that

change.

12.31 PWM Output Override

All control bits associated with the PWM output

override function are cont ained in the IO CONx r egister.

If the PENH, PENL bits are set, the PWM module

controls the PWMx output pins.

The PWM output override bits allow the user to manu-

ally drive the PWM I/O pins to specified logic states

independent of the duty cycle comparison units.

The OVRDAT<1:0> bits in the IOCONx register deter-

mine the state of the PWM I/O pins when a particular

output is overridden via the OVRENH,L bits.

The OVRENH, OVRENL bits are active high control

bits. When the OVREN bits are set, the corresponding

OVRDAT bit overrides the PWM output from the PWM

generator.

12.31.1 COMPLEMENTARY OUTPUT MODE

When the PWM is in Co mplemen tary O utput mo de, the

dead-time generator is still active with overrides. The

output overrides and Fault overrides generate control

signal s used b y the dea d-time unit to set the outputs as

requested, including dead time.

Dead-time insertion can be performed when PWM

channel s are overridden manually.

dsPIC30F1010/202X

12.31.2 OVERRIDE SYNCHRONIZATION

If the O SYNC bit i n the IOCONx regist er is s et, th e out-

put overrides performed via the OVRENH,L and the

OVDDAT<1:0> bits are synchronized to the PWM time

base. Synchronous output overrides occur when the

time base is zero.

If PTEN = 0, meani ng the time r is no t runni ng, writes to

IOCON take effect on the next TCY boundary.

12.32 Functional Exceptions

12.32.1 PO W ER RESET C OND ITIO NS

All regist ers associated with the PWM module are reset

to the states given in Table 12-4 upon a Power-on

Reset. On a d evic e reset, the PWM output pi ns are

tri-stated.

12.32.2 SLEEP MODE

The selec ted Fault input pin has the abi li ty to w ake the

CPU from Sleep mode. The PWM module should gen-

erate an asynchronous interrupt if any of the selected

Fault pins is driven low while in Sleep.

It is recommended that the user disable the PWM out-

puts prior to entering Sleep mode. If the PWM module

is controlling a power convers ion applic ation, the action

of putting the device into Sleep will cause any control

loops to be disabled, and most applications will likely

experience issues unless they are explicitly designed

to operate in an Open-Loop mode.

12.32.3 CPU IDLE MODE

The dsP IC30F202X m odule has a PTSIDL control bi t in

the PTCON register. This bit determines if the PWM

module continues to operate or stops when the device

enters Idle mode. Stopped Idle mode functions like

Sleep mo de, and F ault pins a re asynch ronously active.

•PTSIDL = 1 (Stop module when in Idle mode)

•PTSIDL = 0 (Don't stop module when in Idle

mode)

It is recommended that the user disable the PWM out-

puts prior to entering Idle mode. If the PWM module is

controlling a power-conversion application, the action

of putting the device into Idle will cause any control

loops to be disabled, and most applications will likely

experience issues unless they are explicitly designed

to operate in an Open-Loop mode.

12.33 Register Bit Alignment

Table 12-4 on p a ge 142 show s th e reg ist ers for the PS

PWM module. All time-based data for the module is

always bit-aligned with respect to time. For example: bit

3 in the period register, the duty cycle registers, the

dead-time regi sters, the trigger reg isters and the phase

registers always represents a value of 8.4 nsec,

assuming 30 MIPS operation. Unused portions of reg-

isters always read as zeros.

The use o f dat a al ignm ent makes it easier t o w rite so ft-

ware be cause it eli minates the need to shif t time value s

to fit into registers. It also eases the computation and

understanding of time allotment within a PWM cycle.

dsPIC30F1010/202X

12.34 APPLICATION EXAMPLES:

12.34.1 STANDARD PWM MODE

In standard PWM mode, the PWM output is typically

connected to a single transistor, which charges an

inductor, as shown in Figure 12-22. Buck and Boost

converters typically use standard PWM mode.

FIGURE 12 - 22: APPLIC ATI ONS OF

S T ANDA RD P WM MODE

12.34.2 APPLICATION OF COMPLEMENTARY

PWM MODE

Complementary mode PWM is often used in circuits

that use two tra nsistors in a bri dge co nfigura tio n where

transformers are not used, as shown in Figure 12-23.

If transformers are used, then some means must be

provided to ensure that no net DC currents flow

through the transformer to prevent core saturation.

FIGURE 12 -23: APPLICAT IONS OF

COMPLEMEN TARY PWM

MODE

Buck Converter

+VIN L1

PWM1H

VOUT

Boost Converter

+VIN

PWM1H

L1 VOUT

Period

PWM1H

OFF

Inductor charges during T

versus Period controls power flow

VOUT

+VIN

PWM1H

PWM1L

Synchronous Buck Converter

PWM1H

PWM1L

Series Resonant H al f B ri dge Converte r

VOUT

PWM1L

PWM1H

Dead Time Dead Time Dead Ti m e

Period

dsPIC30F1010/202X

12.34.3 APPLICATION OF PUSH-PULL PWM

MODE

Push-Pull PWM mode is typically used in transformer

coupled circuits to ensure that no net DC currents flow

through the transformer. Push-Pull mode ensures that

the same duty cycle PWM pulse is applied to the

transformer windings in alternate directions, as shown

in Figure 12-24.

FIGURE 12-24: APPLIC ATIONS OF PUSH-

PULL PWM MODE

12.34.4 APPLICATION OF MULTI-PHASE PWM

MODE

Multi-Ph ase PWM mode is often used in DC/DC con-

verters that must handle very fast load current tran-

sient s and fi t into tig ht sp aces. A mu lti-pha se con verter

is essentially a parallel array of buck converters that

are operated slightly out of phase of each other, as

shown in Figure 12-25. The multiple phases create an

effective switching speed equal to the sum of the indi-

vidual converters. If a single phase is operating with a

333 KHz PWM frequency, then the effective switching

frequency for the circuit is 1 MHz. This high switching

frequency greatly reduces output capacitor size

requirem ents and improv es load tran sie nt res pon se.

FIGURE 12 -25: APPLICAT IONS OF MUL TI-

PHASE PWM MODE

VOUT

Half Bridge Converter

+VIN

PWM1H

PWM1L

PWM1H

PWM1L

TON TOFF

Period Period

Dead Time Dead Time De ad Time

+VIN

PWM1H

PWM1L

Push-Pull Buck Converter

L1 VOUT

PWH1H

PWH1L

PWH1H

+VIN

T1 L1 VOUT

Full Bridge Converter

+VIN

PWM1H PWM2H PWM3H

L1 L2 L3

PWM1L PWM1L PWM1L

VOUT

Converter

Multiphase DC/DC

PWM1H

PWM1L

PWM2H

PWM2L

PWM3H

PWM3L

dsPIC30F1010/202X

12.34.5 APPLICATION OF VARIABLE PHASE PWM

MODE

Variable phase PWM is used in newer power conver-

sion topologies that are designed to reduce switching

losses. In standard PWM methods, any time a transis-

tor switches between the conducting state and the

nonconducting state (and vice versa), the transistor is

exposed to the full current and voltage condition for

the period of time it takes the transistor to turn on or

off. The power loss (V * I * Tsw * FPWM) becomes

appreciable at high frequencies. The Zero Voltage

Switching (ZVS) and Ze ro Current Switching (ZVC) cir-

cuit topologies attempt to use quasi-resonant tech-

niques to shift either the voltage or current waveforms

relative to each other. This action either makes the

voltage or the current zero at the time the transistor

turns on or off. If either the current or the voltage is

zero, then there is no switching loss generated.

In variable phase PWM modes, the duty cycle is fixed

at 50%, and the po w er f low i s co ntrolled b y v ary in g th e

phase relationship between the PWM channels, as

shown in Figure 12-26.

FIGURE 12 - 26: APPLIC ATI ON O F

VARIABLE PHASE PWM

MODE

12.34.6 APPLICATION OF CURRENT RESET PWM

MODE

In Current Res et PWM mode, the PWM frequenc y var-

ies with the load current. This mode is different than

most PWM modes because the user sets the maxi-

mum PWM period, but an external circuit measures

the inductor current. When the inductor current falls

below a specified value, the external current compara-

tor circuit generates a signal that resets the PWM time

base counter. The user specifies a PWM “on” time,

and then some time after the PWM signal becomes

inactive, the inductor current falls below a specified

value and the PWM counter is reset earlier than the

programmed PWM period. This mode is sometimes

called Constant On-Time.

This mode should not be confused with cycle-by-cycle

current-limiting PWM, where the PWM is asserted, an

external circu it gene rates a current Fault an d the PWM

signal is turned off before its programmed duty cycle

would normally turn it off. In this mode, shown in

Figure 12-27, the PWM frequency is fixed per the time

base period.

FIGURE 12 -27: APPLICAT ION OF

CURRENT RESET PWM

MODE

PWM1H

PWM1L

PWM2H

PWM2L

Variable Phase Shift

Full Bridge ZVT Converter

T1 V

OUT

PWM1H

PWM1H PWM1HPWM1H

PWM1H

OUT

External current comparator resets PWM counter

PWM cycle restarts early

This is a variable frequency PWM mode

PWM1H

TON

OFF

Actual Period

Programmed Period

dsPIC30F1010/202X

12.35 METHODS TO REDUCE EMI

The goal is to move the PWM edges around in time to

spread the EMI energy over a range of frequencies to

reduce the peak energy at any given frequency during

the EMI measurement process, which measures long

term averag es .

The EMI measurement process integrates the EMI

energy into 9 kHz wide frequency bins. Assuming that

the carrier (PWM) frequency is 150 kHz, a 6% dither

will yield a 9 kHz wide dither.

12.35.1 METHOD #1: PROGRAMMABLE FRC

DITHER

This method dithers all of the PWM outputs and the

system clock. The advantage of this method is that no

CPU resources are required. It is automatic once it is

setup . Th e us er c an pe r iod i ca ll y u p da t e th es e v al u es

to simulate a more random frequency pattern.

12.35.2 METHOD #2: SOFTWARE CONTROLLED

DITHER

This method uses software to dither individual PWM

channels by scaling the duty cycle and period. This

method co nsu me s CPU res ourc es :

Assume:

4 PWM channels updated @ 150 kHz rate:

600 kHz x (5 clocks (2 mul, 1 tblrdl, 1 mov))

= 3 MIPS additional work load

12.35.3 METHOD #3: SOFTWARE SCALING OF

TIME BASE PERIOD

This method used software to scale just the time base

period. Assuming that the dither rate is relatively slow

(about 250 Hz), the application control loop should be

able to compensate for the changes in PWM period

and adjust the duty cycle accordingly.

12.35.4 METHOD #4: FREQUENCY MODULATION

This method varies the frequency at which the PWM

cycle is varied (dithered). The frequency modulation

proc ess is si milar (m athem atical ly spea king) to Phase

Modulation when analyzed over a small time window.

The PWM module has the capability to phase modu-

late the PWM signals via the phase offset registers.

Phase mod ulatio n has the ad vant age tha t the softw are

is simpler and faster because multiple multiply opera-

tions (used for dithering frequency by scaling period

and duty cycles) are replaced with fewer additions or

simple updates of phase offset

values into the phase registers.

This method also has these advantages:

1. Multi-phase and variable phase PWM modes

could still be created.

2. The PWM generators can still use the common

time base, which simplifies determining when a

“quiet time” is available for measuring current.

This method has one disadvantage: the phase modu-

lation has to be at a relatively high update rate to

achieve usable frequency spreading.

12.35.5 INDEPENDENT PWM CHANNEL

DITHERING ISSUES:

Issues for mul t i-p ha se or v aria bl e ph as e de si gns us in g

independent output dithering must consider these

issues:

1. The phases are no longer phase aligned.

2. Control of current sharing among phases is

more difficult.

dsPIC30F1010/202X

12.36 EXTERNAL SYNCHRONIZATION

FEATURES

In large power conversion systems, it is often desir-

able to be able to synchronize multiple power control-

lers to ensure that “beat frequencies” are not

generated within the system, or as a means to ensure

“quiet” periods during which current and voltage mea-

surements can be made.

dsPIC30F202X devices (excluding 28-pin packages)

have input and/or output pins that provide the capabil-

ity to either synchronize the SMPS dsPIC DSC device

with an external device or have external devices syn-

chronized to the SMPS dsPIC DSC. These synchro-

nizing features are enabled via the SYNCIEN and

SYNCOEN bits in the PTCON control register in the

PWM module.

The SYNCPOL bit in the PTCON register selects

whether the rising edge or the falling edge of the

SYNCI signal is the active edge. The SYNCPOL bit in

the PTCON register also selects whether the SYNCO

output pulse is low active or high active.

The SYNCSRC<2:0> bits in the PTCON register

specify the source for the SYNCI signal.

If the SYNCI feature is enabled, the primary time base

counter is reset when an active SYNCI edge is

detected. If the SYNCO feature is enabled, an output

pulse is generated when the primary time base

counter rolls over at the end of a PWM cycle.

The recom mende d SYNCI puls e wid th shoul d be more

than 100 nsec. The expected SYNCO output pulse

width will be approximately 100 nsec.

When using the SYNCI feature, it is recommended

that t h e us er pr og r am t he p e r io d r e gi ste r wi t h a pe ri od

value th at i s s lig htl y lo nge r tha n th e ex pec te d pe riod of

the external synchronization input signal. This pro-

vides protection in case the SYNCI signal is not

received due to noise or external component failure.

With a reasonable period value programmed into the

PTPER register, the local power conversion process

should remain operational even if the global

synchronization signal is not received.

12.37 CPU LOAD STAG GERING

The SMPS dsPIC DSC has the ability to stagger the

individual trigger comparison operations. This feature

helps to level the processor’s workload to minimize

situations where the processor is overloaded.

Assume a situation where there are four PWM chan-

nels controlling four independent voltage outputs.

Assume further that each PWM generator is operating

at 1000 kHz (1 µsec period) and each control loop is

operating at 125 kHz (8 µsec).

The TRGDIV<2:0> bits in each TRGCONx register will

be set to ‘111’, which selects that every 8th trigger

comparison match will generate a trigger signal to the

ADC to capture data and begin a conversion process.

If the stagger-in-time feature did not exist, all of the

requests from all of the PWM trigger registers might

occur at the same time. If this “pile-up” were to hap-

pen, some da ta sample might becom e s t al e (o utdated)

by the time the data for all four channels can be

processed.

With the st agge r-in-tim e feature, the trigger si gnals are

spaced out over time (during succeeding PWM peri-

ods) so that all of the data is processed in an orderly

manner.

The ROLL counter is a counter connected to the pri-

mary time base counter. The ROLL counter is incre-

mented each time the primary time base counter

reaches terminal count (period rollover).

The stagger-in-time feature is controlled by the

TRGSTRT<5:0> bits in the TRGCONx registers. The

TRGSTRT<5:0> bits specify the count value of the

ROLL counter that must be matched before an individ-

ual trigger comparison module in each of the PWM

generators can begin to count the trigger comparison

events as specified by the TRGDIV<2:0> bits in the

PWMCONx registers.

So, in our example with the four PWM generators, the

first PWM’s TRGSTRT<5:0> bits would be ‘000’, the

second PWM’s TRGSTRT bits would be set to ‘010’,

the third PWM’s TRGSTRT bits would be set to ‘100’

and the fourth PWM’s TRGSTRT bits would be set to

‘110’. Therefore, over a total of eight PWM cycles, the

four separate control loops could be run each with

their own 2-µsec time period.

12.38 EXTERNAL TRIGGER BLANKING

Using the LEB<9:3> bits in the LEBCONx registers,

the PWM module has the capability to blank (ignore)

the external current and Fault inputs for a period of 0

to 1024 nsec. This feature is useful if power transistor

turn-on induced transients make current sensing

diffi cult at the start of a PWM cycle.

dsPIC30F1010/202X

TABLE 12-4: POWER SUPPLY PWM REGISTER MAP

File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PTCON 0400 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> 0000

PTPER 0402 PTPER<15:3> — — —FFF0

MDC 0404 MDC<15:0> 0000

SEVTCMP 0406 SEVTCMP<15:3> — — —0000

PWMCON1 0408 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> — — — — XPRES IUE 0000

IOCON1 040A PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> — OSYNC 0000

FCLCON1 040C — — — CLSRC<3:0> CLPOL CLMOD FLTSRC<3:0> FLTPOL FLTMOD<1:0> 0000

PDC1 040E PDC1<15:0> 0000

PHASE1 0410 PHASE1<15:2> ——0000

DTR1 0412 —— DTR1<13:2> ——0000

ALTDTR1 0414 —— ALTDTR1<13:2> ——0000

TRIG1 0416 TRIG<15:3> — — —0000

TRGCON1 0418 TRGDIV<2:0> —- —- —- —- —- —- —- TRGSTRT<5:0> 0000

LEBCON1 041A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3> — — —0000

PWMCON2 041C FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> — — — — XPRES IUE 0000

IOCON2 041E PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> — OSYNC 0000

FCLCON2 0420 — — — CLSRC<3:0> CLPOL CLMOD FLTSRC<3:0> FLTPOL FLTMOD<1:0> 0000

PDC2 0422 PDC2<15:0> 0000

PHASE2 0424 PHASE2<15:2> ——0000

DTR2 0426 —— DTR2<13:2> ——0000

ALTDTR2 0428 —— ALTDTR2<13:2> ——0000

TRIG2 042A TRIG<15:3> — — —0000

TRGCON2 042C TRGDIV<2:0> —- —- —- —- —- —- —- TRGSTRT<5:0> 0000

LEBCON2 042E PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3> — — —0000

PWMCON3 0430 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> — — — — XPRES IUE 0000

IOCON3 0432 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> — OSYNC 0000

FCLCON3 0434 — — — CLSRC<3:0> CLPOL CLMOD FLTSRC<3:0> FLTPOL FLTMOD<1:0> 0000

PDC3 0436 PDC3<15:0> 0000

PHASE3 0438 PHASE3<15:2> ——0000

DTR3 043A —— DTR3<13:2> ——0000

ALTDTR3 043C —— ALTDTR3<13:2> ——0000

TRIG3 043E TRIG<15:3> — — —0000

TRGCON3 0440 TRGDIV<2:0> —- —- —- —- —- —- —- TRGSTRT<5:0> 0000

LEBCON3 0442 PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3> — — —0000

PWMCON4 0444 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> — — — — XPRES IUE 0000

IOCON4 0446 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> — OSYNC 0000

dsPIC30F1010/202X

FCLCON4 0448 — — — CLSRC<3:0> CLPOL CLMODE FLTSRC<3:0> FLTPOL FLTMOD<1:0> 0000

PDC4 044A PDC4<15:0> 0000

PHASE4 044C PHASE4<15:2> ——0000

DTR4 044E — — DTR4<13:2> ——0000

ALTDTR4 0450 —— ALTDTR4<13:2> ——0000

TRIG4 0452 TRIG<15:3> — — —0000

TRGCON4 0454 TRGDIV<2:0> —- —- —- —- —- —- —- TRGSTRT<5:0> 0000

LEBCON4 0456 PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3> — — —0000

Reserved 0458-

47F — — — — — — — — — — — — — — — —0000

TABLE 12-4: POWER SUPPLY PWM REGISTER MAP (CONTINUED)

File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

dsPIC30F1010/202X

NOTES:

dsPIC30F1010/202X

13.0 SERIAL PER IPHERAL

INTERFACE (SPI)

The Serial Peripheral Interface (SPI) module is a syn-

chronous serial interface useful for communicating with

other peripheral or microcontroller devices. These

peripheral devices may be serial EEPROMs, shift regis-

ters, display drivers, ADC, etc. The SPI module is

comp ati bl e wit h SP I a nd SIO P fro m Moto rol a®.

The SPI module consists of a 16-bit shift register,

SPIxSR (w h ere x = 1 or 2), us ed f or sh if tin g da ta in a nd

out, and a buffer register , SPIxBUF. T wo control registers,

SPIxCON1 and SPIxCON2, configure the module. The

SPIxSR register is not accessible by user software. A sta-

tus register, SPIxSTAT, indicates various status

conditions.

The ser ial in terf ace con sists of 4 pins : SDIx (seria l data

input) , SDO x (s eri al d at a ou tp ut) , SCKx (s h ift cl oc k in pu t

or o utp ut ), and SSx (active-low s l av e se le ct ).

In Master mode operation, SCK is a clock output but in

Slave mode, it is a clock input.

A series of eight (8) or sixteen (16) clock pulses shift out

bits from the SPIxSR to SDOx pin and simultaneously

shift in data from SDIx pin. An interrupt is generated

when the transfer is complete and the corresponding

interrupt flag bit (SPI1IF or SPI2IF) is set. This interrupt

can be disabled through an interrupt enable bit (SPI1IE

or SPI2I E ).

The re ceive op eration is doub le-buff ered. Wh en a com-

plete byte is received, it is transferred from SPIxSR to

SPIxBUF.

If the receive buffer is full when new data is being trans-

ferred from SPIxSR to SPIxBUF, the module sets the

SPIROV bit (SPIxSTAT<6>) to indicate an overflow con-

dition. The transfer of the data from SPIxSR to SPIxBUF

is not co mpleted, and the ne w data is l ost. The mo dule

does not respond to transitions on the SCKx pin while

SPIROV (SPIxSTAT<6>) is ‘1’, effectively disabling the

module un til SPIxBUF is read by u se r s o ftwa re.

Transmit writes are also double-buffered. The user soft-

ware wri tes to SPIxBUF. When the master or slave trans-

fer is completed, the contents of the shift register

(SPIxSR) are moved to the receive buffer . If any transmit

data has been written to the buffer register, the contents

of the transmit buffer are moved to SPIxSR. The received

data is thus placed in SPIxBUF and the transmit data in

SPIxS R is r ea dy fo r t he ne x t tr an sfer.

To set up the SPI module for the Master mode of

operation:

1. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSn

b) Set the SPIxIE bit in the respective IECn

c) Write the SPIxIP bits in the respective IPCn

2. Write the desired settings to the SPIxCON1

3. Clear the SPIROV bit (SPIxSTAT<6>).

4. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

5. Write the data to be transmitted to the SPIxBUF

soon as d at a i s writte n to the SPIx BUF re gis te r.

To set up the SPI module for the Slave mode of operation:

1. Clear the SPIxBUF register.

2. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSn

b) Set the SPIxIE bit in the respective IECn

c) Write the SPIxIP bits in the respective IPCn

3. Write the desire d settin gs to the SPIxCON 1 and

SPIxCON2 registers with MSTEN

(SPIxCON1<5>) = 0.

4. Clear the SMP bit (SPIxCON1<9>).

5. If the CKE (SPIxCON1<8>) bit is set, then the

SSEN bit (SPIxCON1<7>) must be set to enable

the SSx pin.

6. Clear the SPIROV bit (SPIxSTAT<6>).

7. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

The SPI m odule genera tes an interru pt ind icatin g com-

pletion of a by te or word transfe r, as well as a sep arate

interrupt for all SPI error conditions.

Note: This data sheet summarizes the features

of this group of dsPIC30F1010/202X devices. It is not

inte nd ed t o be a c om pr ehe n si ve re f e re n ce so urc e. To

comple ment th e inform ation in this dat a sheet , refer to

the “dsPI C30F Family Refere nce Manual” (DS70046).

Note: The dsPIC30F101/202X family has only

one SPI. All references to x = 2 are

intended for software compatibility with

other dsPIC DSC devices.

Note: Both the transmit buffer (SPIxTXB) and

the receive buffer (SPIxRXB) are mapped

to the same register address, SPIxBUF.

Do not perform read-modify-write opera-

tions (such as bit-oriented instructions) on

the SPIxBUF register.

dsPIC30F1010/202X

FIGURE 13-1: SPI MODULE BLOCK DIAGRAM

Note: The ds PIC 30F 101 0/2 020 device s do not contain th e SS1 pin. There fore , th e Slav e Select an d Frame Sync

features cannot be used on these devices. These features are available on the dsPIC30F2023.

Inte rn al Da ta B u s

SDIx

SDOx

SSx

SCKx

SPIxSR

bit 0

Shift Control

Edge

Select

FCY

Primary

1:1/4/16/64

Enable

Prescaler

Sync

SPIxBUF

Control

Transfer

Write SPIxBUF

Read SPIxBUF

SPIxCON1<1:0>

SPIxCON1<4:2>

Master Clock

Clock

Control

Secondary

Prescaler

1:1 to 1:8

SPIxRXB SPIxTXB

dsPIC30F1010/202X

FIGURE 13-2: SPI MASTER/SLAVE CONNECTION

FIGURE 13-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM

FIGURE 13-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM

Serial Receive Buffer

(SPIxRXB)

LSb

MSb

SDIx

SDOx

PROCESSOR 2 (SPI Slave)

SCKx

SSx(1)

Serial Transmit Buffer

(SPIxTXB)

Serial Receive Buffer

(SPIxRXB)

Shift Regis ter

(SPIxSR)

MSb LSb

SDOx

SDIx

PROCESSOR 1 (SP I Master)

Serial Clock

(SSEN (SPI xCON 1<7> ) = 1 and MSTEN (SPIxCON1<5>) = 0)

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must wr ite tra nsmi t data to/r ead rec eive d dat a from SP IxBUF. The SPIx TXB an d SPIxR XB reg ister s are m emory

mapped to SPIxBUF.

SCKx

Serial Transmit Buffer

(SPIxTXB)

(MSTEN (SPIxCON1<5>) = 1)

SPI Buffer

(SPIxBUF)(2)

SPI Buffer

(SPIxBUF)(2)

Shift Regis ter

(SPIxSR)

SDOx

SDIx

dsPIC33F

Serial Clock

SSx

SCKx

Frame Sync

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

(SPI Slave, Frame S lav e)

SDOx

SDIx

dsPIC33F

Serial Clock

SSx

SCKx

Frame Sync

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

(SPI Mas ter, Frame Sl ave)

dsPIC30F1010/202X

FIGURE 13-5: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM

FIGURE 13-6: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM

EQUATION 13-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED

TABLE 13-1: SAMPLE SCKx FREQUENCIES

FCY = 40 MHz Secondary Prescaler Settings

1:1 2:1 4:1 6:1 8:1

Primary Prescaler Settings 1:1 Invalid Invalid 7500 5000 3750

4:1 7500 3750 1875 1250 937.5

16:1 1875 937.5 469 312.5 234.4

64:1 469 234.4 117 78.1 58.6

FCY = 5 MHz

Primary Prescaler Settings 1:1 5000 2500 1250 833 625

4:1 1250 625 313 208 156

16:1 313 156 78 52 39

64:17839201310

Note: SCKx frequencies shown in kHz.

SDOx

SDIx

dsPIC33F

Serial Clock

SSx

SCKx

Frame Sync

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

(SPI Slave, Frame Slav e)

SDOx

SDIx

dsPIC33F

Serial Clock

SSx

SCKx

Frame S ync

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

(SPI Master, Frame Slave)

Primary Prescaler * Secondary Prescaler

FCY

FSCK =

dsPIC30F1010/202X

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

SPIEN — SPISIDL — — — — —

bit 15 bit 8

U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0

— SPIROV — — — — SPITBF SPIRBF

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 SPIEN: SPIx Enable bit

1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

0 = Disables module

bit 14 Unimplemented: Read as ‘0’

bit 13 SPISIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 SPIROV: Receive Overflow Flag bit

1 = A new byte/word is completely received and discarded. The user software has not read the

previous data in the SPIxBUF register.

0 = No overflow has occurred

bit 5-2 Unimplemented: Read as ‘0’

bit 1 SPITBF: SPIx Transmit Buffer Full Status bit

1 = Transmit not yet started, SPIxTXB is full

0 = Transmit started, SPIxTXB is empty

Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.

Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.

bit 0 SPIRBF: SPIx Receive Buffer Full Status bit

1 = Receive complete, SPIxRXB is full

0 = Receive is not complete, SPIxRXB is empty

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.

Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.

dsPIC30F1010/202X

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — DISSCK DISSDO MODE16 SMP CKE(1)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only)

1 = Internal SPI clock is disabled, pin functions as I/O

0 = Internal SPI clock is enabled

bit 11 DISSDO: Disable SDOx pin bit

1 = SDOx pin is not used by module; pin functions as I/O

0 = SDOx pin is controlled by the module

bit 10 MODE16: Wo rd/By te Commu nic ati on Sele ct bit

1 = Communication is word-wide (16 bits)

0 = Communication is byte-wide (8 bits)

bit 9 SMP: SPIx Data Input Sample Phase bit

Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

Slave mode:

SMP must be cleared when SPIx is used in Slave mode.

bit 8 CKE: SPIx Clock Edge Select bit(1)

1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)

0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

bit 7 SSEN: Slave Select Enable bit (Slave mode)

1 = SSx pin used for Slave mode

0 = SSx pin not used by module. Pin cont rolled by port func tion.

bit 6 CKP: Clock Polarity Select bit

1 = Idle stat e for clock is a high level; active state is a lo w leve l

0 = Idle state for clock is a low level; active state is a high level

bit 5 MSTEN: Master Mode Enable bit

1 = Master mode

0 = Slave mode

bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)

111 = Secondary prescale 1:1

110 = Secondary prescale 2:1

...

000 = Secondary prescale 8:1

bit 1-0 PPRE<1:0>: Primary Presca le bits (Master mode)

11 = Primary prescale 1:1

10 = Primary prescale 4:1

01 = Primary prescale 16:1

00 = Primary prescale 64:1

Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed

SPI modes (FRMEN = 1).

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0

FRMEN SPIFSD FRMPOL — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — FRMDLY —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 FRMEN: Framed SPIx Support bit

1 = Framed SPIx support enabled (SSx pin us ed as frame sync pulse input/output)

0 = Framed SPIx support disabled

bit 14 SPIFSD: Frame Sync Pulse Direction Control bit

1 = Frame sync pulse input (slave)

0 = Frame sync pulse output (master)

bit 13 FRMPOL: Frame Sync Pulse Polarity bit

1 = Frame sync pulse is active-high

0 = Frame sync pulse is active-low

bit 12-2 Unimplemented: Read as ‘0’

bit 1 FRMDLY: Frame Sync Pulse Edge Select bit

1 = Frame sync pulse coincides with first bit clock

0 = Frame sync pulse precedes first bit clock

bit 0 Unimplemented: This bit must not be set to ‘1’ by the user applic ation.

dsPIC30F1010/202X

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

TABLE 13-2: SPI1 REGISTER MAP

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SPI1STAT 0240 SPIEN — SPISIDL — — — — — —SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000

SPI1CON 0242 — — —

DISSCK

DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 0000 0000 0000

SPI1CON2

0244

FRMEN

SPIFSD FRMPOL — — — — — — — — — — —

FRMDLY

—0000 0000 0000 0000

SPI1BUF 0246 Transmit and Receive Buffer 0000 0000 0000 0000

Legend: u = uninitialized bit

dsPIC30F1010/202X

14.0 I2C™ MODULE

The Inter-Integrated Circuit (I2C) module provides

complete hardware support for both Slave and Multi-

Master modes of the I2C serial communication

standard, with a 16-bit interface.

This module offers the following key features:

•I

2C interface supporting both Master and Slave

operation.

•I

2C Slave mode supports 7 and 10-bit address

•I

2C Master mode su pports 7 and 10-bit address

•I

2C port allows bidirectional transfers between

master and slav es.

• Serial clock synchronization for I2C port can be

used as a ha ndshake mechanis m to suspen d and

resume serial transfer (SCLREL control).

•I

2C supports Multi-Master operation; detects bus

collision and will arbitrate accordingly.

14.1 Operating Function Description

The hardw are fully im plements all the maste r and slave

functions of the I2C Standard and Fast mode

specifications, as well as 7 and 10-bit addressing.

Thus, the I2C module can operate either as a slave or

a master on an I2C bus.

14.1.1 VARIOUS I2C MODES

The following types of I2C operation are supported:

•I

2C Slave operation with 7 or 10-bit address

•I

2C Master operation with 7 or 10-bit address

See the I2C programmer’s model in Figure 14-1.

14.1.2 PIN CONFIGURATION IN I2C MODE

I2C has a 2- pin i nterfac e; pin SCL is clock and pin SD A

is data.

FIGURE 14 - 1: PROGRAMMER’S MO D EL

14.1.3 I2C REGISTERS

I2CCON and I2CSTAT are Control and Status regis-

ters, respectivel y . The I2CCON register is r eadable and

writable. The lower 6 bits of I2CSTAT are read-only.

The remaining bits of the I2CSTAT are read/write.

I2CRSR is the shift register used for shifting data,

whereas I2CRCV is the buffer register to which data

bytes are written, or from which data bytes are read.

I2CRCV is the receive buffer, as shown in Figure 16-1.

I2CTRN is the transmit register to which bytes are writ-

ten during a transmit operation, as s hown in Figure 16-2.

The I2CADD regis ter hol ds the s lave a ddress. A status

bit, ADD10, indicates 10-bit Address mode. The

I2CBRG acts as the Baud Rate Generator (BRG)

reload value.

In receive operations, I2CRSR and I2CRCV together

form a double-buffered receiver. When I2CRSR

receives a complete byte, it is transferred to I2CRCV

and an interrupt pulse is generated. During

transmission, the I2CTRN is not double-buffered.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

bit 7 bit 0 I2CRCV (8 bits)

bit 7 bit 0 I2CTRN (8 bits)

bit 8 bit 0 I2CBRG (9 bits)

bit 15 bit 0 I2CCON (16 bits)

bit 15 bit 0 I2CSTAT (16 bits)

bit 9 bit 0 I2CADD (10 bits)

Note: Following a Restart condition in 10-bit

mode, the user only needs to match the

first 7-bit addre ss.

dsPIC30F1010/202X

FIGURE 14-2: I2C™ BLOCK DIAGRAM

I2CRSR

I2CRCV

Internal

Data Bus

SCL

SDA

Shift

Mat ch Det ect

I2CADD

Start and

St op bit Detect

Clock

Addr_Match

Clock

Stretching

I2CTRN LSB

Shift

Clock

Write

Read

BRG Down I2CBRG

Reload

Control

FCY

Start, Restart,

Stop bit Generate

Write

Read

Acknowledge

Generation

Collision

Detect

Write

Read

Write

Read

I2CCON

Write

Read

I2CSTAT

Control Logic

Read

LSB

Counter

dsPIC30F1010/202X

14.2 I2C Module Addresses

The I2CADD register contains the Slave mode

addresses. The register is a 10-bit register.

If the A10M bit (I2CCON<10>) is ‘0’, the address is

inter prete d by the mo dul e as a 7 - bit add ress . When an

address is received, it is compared to the 7 Least

Significant bits of the I2CADD register.

If the A10M bit is ‘1’, the address is assumed to be a

10-bit address. When an address is received, it will be

compared with the binary value ‘1 1 1 1 0 A9 A8’

(where A9, A8 are two Most Significant bits of

I2CADD). If that value matches, the next address will

be compared with the Least Significant 8 bits of

I2CAD D, as speci fied in the 1 0-bit addres sing proto col.

14.3 I2C 7-bit Slave Mode Operation

Once enabled (I2CEN = 1), the slave module will wait

for a S t art bit to occur (i.e., the I2C module is ‘I dle’). Fol-

lowin g t he det ection of a Start bit , 8 bit s are s hifted into

I2CRSR and the address is compared against

I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>

are compared against I2CRSR<7:1> and I2CRSR<0>

is the R_W bit. All incoming bits are sampled on the

rising edge of SCL.

If an address match occurs, an acknowledgement will

be sent, and the slave event interrupt flag (SI2CIF) is

set on the falling edge of the ninth (ACK) bit. The

address match does not affect the contents of the

I2CRCV buffer or the RBF bit.

14.3.1 SLAVE TRANSMISSION

If the R_W bit received is a ‘1’, then the serial port will

go into Transmi t mode. It wil l send AC K on the nint h bit

and then hold SCL to ‘0’ un til the CPU responds b y writ-

ing to I2C TRN. SCL is rele ased by settin g the SCLREL

bit, and 8 bits of data are shifted out. Data bits are

shifted out on the fa lling edge of SCL, s uch that SDA i s

valid during SCL high (see timing diagram). The inter-

rupt pulse is sent on the falling edge of the ninth clock

pulse, regardless of the status of the ACK received

from the master.

14.3.2 SLAVE RECEPTION

If the R_W bit received is a ‘0’ during an address

match, then Receive mode is initiated. Incoming bits

are sampled on the rising edge of SCL. After 8 bits are

received, if I2CRCV is not full or I2COV is not set,

I2CRSR is transferred to I2CRCV. ACK is sent on the

ninth clock.

If the RBF flag is set, indicating that I2CRCV is still

holding data from a pre vious operati on (RBF = 1), the n

ACK is not sent; however, the interrupt pulse is gener-

ated. In the case of an overflow, the contents of the

I2CRSR are not loaded into the I2CRCV.

14.4 I2C 10-bit Slave Mode Operation

In 10-bit mode, the basic receive and transmit opera-

tions are the same as in the 7-bit mode. However, the

criteria for address match is more complex.

The I2C specification dictates that a slave must be

address ed for a write ope ration, with tw o address byte s

following a Start bit.

The A10M bit is a control bit that signifies that the

address in I2CADD is a 10-bit address rather than a

7-bit address. The address detection protocol for the

first byte of a message address is identical for 7-bit

and 10-bit messages, but the bits being compared are

different.

I2CADD holds the entire 10-bit address. Upon receiv-

ing an address following a Start bit, I2CRSR <7:3> is

compared against a literal ‘11110’ (the default 10-bit

address) and I2CRSR<2:1> are compared against

I2CADD<9:8>. If a match occurs and if R_W = 0, the

interrupt pu lse is sent. Th e ADD10 bit will be cleare d to

indicate a partial address match. If a match fails or

R_W = 1, the ADD10 bit is cleared and the module

returns to the Idle state.

The low byte of the address is then received and com-

pared with I2CADD<7:0>. If an address match occurs,

the interrupt pulse is generated and the ADD10 bit is

set, indicating a complete 10-bit address match. If an

address match did not occur, the ADD10 bit is cleared

and the module returns to the Idle state.

14.4.1 10-BIT MODE SLAVE

TRANSMISSION

Once a slave is addressed in this fashion, with the full

10-bit address (we will refer to this state as

“PRIOR_ADDR_MA TCH”), the master can begin send-

ing data bytes for a slave reception operation.

14.4.2 10-BIT MODE SLAVE RECEPTION

Once ad dresse d, the ma ster can gen erate a Repe ated

Start, reset the high byte of the address and set the

R_W bit without generating a Stop bit, thus initiating a

slave trans mit opera tion.

Note: The I2CRCV will be loaded if the I2COV

bit = 1 and the RBF flag = 0. In this case,

a read of the I2CRCV was performed, but

the user did not clear the state of the

I2COV bit before the next receive

occurred. The acknowledgement is not

sent (ACK = 1) and the I2CRCV is

updated.

dsPIC30F1010/202X

14.5 Automatic Clock Stretch

In the Slave mo des, the module ca n synchroniz e buf fer

reads and write to the master device by clock

stretching.

14.5.1 TRANSMIT CLOCK STRETCHING

Both 10-bit and 7-bit Transmit modes implement clock

stretching by asserting the SCLREL bit after the falling

edge of the ninth clock if the TBF bit is cleared,

indicating the buffer is empty.

In Slave Transmit modes, clock stretching is always

performed, irrespective of the STREN bit.

Clock synchronization takes place following the ninth

clock of the transmit sequence. If the device samples

an ACK on the fa lling edge o f the ni nth cl ock, a nd if th e

TBF bit is still clear, then the SCLREL bit is automati-

cally cleared. The SCLREL being cleared to ‘0’ will

assert the SCL line low. The user’s ISR must set the

SCLREL bit before transmission is allowed to con-

tinue. By ho ldi ng the SC L l ine lo w, the user has tim e to

service the ISR and load the contents of the I2CTRN

before the master device can initiate another transmit

sequence.

14.5.2 RECEIVE CLOCK STRETCHING

The STREN bit in the I2CCON register can be used to

enable clock stretching in Slave Receive mode. When

the STREN bit is set, the SCL pin will be held low at

the end of each data receive sequence.

14.5.3 CLOCK STRETCHING DURING

7-BIT AD DRES SIN G (S TR EN = 1)

When the STREN bit is set in Slave Receive mode,

the SCL line is held low when the buffer register is full.

The method for stretching the SCL output is the same

for both 7 and 10-bit Addressing modes.

Clock stretching takes place following the ninth clock of

the receive sequence. On the falling edge of the ninth

clock at the end of the ACK sequence, if the RBF bit is

set, the SCLREL bit is automatically cleared, forcing the

SCL output to be held low. The user’s ISR must set the

SCLREL bit before reception is allowed to continue. By

holding the SCL line low, the user has time to service

the ISR and read the contents of the I2CRCV before the

master device can initiate another receive sequence.

This will prevent buffer overruns from occurring.

14.5.4 CLOCK STRETCHING DURING

10-BIT ADDRESSING (STREN = 1)

Clock stretching takes place automatically during the

addressing sequence. Because this module has a

the protocol to wait for the address to be updated.

After the address phase is complete, clock stretching

will occur on each data receive or transmit sequence

as was described earlier.

14.6 Software Controlled Clock

Stretching (STREN = 1)

When the STREN bit is ‘1’, the SCLREL bit may be

cleared by software to allow software to control the

clock stretching. The logic will synchronize writes to

the SCLREL bit with the SCL clock. Clearing the

SCLREL bit will not assert the SCL output until the

module detects a falling edge on the SCL output and

SCL is sampled low. If the SCLREL bit is cleared by

the user while the SCL line has been sampled low, the

SCL output will be asserted (held low). The SCL out-

put will remain low until the SCLREL bit is set, and all

other devices on the I2C bus have deasserted SCL.

This ensures that a write to the SCLREL bit will not

violate the minimum high time requirement for SCL.

If the STREN bit is ‘0’, a software write to the SCLREL

bit will be disregarded and have no effect on the

SCLREL bit.

14.7 Interrupts

The I2C module generates two interrupt flags, MI2CIF

(I2C Master In terrupt Flag) and SI2 CIF (I2C Slave Inter-

rupt Flag). The MI2CIF interrupt flag is activated on

completion of a master message event. The SI2CIF

interrupt flag is activated on detection of a message

directed to the slave.

Note 1: If the user loads the contents of I2CTRN,

setting the TBF bit before the fallin g edge

of the n int h c lo ck , th e SC LREL bit w il l n ot

be cleared and clock stretching will not

occur.

2: The SCLREL bit can be set in software,

regardless of the state of the TBF bit.

Note 1: If the user reads the contents of the

I2CRCV, clearing the RBF bit before the

falling edge of the ninth clock, the

SCLREL bit will not be cleared and clock

stretching will not occur.

2: The SCLREL bit can be set in software,

regardles s of the state of the RBF bit. The

user should be car eful to clear the RBF bit

in the ISR before the next receive

sequenc e in order to preven t an Overflow

condition.

dsPIC30F1010/202X

14.8 Slope Control

The I2C standard requires slope control on the SDA

and SCL signals for Fast mode (400 kHz). The control

bit, DISSLW , enab les the user to disa ble slew rate co n-

trol, if desired. It is necessary to disable the slew rate

control for 1 MHz mode.

14.9 IPMI Support

The control bit IPMIEN enables the module to support

Intelligent Peripheral Management Interface (IPMI).

When this bit i s s et, t he m od ule ac ce pts an d ac t s upo n

all addres ses .

14.10 General Call Address Support

The general call address can address all devices.

When this address is used, all devices should,

in theory, respond with an acknowledgement.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all ‘0’s with R_W = 0.

The general call address is recognized when the Gen-

eral Call Enable (GCEN) bit is set (I2CCON<7> = 1).

Following a Start bit detection, 8 bits are shifted into

I2CRSR and the address is compared with I2CADD,

and is also compared with the general call address

which is fixed in hardware.

If a gen eral cal l addre ss matc h occurs, the I2CRS R is

transferred to the I2CRCV after the eighth clock, the

RBF flag is set, and, on the falling edge of the ninth bit

(ACK bit), the master event interrupt flag (MI2CIF) is

set.

When the i nte rrupt is serviced, the source for the int er-

rupt can be checked by reading the contents of the

I2CRCV to determine if the address was device

specific, or a general call address.

14.11 I2C Master Support

As a Master device, six operations are supported.

• Assert a Start condition on SDA and SCL.

• Assert a Restart condition on SDA and SCL.

• Write to the I2CTRN register initiating

transmission of data/address.

• Generate a Stop condition on SDA and SCL.

• Configure the I2C port to receive data.

• Generate an ACK condition at the end of a

received byte of data.

14.12 I2C Master Operation

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the begi nning of the next seria l transfer, the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the data direction bit. In

this ca se, the da ta direc tion bit (R_ W) is logi c ‘0’. Serial

data is transmitted 8 bits at a time. After each byte is

transmitted , an ACK bit i s received . S t art and Stop con-

ditions are output to indicat e the beginn ing and the en d

of a serial transfer.

In Master Rec eive mode, the firs t byte transmitte d con-

tains the slave address of the transmitting device (7

bits) and the data direction bit. In this case, the data

directio n bi t ( R_W) is log ic 1. Thus, the first byte trans-

mitted is a 7-b it slave a ddress, followed b y a ‘ 1’ to ind i-

cate receive bit. Serial data is received via SDA, while

SCL outputs the serial clock. Serial data is received 8

bits at a tim e. After e ach by te is rece ived, a n ACK bit is

transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

14.12.1 I2C MASTER TRANSMISSION

T ransmission of a data byte, a 7-bit address, or the sec-

ond half of a 10-bit address is accomplished by simply

writing a value to I2CTRN register. The user should

only write to I2CTRN when the module is in a WAIT

state . This actio n will set th e Buff er Full Fl ag (TBF ) and

allow the Baud Rate Generator to begin counting and

start the next transmission. Each bit of address/data

will be shifted out onto the SDA pin after the falling

edge of SCL is asserted. The Transmit Status Flag,

TRSTAT (I2CSTAT<14>), indicates that a master

transmit is in progress.

14.12.2 I2C MASTER RECEPTION

Master mode recepti on is enabl ed by progra mmin g the

receive enable (RCEN) bit (I2CCON<3>). The I2C

module must be Idle before the RCEN bit is set, other-

wise the RCEN bit will be disregarded. The Baud Rate

Generator begins counting, and, on each rollover, the

state of the SCL pin toggles, and dat a is shifted in to the

I2CRSR on the rising edge of each clock.

dsPIC30F1010/202X

14.12.3 BAUD RATE GENERATOR

In I2C Master mode, the reload value for the BRG is

located in the I2CBRG register. When the BRG is

loaded w ith th is v alu e, the BRG c ou nt s d own to ‘0’ and

stops until another reload has taken place. If clock

arbitration is taking place, for instance, the BRG is

reloaded when the SCL pin is sampled high.

As per the I2C standard, FSCK may be 100 kHz or

400 kHz. However, the user can specify any baud rate

up to 1 MHz. I2CBRG values of ‘ 0’ or ‘1’ are illegal.

EQUATION 14-1: I2CBRG VALUE

14.12.4 CLOCK ARBITRATION

Clock arbitration oc curs when the m aster deasse rts the

SCL pi n (SCL al lowe d to fl oat hi gh) duri ng an y rece ive,

transmi t or Restar t/S top conditio n. When the SCL pi n is

allowed to float high, the Baud Rate Generator is

suspended from counting until the SCL pin is actually

sampled high. When the SCL pin is sampled high, the

Baud Rate Generator is reloaded with the contents of

I2CBRG and begins counting. This ensures that the

SCL high time w il l al ways be a t lea st o ne BR G roll over

count in the event that the clock is held low by an

external device.

14.12.5 MULTI-MASTER COMMUNICATION,

BUS CO LLISION AND BUS

ARBITRATION

Multi-Master operation support is achieved by bus

arbitration. When the master outputs address/data bits

onto the SDA pin, arbitration takes place when the

master outputs a ‘1’ on SDA, by letting SDA float high

whil e another mast er asserts a ‘0’. When the SCL pin

floats high, data should be stable. If the expected data

on SDA is a ‘1’ and the data sampled on the SDA

pin = 0, then a bus collision has taken place. The

master will set the MI2CIF pulse and reset the master

portion of the I2C port to its Idle state.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the TBF flag is

cleared, the SDA and SCL lines are deasserted, and a

value can now be written to I2CTRN. When the user

services the I2C master event Interrupt Service

Routine, if the I2C bus is free (i.e., the P bit is set) the

user can resume communication by asserting a Start

condition.

If a Start, Restart, Stop or Acknowledge condition was

in progres s when the bus collisi on o cc urre d, th e c ond i-

tion is aborte d, the SDA an d SCL li nes a re deas serted,

and the respective control bits in the I2CCON register

are cleared to ‘0’. When th e u s er se r vi c es the bu s c ol -

lision Interrupt Service Routine, and if the I2C bus is

free, the user can resume co mm uni ca tion by asse rtin g

a Start condition .

The Master will continue to monitor the SDA and SCL

pins and, if a Stop condition occurs, the MI2CIF bit will

be set.

A write to the I2CTR N will start the trans mission of dat a

at the fi rst data bit, regardless of where the transmitter

left off when bus collision occurred.

In a Multi-Mas ter environment, th e i nte rrupt generation

on the d etecti on of Start a nd Stop co nditio ns al lows th e

determination of when the bus is free. Control of the I2C

bus can be taken when the P bit is set in the I2CSTAT

cleared.

14.13 I2C Module Operation During CPU

Sleep and Idle Modes

14.13.1 I2C OPERATION DURING CPU

SLEE P MOD E

When the device enters Sleep mode, all clock sources

to the module are shutdown and stay at logic ‘0’. If

Sleep occurs in the middle of a transmission, and the

state machine is partially into a transmission as the

clocks s top, the n the tra nsmiss ion is ab orted. Si milarl y,

if Sleep occurs in the middle of a reception, then the

reception is aborted.

14.13.2 I2C OPERATION DURING CPU IDLE

MODE

For the I2C, the I2CSIDL bit selects if the module will

stop on Idle or continue on Idle. If I2CSIDL = 0, the

module will continue operation on assertion of the Idle

mode. If I2CSIDL = 1, the module will stop on Idle.

I2CBRG Fcy

Fscl

-----------Fcy

1 111 111,,

---------------------------

–

⎝⎠

⎛⎞

1–=

dsPIC30F1010/202X

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

TABLE 14-1: I2C™ REGIS TER MAP

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

I2CRCV 0200 — — — — — — — — Receive R egist er 0000 0000 0000 0000

I2CTRN 0202 — — — — — — — — Transmit R egist er 0000 0000 1111 1111

I2CBRG 0204 — — — — — — — Baud Rate Generator 0000 0000 0000 0000

I2CCON 0206 I2CEN —I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000

I2CSTAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000

I2CADD 020A — — — — — — Address Register 0000 0000 0000 0000

dsPIC30F1010/202X

NOTES:

dsPIC30F1010/202X

15.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART) MODULE

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules

available in the dsPIC30F1010/202X device family.

The UART is a full-duplex asynchronous system that

can communicate with peripheral devices, such as

personal computers, LIN, RS-232 and RS-485 inter-

faces. The module also includes an IrDA encoder and

decoder.

The primary features of the UART module are:

• Full-Duplex 8 or 9-bit Data Transmission through

the U1TX and U1RX pins

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

• Fully Integrated Baud Rate Generator with 16-bit

Prescaler

• Baud Rates Ranging from 1 Mbps to 15 bps at

16 MIPS

• 4-Deep First-In-First-Out (FIFO) Transmit Data

Buffer

• 4-Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error Detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive Interrupts

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Supports Automatic Baud Rate Detection

• IrDA Encoder and Decoder Logic

• 16x Baud Clock Output for IrDA Support

A simplified block diagram of the UART is shown in

Figure 15-1. The UART module consists of these key

important hardware elements:

• Baud Rate Generator

• Asynchronous Transmitter

• Asynchronous Receiver

FIGURE 15-1: UART SIMPLIFIED BLOCK DIAGRAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

U1RX

IrDA®

UAR T 1 Rece iv er

UART1 Transmitter U1TX

Baud Rate Generator

dsPIC30F1010/202X

15.1 UART Baud Rate Generator (BRG)

The UART module includes a dedicated 16-bit Baud

Rate Generator. The U1BRG register controls the

period of a free-running 16-bit timer. Equation 15-1

shows the formula for computation of the baud rate

with BRGH = 0.

EQUATION 15-1: UART BAUD RATE WITH

BRGH = 0(1,2,3)

Example 15-1 shows the calculation of the baud rate

error for the following conditions:

•F

CY = 7.5 MHz

• Desired Baud Rate = 9600

The maximum baud rate (BRGH = 0) possible is

FCY/16 (for U1BRG = 0), and the minimum baud rate

possible is FCY/(16 * 65536).

Equation 15-2 shows the formula for computation of

the baud rate with BRGH = 1.

EQUATION 15-2: UART BAUD RATE WITH

BRGH = 1(1,2,3)

The maxim um bau d rate (BRGH = 1) pos si ble is F CY/4

(for U1BRG = 0) and the minimum baud rate possible

is FCY/(4 * 65536).

Writing a new value to the U1BRG register causes the

BRG timer to be reset (cleared). This ens ures the BRG

does not wai t for a timer overflow be fore generating the

new baud rate.

EXAMPLE 15-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1)

Note 1: FCY denotes the instruction cycle clock

frequency (FOSC/2).

2: Assuming external oscillator with fre-

quency of 15 MHz and PLL disabled,

FCY is 7.5 MHz.

3: Assuming external oscillator with fre-

quency of 15 MHz and PLL enabled,

FCY is 30 MHz.

Baud Rate = FCY

16 • (U1BRG + 1)

FCY

16 • Baud Rate

U1BRG = – 1

Baud Rate = FCY

4 • (U1BRG + 1)

FCY

4 • Baud Rate

U1BRG = – 1

Note 1: FCY denotes the instruction cycle clock

frequency.

2: Assuming external oscillator with fre-

quency of 15 MHz and PLL disabled,

FCY is 7.5 MHz.

3: Assuming external oscillator with fre-

quency of 15 MHz and PLL enabled,

FCY is 30 MHz.

Desired B aud Rat e = Fcy/(16 (U1BR G + 1))

Solving for U1BR G va lue:

U1BRG = ((FCY/Des ired Baud Ra te)/16 ) – 1

U1BR G = ( (7500000/ 9600)/1 6) – 1

U1BRG = 48

Calcula te d Ba ud Rate = 7500 000/(16 (48 + 1))

= 9 566

Error = (Calculated Baud Rate – Desired Baud Rate)

Desire d Baud Ra te

= (9566 – 9600)/9600

=-0.35%

Note 1: Based on TCY = 2/FOSC, PL L are disabled.

dsPIC30F1010/202X

15.2 Transmitting in 8-bit Data Mode

1. Set up the UART:

a) Write appropriate values for data, parity and

Stop bits.

b) Write appropriate baud rate value to the

U1BRG register.

c) Set up transmit and receive interru pt enable

and priority bits.

2. Enable the UART.

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write d ata byt e to lo wer by te of T XxRE G word.

The value will be immediately transferred to the

Transmit Shift Register (TSR), and the serial bit

stream wi ll start sh ifting out with next rising edge

of the baud clock.

5. Alternately, the data byte may be transferred

while UTXEN = 0, and then the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

6. A transmit interrupt will be generated as per

interrupt control bit, UTXISELx.

15.3 Transmitting in 9-bit Data Mode

1. Set up the UART (as described in Section 15.2

“Transmitting in 8-bit Data Mode”).

2. Enable the UART.

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write TXxREG as a 16-bit value only.

5. A word write to TXxREG triggers the transfer of

the 9-bit data to the TSR. Serial bit stream will

start shifting out with the first rising edge of the

baud clock.

6. A transmit interrupt will be generated as per the

setting of control bit, UTXISELx.

15.4 Break and Sync Transmit

Sequence

The following sequence will send a message frame

header made up of a Break, followed by an auto-baud

Sync byte.

1. Configure the UART for the desired mode.

2. Set UTXEN and UTXBRK – sets up the Break

character,

3. Load the TXxREG with a dummy character to

initiate transmission (value is ignored).

4. Write ‘55h’ to TXxREG – loads Sync character

into the transm it FIFO .

5. After the Break has been sent, the UTXBRK bit

is reset by hardware. The Sync character now

transmits.

15.5 Receiving in 8-bit or 9-bit Data

Mode

1. Set up the UART (as described in Section 15.2

“Transmitting in 8-bit Data Mode”).

2. Enable the UART.

3. A receive interrupt will be generated when one

or mor e da ta c har ac t ers ha ve be e n re ce iv ed as

per interrupt control bit, URXISELx.

4. Read the OERR bit to determine if an overrun

error has occ urred. The OERR bit mus t be reset

in software.

5. Read RXxREG.

The act of read ing the RXxREG character will move the

next character to the top of the rec eiv e FI FO , inc lu din g

a new set of PERR and FERR values.

15.6 Built-in IrDA Encoder and Deco der

The UART has full im pl em entation of the IrDA enc od er

and decoder as part of the UART module. The built-in

IrDA encoder and decoder functionality is enabled

using the IREN bit U1MODE<12>. When enabled

(IREN = 1), the receive pin (U1RX) acts as the input

from the infrared receiver. The transmit pin (U1 TX) acts

as the output to the infrared transmitter.

15.7 Alternate UART I/O Pins

An alternat e set of I/O pins, U1ATX and U1ARX can be

used for c ommunication s. The alternate UAR T pins are

useful when the primary UAR T pins are shared by other

peripherals. The alternate I/O pins are enabled by set-

ting the ALTIO bit in the UxMODE register. If ALTIO =

1, the U1ATX and U1ARX pins are used by the UART

module, instead of the U1TX and U1RX pins. If ALTIO

= 0, the U1TX and U1RX pins are used by the UART

module.

dsPIC30F1010/202X

R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0

UARTEN — USIDL IREN —ALTIO— —

bit 15 bit 8

R/W-0 HC R/W-0 R/W-0 HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL

bit 7 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit HC = Hardware Cleared HS = Hardware Select

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 UARTEN: UART1 Enable bit

= UART1 enabled; all UART1 pins are controlled by UART1 as defined by UEN<1:0>

= UAR T1 disabled; a ll UAR T1 pins are con trolled by PO R T latche s; UA R T1 p ower consu mp tion minimal

bit 14 Unimplemented: Read as ‘0’

bit 13 USIDL: Sto p in Idle Mo de bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12 IREN: IrDA Encoder and Decoder Enable bit

1 = IrDA encoder and decoder enabled

0 = IrDA encoder and decoder disabled

Note: This feature is only available for the 16x BRG mode (BRGH = 0).

bit 11 Unimplemented: Read as ‘0’

bit 10 ALTIO: UART Alternate I/O Selection bit

1 = UART communicates using U1ATX and U1ARX I/O pins

0 = UART communicates using U1TX and U1RX I/O pins.

bit 9-8 Unimplemented: Read as ‘0’

bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit

1 = UART1 will continue to sample the U1RX pin; interrupt generated on falling edge, bit cleared in

hardware on following rising edge

0 = No wake-up enabled

bit 6 LPBACK: UART1 Loopback Mode Select bit

1 = Enable Loopback mode

0 = Loopback mode is disabled

bit 5 ABAUD: Auto-Baud Enable bit

1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);

cleared in hard w are upo n comple tion

0 = Baud rate measurement disabled or completed

bit 4 RXINV: Receiv e Polarity Inv ers ion bit

1 = U1RX Idle state is ‘0’

0 = U1RX Idle state is ‘1’

bit 3 BRGH: High Baud Rate Enable bit

1 = BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode)

0 = BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode)

dsPIC30F1010/202X

bit 2-1 PDSEL1:PDSEL0: Parity and Data Selection bits

11 = 9-bit data, n o parity

10 = 8-bit data, odd parity

01 = 8-bit data, even parity

00 = 8-bit data, n o parity

bit 0 STSEL: Stop Bit Selection bit

1 = Two Stop bits

0 = One Stop bit

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

UTXISEL1 UTXINV(1) UTXISEL0 — UTXBRK UTXEN UTXBF TRMT

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA

bit 7 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit HS =Hardware Set HC = Hardware Cleared

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15, 13 UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits

11 =Reser ved; do not us e

10 =Interrupt when a character is transferred to the Transmit Shift Register and as a result, the

transmit buffer becomes empty

01 =Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit

operation s are com pl ete d

00 =Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at

least one character open in the transmit buffer)

bit 14 UTXINV: IrDA Encoder Transmit Polarity Inversion bit(1)

1 = IrDA encoded U1TX idle state is ‘1’

0 = IrDA encoded U1TX idle state is ‘0’

Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is

enabled (IREN = 1).

bit 12 Unimplemented: Read as ‘0’

bit 11 UTXBRK: Transmit Break bit

1 = Send Sync Break on next tran smissi on – S t art bit, foll owed by twe lve ‘0’ bit s, foll owed by Stop bit;

cleared by hardware upon completion

0 = Sync Break transmission disabled or completed

bit 10 UTXEN: Transmit Enable bit

1 = Transmit enabled, U1TX pin controlled by UART1

0 = Transmit disabled, any pending transmission is aborted and buffer is reset. U1TX pin controlled by

PORT.

bit 9 UTXBF: Transmit Buffer Full Status bit (Read-Only)

1 = Transmit buffer is full

0 = Transmit buffer is not full, at least one more character can be written

bit 8 TRMT: Transmit Shift Register Empty bit (Read-Only)

1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has

completed)

0 = Transmit Shift Register is not empty, a transmission is in progress o r que ued

bit 7-6 URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits

11 =Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)

10 =Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)

0x =Interrupt is set wh en any chara cter is receive d and transferred from the RSR to the receive bu ffer .

Receive buffer has one or more characters.

bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.

0 = Address Detect mode disabled

dsPIC30F1010/202X

bit 4 RIDLE: Receiver Idle bit (Read-Only)

1 = Receiver is Idle

0 = Receiver is active

bit 3 PERR: Parity Error Status bit (Read-Only)

1 = Parity error has been detec ted fo r the current chara cter (c haract er at t he top o f the receive FIFO)

0 = Parity error has not been detected

bit 2 FERR: Framing Error Status bit (Read-Only)

1 = Framing error has been detected for the current character (character at the top of the receive

FIFO)

0 = Framing error has not been detected

bit 1 OERR: Receive Buffer Overrun Error Status bit (Read/Clear-Only)

1 = Receive buffer has overflowed

0 = Receive bu ffer has not overfl owed (clearin g a previou sly set O ERR bit (1→0 transition) will reset

the receiver buffer and the RSR to the empty state)

bit 0 URXDA: Receive Buffer Data Available bit (Read-Only)

1 = Receive buffer has data, at least one more character can be read

0 = Receive buffer is empty

dsPIC30F1010/202X

TABLE 15-1: UART1 REGISTER MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

U1MODE 0220 UARTEN —USIDLIREN—ALTIO—— WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL

0000

U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

0110

U1TXREG 0224 — — — — — — — UAR T Transmit R egi ster

xxxx

U1RXREG 0226 — — — — — — — UAR T Receiv e Register

0000

U1BRG 0228 Ba ud R a te G en era to r P re sca le r

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

© 2006 Microchip Technology Inc. Preliminary DS70178C-page 169
dsPIC30F1010/202X
16.0 10-BIT 2 MSPS ANALOG-TO-
DIGITAL CONVERTER (ADC) 
MODULE
The dsPIC30F1010/202X devices provide high-speed
successive approximatio n analog to digita l conversions
to support applications such as AC/DC and DC/DC
power convert ers.
16.1 Features
• 10-bit resolution
• Uni-polar Inp uts
• Up to 12 input channels
• ±1 LSB accuracy
• Single supply operation
• 2000 ksps conversion rate at 5V
• 1000 ksps conversion rate at 3.0V
• Low power CMOS technology
16.2 Description
This ADC module is designed for applications that
require l ow l atency b etwe en the  reques t for con versio n
and the resultant output data. Typical applications
include:
• AC/DC power supplies
• DC/DC converters
• Power factor correcti on
This ADC works with the Power Supply PWM module
in power control applications that require high-fre-
quency control loops. This module can sample and
convert two analog in puts in one microsecond. The  one
micros econd con version de lay reduce s the “phase la g”
between measurement and control system response.
Up to 4 inputs may be sampled at a time, and up  to 12
inputs may request conversion at a time. If multiple
input s request co nversion, the ADC will convert them in
a sequential manner starting with the lowest order
input.
This ADC design provides each pair of analog inputs
(AN1,AN0), (AN3,AN2 ), ... , the a bility to speci fy its own
trigger source out of a maximum of sixteen different
trigger sources. This capability allows this ADC to sam-
ple and convert analog inputs that are associated with
PWM generators operating on independent time
bases.
There is no operation during Sleep mode. The user
applications typically require synchronization between
analog data sampling and PWM output to the applica-
tion cir cuit.   The v ery high s peed oper ation of thi s ADC
module allows “data  on demand”.
In addition, several hardware features have been
added to the peripheral interface to improve real-time
performance in a typical DSP based application.
1. Result alignment options
2. Automated sampling
3. External con ver si on st a r t cont rol
A block diagram of the ADC module is shown in 
Figure 16-1.
16.3 Module Functionality
The 10-bit 2 Msps ADC is designed to support power
conversion applications when used with the Power
Supply  PWM m odule.  The 1 0-bit  2 Msp s  ADC sa mple s
up to N (N ≤ 1 2) in puts at a time and the n co nv ert s  tw o
sampled inputs at a time. The quantity of sample and
hold circuits is determined by a device’s requirements.
The10-Bit  2 Msp s ADC pr oduces t wo 10-bi t conversio n
results in 1 microsecond.
The ADC m od ule  su ppo rts up to 12 anal og  inp ut s . Th e
sampled inputs are connected, via multiplexers, to the
converter. 
The analog reference voltage is defined as the device
supply voltage (AVDD / AVSS). 
The ADC modul e us es the se  Cont rol  and Status  regis -
ters:
• A/D Control Register (ADCON)
• A/D Status Register (ADSTAT)
• A/D Base Register (ADBASE)
• A/D Port Configuration Register (ADPCFG)
• A/D Convert Pair Control Register #0 (ADCPC0)
• A/D Convert Pair Control Register #1 (ADCPC1)
• A/D Convert Pair Control Register #2 (ADCPC2)
The ADCON reg ister control s the operatio n of the ADC
module . The ADSTA T re gister dis plays the s tatus of  the
conversion processes. The ADPCFG registers config-
ure the port pins as analog inputs or as digital I/O. The
CPC registe rs control the  triggerin g of the ADC conver-
sions. (See Register 16-1 through Register 16-7 for
detailed bit configurations.)
Note: A uniq ue feat ure of th e ADC m odul e is i ts  abil-
ity to sample inputs in an asynchronous manner.
Individual sample and hold circuits can be triggered
independently of each other.
Note: The PLL  must be enabled for the  ADC module
to function. This is achieved by using the
FNOSC<1:0> bits in the FOSCSEL Configuration
register.

dsPIC30F1010/202X

FIGURE 16-1: ADC BLOCK DIAGRAM

AVSS

AVDD

Data

Bus Interface

MUX/Sample/Sequence

Control

Format

DAC

12-word, 16-bit

Registers

Comparator

10-Bit SAR Conversion Logic

AN0

AN2

AN6

AN1

AN11

AN3

AN8

AN10

Even numbered inputs

without dedicated

Dedicated Sample & Holds

AN4

Common Sample and Hold

Sample and Hold

dsPIC30F1010/202X

R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0

ADON —ADSIDL——GSWTRG—FORM

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-1 R/W-1

EIE ORDER SEQSAMP —— ADCS<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADON: A/D Operating Mode bit

1 = A/D converter module is ope rati ng

0 = A/D converter is off

bit 14 Unimplemented: Read as ‘0’

bit 13 ADSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module oper ation in Idle mode

bit 12-11 Unimplemented: Read as ‘0’

bit 10 GSWTRG: Global Software Trigger bit

When thi s bit is se t b y the us er, it will tri gge r c onv ers io ns if s ele ct ed by th e TRGSRC<4:0> bits in the

ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e.,

this bit is not auto-c lea ring ).

bit 9 Unimplemented: Read as ‘0’

bit 8 FORM: Data Output Format bit

1 = Fractional (DOUT = dddd dddd dd00 0000)

0 = Integer (DOUT = 0000 00dd dddd dddd)

bit 7 EIE: Early Interrupt Enable bit

1 = Interrupt is generated after first conversion is completed

0 = Interrupt is generated after second conversion is completed

Note: This control bit can only be changed while ADC is disabled (ADON = 0).

bit 6 ORDER: Conversion Order bit

1 = Odd numbered analog input is converted first, followed by conversion of even numbered input

0 = Even numbered analog input is converted first, followed by conversion of odd numbered input

Note: This control bit can only be changed while ADC is disabled (ADON = 0).

bit 5 SEQSAMP: Sequential Sample Enable.

1 = Shared S&H is sampled at the start of the second conversion if ORDER = 0. If ORDER = 1, then

the shared S&H is sampled at the start of the first conversion.

0 = Shared S&H is sa mp led at the same time the dedi ca ted S&H i s sa mp le d if th e sh ared S&H is n ot

currently busy with an existing conversion process. If the shared S&H is busy at the time the

dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion

cycle

bit 4-3 Unimplemented: Read as ‘0’

dsPIC30F1010/202X

bit 2-0 ADCS<2:0>: A/D Conversion Clock Divider Select bits

If PLL is enabled (assume 15 MHz external clock as clock source):

111 = FADC/18 = 13.3 MHz @ 30 MIPS

110 = FADC/16 = 15.0 MHz @ 30 MIPS

101 = FADC/14 = 17.1 MHz @ 30 MIPS

100 = FADC/12 = 20.0 MHz @ 30 MIPS

011 = FADC/10 = 24.0 MHz @ 30 MIPS

010 = FADC/8 = 30.0 MHz @ 30 MIPS

001 = FADC/6 = Reserved, defaults to 30 MHz @ 30 MIPS

000 = FADC/4 = Reserved, defaults to 30 MHz @ 30 MIPS

If PLL is disabled (assume 15 MHz external clock as clock source):

111 = FADC/18 = 0.83 MHz @ 7.5 MIPS

110 = FADC/16 = 0.93 MHz @ 7.5 MIPS

101 = FADC/14 = 1.07 MHz @ 7.5 MIPS

100 = FADC/12 = 1.25 MHz @ 7.5 MIPS

011 = FADC/10 = 1.5 MHz @ 7.5 MIPS

010 = FADC/8 = 1.87 MHz @ 7.5 MIPS

001 = FADC/6 = 2.5 MHz @ 7.5 MIPS

000 = FADC/4 = 3.75 MHz @ 7.5 MIPS

Note: See Figure 18-2 for AD C clock derivation.

dsPIC30F1010/202X

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 R/C-0

H-S R/C-0

H-S

—— P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR

C = Clear in software ‘1’ = Bit is set

H-S = Set by hardware ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 Unimplemented: Read as ‘0’

bit 5 P5RDY: Conversion Data for Pair #5 Ready bit

Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.

bit 4 P4RDY: Conversion Data for Pair #4 Ready bit

Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.

bit 3 P3RDY: Conversion Data for Pair #3 Ready bit

Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.

bit 2 P2RDY: Conversion Data for Pair #2 Ready bit

Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.

bit 1 P1RDY: Conversion Data for Pair #1 Ready bit

Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.

bit 0 P0RDY: Conversion Data for Pair #0 Ready bit

Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADBASE<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

ADBASE<7:1> —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-1 ADC Base Register: This register cont ains the base address of the user’s ADC Interrupt Service Rou-

tine jump table. This register, when read, contains the sum of the ADBASE register contents and the

encoded value of the PxRDY Status bits.

The encoder logic provides the bit number of the highest priority PxRDY bits where P0RDY is the

highest priority, and P5RDY is lowest priority.

Note: The encoding results are shifted left two bits so bits 1-0 of the result are always zero.

bit 0 Unimplemented: Read as ‘0’

Note: As an alternative to using the ADBASE Register, the ADCP0-5 ADC Pair Conversion Complete Interrupts

(Interrupts 37-42) can be used to invoke A to D conversion completion routines for individual ADC input

pairs. Refer to Section 16.9 “Individual Pair Interrupts”.

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — PCFG11 PCFG10 PCFG9 PCFG8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-0 PCFG<11:0>: A/D Port Configuration Control bits

1 = Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS

0 = Port pin in Analog mode, port read input disabled, A/D samples pin voltage

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRQEN1 PEND1 SWTRG1 TRGSRC1<4:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 IRQEN1: Interrupt Request Enable 1 bit

1 = Enable IRQ generation when requested conversion of channels AN3 and AN2 is completed

0 = IRQ is not generated

bit 14 PEND1: Pending Conversion Status 1 bit

1 = Conversion of channels AN3 and AN2 is pending. Set when selected trigger is asserted

0 = Conversion is complete

bit 13 SWTRG1: Software Trigger 1 bit

1 = Start conversion of AN3 and AN2 (if selected in TRGSRC bits). If other conversions are in

progress, th en conversion w ill be perform ed when the conv ersion resources are available. Thi s bit will

be reset when the PEND bit is set.

bit 12-8 TRGSRC1<4:0>: Trigger 1 Source Selection bits

Selects trigger source for conversion of analog channels AN3 and AN2.

00000 = No conversion enabled

00001 = Individual software trigger selected

00010 = Global software trigger selected

00011 = PWM Special Event Trigger selected

00100 = PWM generator #1 trigger selected

00101 = PWM generator #2 trigger selected

00110 = PWM generator #3 trigger selected

00111 = PWM generator #4 trigger selected

01100 = Timer #1 period match

01101 = Timer #2 period match

01110 = PWM GEN #1 current-limit ADC trigger

01111 = PWM GEN #2 current-limit ADC trigger

10000 = PWM GEN #3 current-limit ADC trigger

10001 = PWM GEN #4 current-limit ADC trigger

10110 = PWM GEN #1 fault ADC trigger

10111 = PWM GEN #2 fault ADC trigger

11000 = PWM GEN #3 fault ADC trigger

11001 = PWM GEN #4 fault ADC trigger

bit 7 IRQEN0: Interrupt Request Enable 0 bit

1 = Enable IRQ generation when requested conversion of channels AN1 and AN0 is completed

0 = IRQ is not generated

bit 6 PEND0: Pending Conversion Status 0 bit

1 = Conversion of channels AN1 and AN0 is pending. Set when selected trigger is asserted.

0 = Conversion is complete

bit 5 SWTRG0: Software Trigger 0 bit

1 = Start conversion of AN1 and AN0 (if selected by TRGSRC bits). If other conversions are in

progress, th en conversion w ill be perform ed when the conv ersion resources are available. Thi s bit will

be reset when the PEND bit is set

dsPIC30F1010/202X

bit 4-0 TRGSRC0<4:0>: Trigger 0 Source Selection bits

Selects trigger source for conversion of analog channels AN1 and AN0.

00000 = No conversion enabled

00001 = Individual software trigger selected

00010 = Global software trigger selected

00011 = PWM Special Event Trigger selected

00100 = PWM generator #1 trigger selected

00101 = PWM generator #2 trigger selected

00110 = PWM generator #3 trigger selected

00111 = PWM generator #4 trigger selected

01100 = Timer #1 period match

01101 = Timer #2 period match

01110 = PWM GEN #1 current-limit ADC trigger

01111 = PWM GEN #2 current-limit ADC trigger

10000 = PWM GEN #3 current-limit ADC trigger

10001 = PWM GEN #4 current-limit ADC trigger

10110 = PWM GEN #1 fault ADC trigger

10111 = PWM GEN #2 fault ADC trigger

11000 = PWM GEN #3 fault ADC trigger

11001 = PWM GEN #4 fault ADC trigger

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRQEN3 PEND3 SWTRG3 TRGSRC3<4:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 IRQEN3: Interrupt Request Enable 3 bit

1 = Enable IRQ generation when requested conversion of channels AN7 and AN6 is completed.

0 = IRQ is not generated

bit 14 PEND3: Pending Conversion Status 3 bit

1 = Conversion of channels AN7 and AN6 is pending. Set when selected trigger is asserted.

0 = Conversion is complete

bit 13 SWTRG3: Software Trigger 3 bit

1 = Start conversion of AN7 and AN6 (if selected by TRGSRC bits). If other conversions are in

progress, th en conversion w ill be perform ed when the conv ersion resources are available. Thi s bit will

be reset when the PEND bit is set.

bit 12-8 TRGSRC3<4:0>: T ri gg er 3 Source Selection bit s

Selects trigger source for conversion of analog channels A7 and A6.

00000 = No conversion enabled

00001 = Individual software trigger selected

00010 = Global software trigger selected

00011 = PWM Special Event Trigger selected

00100 = PWM generator #1 trigger selected

00101 = PWM generator #2 trigger selected

00110 = PWM generator #3 trigger selected

00111 = PWM generator #4 trigger selected

01100 = Timer #1 period match

01101 = Timer #2 period match

01110 = PWM GEN #1 current-limit ADC trigger

01111 = PWM GEN #2 current-limit ADC trigger

10000 = PWM GEN #3 current-limit ADC trigger

10001 = PWM GEN #4 current-limit ADC trigger

10110 = PWM GEN #1 fault ADC trigger

10111 = PWM GEN #2 fault ADC trigger

11000 = PWM GEN #3 fault ADC trigger

11001 = PWM GEN #4 fault ADC trigger

bit 7 IRQEN2: Interrupt Request Enable 2 bit

1 = Enable IRQ generation when requested conversion of channels AN5 and AN4 is completed

0 = IRQ is not generated

bit 6 PEND2: Pending Conversion Status 2 bit

1 = Conversion of channels AN5 and AN4 is pending. Set when selected trigger is asserted

0 = Conversion is complete

bit 5 SWTRG2: Software Trigger 2 bit

1 = Start conversion of AN5 and AN4 (if selected by TRGSRC bits). If other conversions are in

progress, th en conversion w ill be perform ed when the conv ersion resources are available. Thi s bit will

be reset when the PEND bit is set

dsPIC30F1010/202X

bit 4-0 TRGSRC2<4:0>: Trigger 2 Source Selection bits

Selects trigger source for conversion of analog channels: AN5 and AN4

00000 = No conversion enabled

00001 = Individual software trigger selected

00010 = Global software trigger selected

00011 = PWM Special Event Trigger selected

00100 = PWM generator #1 trigger selected

00101 = PWM generator #2 trigger selected

00110 = PWM generator #3 trigger selected

00111 = PWM generator #4 trigger selected

01100 = Timer #1 period match

01101 = Timer #2 period match

01110 = PWM GEN #1 current-limit ADC trigger

01111 = PWM GEN #2 current-limit ADC trigger

10000 = PWM GEN #3 current-limit ADC trigger

10001 = PWM GEN #4 current-limit ADC trigger

10110 = PWM GEN #1 fault ADC trigger

10111 = PWM GEN #2 fault ADC trigger

11000 = PWM GEN #3 fault ADC trigger

11001 = PWM GEN #4 fault ADC trigger

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRQEN5 PEND5 SWTRG5 TRGSRC5<4:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRQEN4 PEND4 SWTRG4 TRGSRC4<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15

IRQEN5:

Interrupt Request Enable 5 bit

1 = Enable IRQ generation when requested conversion of channels AN11 and AN10 is completed

0 = IRQ is not generated

bit 14 PEND5: Pending Conversion Status 5 bit

1 = Conversion of channels AN11 and AN10 is pending. Set when selected trigger is asserted

0 = Conversion is complete

bit 13 SWTRG5: Software Trigger 5 bit

1 = Start conversion of AN11 and AN10 (if selected by TRGSRC bits). If other conversions are in

progress, th en conversion w ill be perform ed when the conv ersion resources are available. Thi s bit will

be reset when the PEND bit is set.

bit 12-8 TRGSRC5<4:0>: Trigger Source Selection 5 bits

Selects trigger source for conversion of analog channels A11 and A10.

00000 = No conversion enabled

00001 = Individual software trigger selected

00010 = Global software trigger selected

00011 = PWM Special Event Trigger selected

00100 = PWM generator #1 trigger selected

00101 = PWM generator #2 trigger selected

00110 = PWM generator #3 trigger selected

00111 = PWM generator #4 trigger selected

01100 = Timer #1 period match

01101 = Timer #2 period match

01110 = PWM GEN #1 current-limit ADC trigger

01111 = PWM GEN #2 current-limit ADC trigger

10000 = PWM GEN #3 current-limit ADC trigger

10001 = PWM GEN #4 current-limit ADC trigger

10110 = PWM GEN #1 fault ADC trigger

10111 = PWM GEN #2 fault ADC trigger

11000 = PWM GEN #3 fault ADC trigger

11001 = PWM GEN #4 fault ADC trigger

bit 7 IRQEN4: Interrupt Request Enable 4 bit

1 = Enable IRQ generation when requested conversion of channels AN9 and AN8 is completed

0 = IRQ is not generated

bit 6 PEND4: Pending Conversion Status 4 bit

1 = Conversion of channels AN9 and AN8 is pending. Set when selected trigger is asserted.

0 = Conversion is complete

bit 5 SWTRG4: Software Trigger 4 bit

1 = Start conversion of AN9 and AN8 (if selected by TRGSRC bits). If other conversions are in

progress, th en convers ion will be perfo rmed when the conversio n resources are availab le. This bit will

be reset when the PEND bit is set.

dsPIC30F1010/202X

bit 4-0 TRGSRC4<4:0>: Trigger Source Selection 4 bits

Selects trigger source for conversion of analog channels: AN9 and AN8

00000 = No conversion enabled

00001 = Individual software trigger selected

00010 = Global software trigger selected

00011 = PWM Special Event Trigger selected

00100 = PWM generator #1 trigger selected

00101 = PWM generator #2 trigger selected

00110 = PWM generator #3 trigger selected

00111 = PWM generator #4 trigger selected

01100 = Timer #1 period match

01101 = Timer #2 period match

01110 = PWM GEN #1 current-limit ADC trigger

01111 = PWM GEN #2 current-limit ADC trigger

10000 = PWM GEN #3 current-limit ADC trigger

10001 = PWM GEN #4 current-limit ADC trigger

10110 = PWM GEN #1 fault ADC trigger

10111 = PWM GEN #2 fault ADC trigger

11000 = PWM GEN #3 fault ADC trigger

11001 = PWM GEN #4 fault ADC trigger

dsPIC30F1010/202X

16.4 ADC Result Buffer

The ADC module contains up to 12 data output regis-

ters to store the A/D results called ADCBUF<11:0>.

The registers are 10 bits wide, but are read into differ-

ent format, 16-bit words. The buffers are read-only.

Each analog input has a corresponding data

output register.

This module DOES NOT include a circular data

buffer or FIFO. Because the conversion results may

be produced in any order, such schemes will not work

since there would be no means to determine which

data is in a specific location.

The SAR write to the buffers is synchronous to the

ADC clock. Reads from the buffers will always have

valid data assuming that the data-ready interrupt has

been processed.

If a buffer location has not been read by the software

and the SAR needs to overwrite that location, the

previous data is lost.

Reads from the result buffer pass through the data for-

matter. The 10 bi t s of the res ult data are form att ed in to

a 16-bit word.

16.5 Application Information

The ADC module implements a concept based on

“Conversion Pairs”. In power conversion applications,

there is a need to measure voltages and currents for

each PWM control loop. The ADC module enables the

sample and conversion process of each conversion

pair to be precisely timed relative to the PWM signals.

In a user’s application circuit, the PWM signal enables

a transisto r, which all ows an induc tor to charge up with

current to a desired value. The long er a PWM signal is

on, the longer the inductor is charging, and therefore

the inductor current is at its maximum at the end of the

PWM signal. Often, this is the point where the user

wants to ta ke the current and voltage measurements.

Figur e 16-2 shows a ty pic al power co nv ers ion appl ic a-

tion (a boost converter) where the current sensing of

the induc tor is don e by mon itorin g the vol tage acr oss a

resistor in series with the power transistor that

“charges” the inductor. The significant feature of this

figure is that if the sampling of the resistor voltage

occurs slightly later than the desired sample point, the

data read will be zero. This is not acceptable in most

applications. The ADC module always samples the

analog voltages at the appointed time regardless of

whether the ADC converter is busy or not.

The Power Supply PWM module supports 2-4 indepen-

dent PWM c hannels a s wel l as 2-4 t rigg er s ign als (on e

per PWM generator). The user can configure these

channels to initiate an ADC conversion of a selected

input pair at the proper time in the PWM cycle. The

Power Supply PWM module also provides an addi-

tional trigger signal (Special Event Trigger), which can

be programmed to occur at a specified time during the

primary ti me base count cycle.

FIGURE 16-2: APPLICATION EXAMPLE: IMPORTANCE OF PRECISE SA MPLI NG

PWM

Late sample yields

zero data

Desired sample point

Critical Edge

+VIN IL

PWM

VISENSE

VOUT

COUT

Measuring peak inductor current is very important

Example Boost Converter

dsPIC30F1010/202X

16.6 Reverse Conversion Order

The ORDER control bit in the ADCON register, when

set, rever ses the order of the input pa ir conversion pro-

cess. Normally (ORDER = 0), the even numbered

input of an in put p air is converted first and then the od d

numbered input is converted. If ORDER = 1, the odd

numbered input pin of an input pair is converted first,

followed by the even numbered pin.

This feature is useful when using voltage control

modes and using the early interrupt capability

(EIE = 1). These features enable the user to minimize

the time period from actual acquisition of the feedback

(ADC) data to the update of the control output (PWM).

This time from input to output of the control system

determines the ov erall stab ility of the control system.

16.7 Simultaneous and Sequential

Sampling in a pair

The inputs that have dedicated Sample and Hold

(S&H) circui t s a re s amp le d w hen the ir s pecified trigger

events occur. The inputs that share the common sam-

ple and hold circuit are sampled in the following

manner:

1. If the SEQSAMP bit = 0, and the common

(shared) sample and hold circuit is NOT busy,

then the shared S&H will sample their specified

input at the same time as the dedicated S&H.

This action provides “Simul taneous” sample and

hold functionality.

2. If the SEQSAMP bit = 0, and the shared S&H is

currently busy with a conversion in progress,

then the shared S&H will sample as soon as

possible (at the start of the new conversion

process for the pair).

3. If the SEQSAMP bit = 1, then the shared S&H

will sample at the start of the conversion process

for that in put. For ex ample: If th e ORDER bit = 0

the shared S&H will sample at the start of the

conversion of the second input. If ORDER = 1,

then the shared S&H will sample at the start of

the conversion for the first input.

The SEQSAMP bit is useful for some applica-

tions that want to minimize the time from a

sample event to the conversion of the sample.

When SEQSAMP = 0, the logi c attem pt s to t ake

the samp les for both in put s of a pai r at the same

time if the reso urces are available. T he user can

often ensure that the ADC will not be busy with

a prior conversion by controlling the timing of the

trigger signals that initiate the conversion

processes.

16.8 Group Interrupt Generation

The ADC m odu le p rov ide s a com m on o r “G roup ” int er-

rupt requ est that is the OR o f all of th e enabled interrupt

sources within the module. Each CPC register has two

IRQENx bits, one for each analog input pair. If the

IRQEN bit is set, an interrupt request is made to the

interrupt controller when the requested conversion is

completed. When an interrupt is generated, an asso-

ciated PxRDY bit in the ADSTAT register is set. The

PxRDY bit is cleared by the user. The user’s software

can examine the ADSTAT register’s PxRDY bits to

determine if additional requested conversions have

been completed.

The group inte rrup t is use ful for applica tio ns that use a

common software routine to process ADC interrupts for

multiple analog input pairs. This method is more

tradit ion al in con ce pt.

Note: The us er must cle ar the IFS bit associ ated

with the ADC in the interrupt controller

before the PxRDY bit is cleare d. Failure to

do so m ay caus e i nte rrupts to be los t. Th e

reason is that the ADC will possibly have

another interrupt pending. If the user

clears the PxRDY bit first, the ADC may

generate another interrupt request, but if

the user then clears the IFS bit, the

interrupt request will be erased.

dsPIC30F1010/202X

16.9 Individual Pair Interrupts

The ADC module also provides individual interrupts

output s for each a nalog input pai r. These i nterrupt s a re

always enabled within the module. The pair interrupts

can be individually enabled or disabled via the

associated interrupt enable bits in the IEC registers.

Using the group interrupts may require the interrupt

service routine to determine which interrupt source

generated the interrupt. For applications that use sep-

arat e software tasks to pro cess ADC da ta, a common

interrupt vector can cause performance bottlenecks.

The use of the indivi dual p ai r interrup ts c an save many

clock cycles compared to using the group interrupt to

process multiple interrupt sources. The individual pair

interrupts support the construction of application

software that is responsive and organized on a task

basis.

Regardless of whether an individual p air interrupt or the

global interrupt are used to respond to an interrupt

request from an ADC conversion, the PxRDY bit s in the

ADSTAT register function in the same manner.

The use of the individual pair interrupts also enables

the user to change the interrupt priority of individual

ADC channels (pairs) as compared to the fixed priority

structure of the group interrupt.

NOTE: The use of individual interrupts DOES NOT

affect the pr iority structur e of the ADC with respect

to the order of input pair conversion.

The us e of indi vidual interrup ts c an reduce the prob lem

of accidently “losing” a pending interrupt while

processing and clearing a current interrupt

16.10 Early Interrupt Generation

The EIE control bit in the ADCON register enables the

generation of the interrupts after completion of the first

convers ion instead of wai ting for the completio n of both

inputs of an input pair. Even though the second input

will still be in the conversion process, the software can

be written to perform some of the computations using

the first data value while the second conversion is

completed.

The use r softwa re can be written to acco unt for the 500

nsec conversion period of the second input before

using the second data, or the user can poll the PEND

bit in the ADCPCx register.

The PEND bit remains set until both conversions of a

pair h ave been compl eted. The PxRD Y bit for the ass o-

ciated interrupt is set in the ADSTAT register at the

comple tion of the first con version, and remain s set until

it is cleared by the user.

16.11 Conflict Resolution

If more than one conversion pair request is active at the

same time, the ADC control logic processes the

requests in a top-down manner, starting at analog pair

#0 (AN1/AN0) and ending at analog pair #5 (AN11/

AN10). This is not a “round-robin” process.

16.12 Deliber ate Conflicts

If the user specifies the same conversion trigger source

for multiple “conversion pairs”, then the ADC module

function s like o ther dsPIC3 0F ADC module s; i.e., it pro-

cesses the requested conversions sequentially (in

pairs) until the sequence has been completed.

16.13 ADC Clock Selection

The ADCS<2:0> bits in the ADCON register specify the

clock divisor value for the ADC clock generation logic.

The input to the ADC clock divisor is the system clock

(240 MHz @ 30 MIPS) when the PLL is operating. This

high-frequency clock provides the needed timing reso-

lution to generate a 24 MHz ADC clock signal required

to process two ADC conversions in 1 microsecond.

16.14 ADC Base Register

It is expected that the user application may have the

ADC module generate 500,000 interrupts per second.

To speed the evaluation of the PxRDY bits in the

ADSTAT register, the ADC module features the read/

write regis ter: ADBASE. Wh en read , th e ADBASE re g-

ister provides a sum of the contents of the ADBASE

ADSTAT register.

The Least Significant bit of the ADBASE register is

forced to zero, which ensures that all (ADBASE +

PxRDY) results are on instruction boundaries.

The PxRDY b it s are b ina ry pr iori ty e nc ode d; P0RD Y i s

the highest priority and P5RDY is the lowest priority.

The encoded priority result is shifted left two bit posi-

tions and added to the contents of the ADBASE regis-

ter. Thus the priority encoding yields addresses that

are on two instruction word boundaries.

The user will typically load the ADBASE register with

the base address of a “J ump ” table that contains either

the addresses of the appropriate ISRs or branches to

the appropriate ISR. The encoded PxRDY values are

set up to reserve two instruction words per entry in the

Jump table. It is expected that the user software will

use one instruction word to load an identifier into a W

the appropriate ISR.

Note: The ADC module will NOT repeatedly loop

once triggered. Each sequence of

conversions requires a trigger or multiple

triggers.

dsPIC30F1010/202X

Example 16-1 shows a code sequence for using the

ADBASE register to implement ADC Input Pair Inter-

rupt Handling. When the ADBASE register is read, it

cont ains th e sum of the bas e addre ss of th e jump tabl e

and the encoded ADC channel pair number left shifted

by 2 bits.

For example, if ADBASE is initialized with a value of

0x0360, a channel pair 1 interrupt would cause an

ADBASE read value of 0x0364 (0x360 +

0b00000100). A channel pair 3 interrupt would cause

an ADBASE read value of 0x036C (0x360 +

0b00001100).

EXAMPLE 16-1: ADC BASE REGISTER CODE

; Initialize and enable the ADC interrupt

MOV #handle(JMP_TBL),W0 ; Load the base address of the ISR Jump

MOV WO, ADBASE ; table in ADBASE.

BSET IPC2,#12 ; Set up the interrupt priority

BSET IPC2,#13

BSET IPC2,#14

BCLR IFS0,#11 ; Clear any pending interrupts

BCLR ADSTAT ; Clear the ADC pair interrupts as well

BSET IEC0,#11 ; Enable the interrupt

; Code to Initialize the rest of the ADC registers

...

; ADC Interrupt Handler

__ADCInterrupt:

PUSH.S ; Save WO-W3 and SR registers

BCLR IFSO,#11 ; Clear the interrupt

MOV ADBASE, W0 ; ADBASE contains the encoded jump address

GOTO W0 ; within JMP_TBL

; Here's the Jump Table

; Note: It is important to clear the individual IRQ flags in the ADC AFTER the IRQ flags

in the interrupt controller. Failure to do so may cause interrupt requests to be lost

JMP_TBL:

BCLR ADSTAT,#0 ; Clear the IRQ flag in the ADC

BRA ADC_PAIR0_PROC ; Actual Pair 0 Conversion Interrupt Handler

BCLR ADSTAT,#1 ; Clear the IRQ flag in the ADC

BRA ADC_PAIR1_PROC ; Actual Pair 1 Conversion Interrupt Handler

BCLR ADSTAT,#2 ; Clear the IRQ flag in the ADC

BRA ADC_PAIR2_PROC ; Actual Pair 2 Conversion Interrupt Handler

BCLR ADSTAT,#3 ; Clear the IRQ flag in the ADC

BRA ADC_PAIR3_PROC ; Actual Pair 3 Conversion Interrupt Handler

BCLR ADSTAT,#4 ; Clear the IRQ flag in the ADC

BRA ADC_PAIR4_PROC ; Actual Pair 4 Conversion Interrupt Handler

dsPIC30F1010/202X

EXAMPLE 16-1: ADC BASE REGISTER CODE (CONTINUED)

16.15 Changing A/D Clock

In genera l, the ADC ca nnot accept c hanges to th e ADC

clock d ivisor whi le ADON = 1. If the user makes A/D

clock changes while ADON = 1, the results will be

indeterminate.

16.16 Sample and Conversion

The ADC module always assigns two ADC clock peri-

ods for the sampling process. When operating at the

maximum conversion rate of 2 Msps per channel, the

sampling period is:

2 x 41.6 nsec = 83.3 nsec.

Each ADC pair specified in the ADCPCx registers ini-

tiates a sample operation when the selected trigger

event occurs. The conversion of the sampled analog

data occurs as resources become available.

If a new trigger event occurs for a specific channel

before a previous sample and convert request for that

channel has been processed, the newer request is

ignored. It is the user’s responsibility not to exceed the

conversion rate capability for the module.

The actual conversion process requires 10 additional

ADC cloc ks. The conve rsion i s proce ssed seriall y, bit 9

first, then bit 8, down to bit 0. The re sul t i s st ored whe n

the conversion is completed.

; The actual pair conversion interrupt handler

; Don't forget to pop the stack when done and return from interrupt

ADC_PAIR0_PROC:

... ; The ADC pair 0 conversion complete handler

POP.S ; Restore W0-W3 and SR registers

RETFIE ; Return from Interrupt

ADC_PAIR1_PROC:

... ; The ADC pair 1 conversion complete handler

POP.S ; Restore W0-W3 and SR registers

RETFIE ; Return from Interrupt

ADC_PAIR2_PROC:

... ; The ADC pair 2 conversion complete handler

POP.S ; Restore W0-W3 and SR registers

RETFIE ; Return from Interrupt

ADC_PAIR3_PROC:

... ; The ADC pair 3 conversion complete handler

POP.S ; Restore W0-W3 and SR registers

RETFIE ; Return from Interrupt

ADC_PAIR4_PROC:

... ; The ADC pair 4 conversion complete handler

POP.S ; Restore W0-W3 and SR registers

RETFIE ; Return from Interrupt

ADC_PAIR5_PROC:

... ; The ADC pair 5 conversion complete handler

POP.S ; Restore W0-W3 and SR registers

RETFIE ; Return from Interrupt

dsPIC30F1010/202X

16.17 A/D Sample and Convert T iming

The samp le and ho ld circuit s assig ned to the inpu t pins

have their own timing logic that is triggered when an

external sample and convert request (from PWM or

TMR) is made. The sample and hold circuits have a

fixed two clock data sample period. When the sample

has been acquired, then the ADC control logic is noti-

fied of a pending requ es t, then the con ve r si on is

performed as the conversion resources become

available.

The ADC mo dule al ways conv erts p airs of analog inp ut

chann els, s o a ty pical co nvers ion pr oces s requi res 24

clock cycles.

FIGURE 16-3: DETAILED CONVERSION SEQU ENCE TIMINGS, SEQSAMP = 0, NOT BUSY

10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st

TAD

adc_clk

sample_even

convert_en

capture_first_data

10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0 1

0 1 2 3

connect_second

connect_first

state counter

capture_second_data

sample_odd

dsPIC30F1010/202X

FIGURE 16-4: DETAILED CONVERSION SEQU ENCE TIMINGS, SEQSAMP = 1

10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st

TAD

adc_clk

sample_even

convert_en

capture_first_data

10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 00 1 2 3

sample_odd(1)

connect_second

connectx_en

state counter

capture_second_data

connect_common

sample_odd(2)

Dependent on S&H availability

Note 1: For all analog input pairs that do not have dedicated sample and hold circuits, the common sample and hold circuit

samples the input at the start of the first and second conversions. Therefore, the s amples are sequential, not

simultaneous.

2: For all analog input p airs that have dedicated sample and hold circuits, the common sample and hold circuit samples

the input at the start of the first conversion so that both samples (odd and even) are near simultaneous.

dsPIC30F1010/202X

16.18 Module Power-Down Modes

The module has two internal power modes.

When the AD ON bit is ‘1’, the module is in Active mode

and is fully powered and functional.

When ADON is ‘0’, the module is in Of f mode. The state

machine for the module is reset, as are all of the

pending conversion requests.

To return to the Active mode from Off mode, the user

must wait for the bias generators to stabilize. The

stabilization time is specified in the electrical specs.

16.19 Effects of a Reset

A device Reset forces all registers to their Reset state.

This forces the ADC module to be turned off, and any

conversion and sampling sequence is aborted. The

value that is in the ADCBUFx register is not modified.

The ADCBUFx registers contain unknown data after a

Power-on Reset.

16.20 Configuring Analog Port Pins

The use of the ADPC FG and TRIS registers control the

operation of the A/D port pins.

The port pins that are desired as analog inputs should

have their corresponding TRIS bit set (input). If the

TRIS bi t is cleared (ou tput), the dig ital outp ut level (V OH

or VOL) will be converted.

Port pins that are desired as analog inputs must have

the corresponding ADPCFG bit clear. This will config-

ure the port to disable the digital input buffer. Analog

levels on pins where ADPCFG<n> = 1, may cause the

digit al input buffer to consum e exc essi ve curren t.

If a pin is not configured as an analog input

ADPCFG<n> = 1, the analog input is forced to AVss,

and conversions of that input do not yield meaningful

results.

When r eading the POR T regist er , all pins co nfigured as

analog input ADPCFG<n> = 0 will read ‘0’.

The A/D operation is independent of the state of the

input sele cti on bits and the TRIS bit s.

16.21 Outp ut Formats

The A/D converts 10 bits. The data buffer RAM is 16

bits wi de . The A DC da ta ca n be re a d in on e of t w o dif -

ferent form ats , as sh own in Fig ure 16-5. The FOR M bit

selects the format. Each of the output formats

translates to a 16-bit result on the data bus.

dsPIC30F1010/202X

FIGURE 16-5: A/D OUTPUT DATA FORMAT

RAM contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Read to Bus:

Fractional d09d08d07d06d05d04d03d02d01d0000000 0

Integer 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

dsPIC30F1010/202X

TABLE 16-1: ADC REGISTER MAP

File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

ADCON 0300 ADON —ADSIDL——GSWTRG— FORM EIE ORDER

SEQSAMP

—— ADCS<2:0> 0009

ADPCFG 0302 — — — —

PCFG11

PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

Reserved 0304 — — — — — — — — — — — — — — — — 0000

ADSTAT 0306 — — — — — — — — — — P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY 0000

ADBASE 0308 ADBASE<15:1> —0000

ADCPC0 030A

IRQEN1

PEND1 SWTRG1 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> 0000

ADCPC1 030C

IRQEN3

PEND3 SWTRG3 TRGSRC3<4:0> IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0> 0000

ADCPC2 030E

IRQEN5

PEND5 SWTRG5 TRGSRC5<4:0> IRQEN4 PEND4 SWTRG4 TRGSRC4<4:0> 0000

Reserved 0310

–

031E

—- — — — — — — — — — — — — — — — 0000

ADCBUF0 0320 — — — — — — ADC Data Buffer 0 xxxx

ADCBUF1 0322 — — — — — — ADC Data Buffer 1 xxxx

ADCBUF2 0324 — — — — — — ADC Data Buffer 2 xxxx

ADCBUF3 0326 — — — — — — ADC Data Buffer 3 xxxx

ADCBUF4 0328 — — — — — — ADC Data Buffer 4 xxxx

ADCBUF5 032A — — — — — — ADC Data Buffer 5 xxxx

ADCBUF6 032C — — — — — — ADC Data Buffer 6 xxxx

ADCBUF7 032E — — — — — — ADC Data Buffer 7 xxxx

ADCBUF8 0330 — — — — — — ADC Data Buffer 8 xxxx

ADCBUF9 0332 — — — — — — ADC Data Buffer 9 xxxx

ADCBUF10 0334 — — — — — — ADC Data Buffer 10 xxxx

ADCBUF11 0336 — — — — — — ADC Data Buffer 11 xxxx

Reserved 0338

– 037E — — — — — — — — — — — — — — — — 0000

dsPIC30F1010/202X

17.0 SMPS COMPARATOR MODULE

The dsPIC30F SMPS Comparator module monitors

current and/or voltage transients that may be too fast

for the CPU and ADC to capture.

17.1 Features Overview

• 16 comparator inputs

• 10-bit DAC provides reference

• Programmable output polarity

• Interrupt generation capability

• Selectable Input sources

• DAC has three ranges of operation:

-AV

DD / 2

- Internal Reference 1.2V 1%

- External Reference < (AVDD - 1.6V)

• ADC sample and convert trigger capability

• Can be disabled to reduce power consumption

• Functional support for PWM Module:

- PWM Duty Cyc le Control

- PWM Period Control

- PWM Fault Detect

FIGURE 17-1: COMPARATOR MODULE BLOCK DIAGRAM

17.2 Module Applications

This module provides a means for the SMPS dsPIC

DSC devices to monitor voltage and currents in a

power conversion application. The ability to detect

tran si e nt co nd i tio ns an d s ti mu l ate th e dsPI C D SC pro -

cessor and/or p eripherals without re quirin g the pro ces-

sor and ADC to c onsta ntly m onito r volt ages or cu rrent s

frees the dsPIC DSC to perform other tasks.

The Com p a rator module has a hig h-s pee d co mparator

and an associated 10-bit DAC that provides a pro-

grammable reference voltage to one input of the com-

parator. The polarity of the comparator output is user

programmable. The output of the module can be used

in the following modes:

• Generate an interrupt

• Trigger an ADC sample and convert process

• Truncate the PWM signal (current limit)

• Truncate the PWM period (current minimum)

• Disab le the PWM outputs (Fault-latch)

The output of the Comparator module may be used in

multiple modes at the same time, such as: (1) gener-

ate an interrupt, (2) have the ADC take a sample and

convert it and (3) truncate the PWM output in

response to a voltage being detected beyond its

expected value.

The Comparator module can also be used to wake-up

the system from Sleep or Idle mode when the analog

input voltage exceeds the programmed threshold

voltage.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

CMPxA*

CMPxC*

DAC

CMPPOL

AVDD/2

INTREF

AVSS

CMREF

CMP

RANGE

INSEL<1:0>

Trigger to PWM

Interrupt Request

CMPxB*

CMPxD*

Glitch Filter Pulse Generator

Status

EXTREF

* x=1, 2, 3 & 4

dsPIC30F1010/202X

17.3 Module Description

The Comparator module uses a 20 nsec comparator.

The comparator offset is ±5 mV typical. The negative

input of the comparator is always connected to the

DAC circuit. The positive input of the comparator is

connected to an analog multiplexer that selects the

des ired source pin.

17.4 DAC

The range of the DAC is controlled via an analog mul-

tiplexer that selects either AVDD/2, internal 1.2V 1%

reference, or an external reference source EXTREF.

The full range of the DAC (AVDD/2) will typically be

used when the chosen input source pin is shared with

the ADC. The reduced range option (INTREF) will

likely be used when monitoring current levels via a

CLx pin using a current sense resistor. Usually, the

measured voltages in such applications are small

(<1.25V), therefore the option of using a reduced ref-

erence range for the comparator extends the available

DAC resolution in these applications. The use of an

external reference enables the user to connect to a

reference that better suits their application.

17.5 Interaction with I/O Buff ers

If the comparator module is enabled and a pin has

been selected as the source for the comparator, then

the chos en I/O p a d m ust dis able the d igi tal input buffer

associated with the pad to prevent excessive currents

in the digital buffer due to analog input voltages.

17.6 Digital Logic

The CMPCONx register (see Register 17-1) provides

the control logic that configures the Comparator mod-

ule. The di gital logic provid es a gli tch filter for the com-

parator output to mask transient signals less than two

TCY (66 nsec) in duration. In Sleep or Idle mode, the

glitch filter is bypassed to enable an asynchronous

path from the comparator to the interrupt controller.

This asynchronous path can be used to wake-up the

processor from Sleep or Idle mode.

The comparator can be disabled while in Idle mode if

the CMPSIDL bit is set. If a device has multiple com-

parators, if any CMPSIDL bit is set, then the entire

group of comparators will be disabled while in Idle

mode. This behavior reduces complexity in the design

of the clock control logic for this module.

The digital logic also provides a one TCY width pulse

generator for triggering the ADC and generating

interrupt requests.

The CMPDACx (see Register 17-2) register provides

the digital input value to the reference DAC.

If the module is di sa ble d, th e D AC and comp arator are

disabled to reduce power consumption.

17.7 Comparator Input Range

The comparator has a limitation for the input Common

Mode Range (CMR) of about 3.5 volts (AVDD – 1.5

volts). This means that both inputs should not exceed

this value, or the comparator’s output will become

indeterminate. As long as one of the inputs is within

the C ommon M ode R ange, t he co mparator outpu t will

be correct. An input ex cu rsi on in to the C MR reg ion will

not corrupt the comparator output, but the comparator

input is saturated.

17.8 DAC Output Range

The DAC has a limitation for the maximum reference

voltage input of (AVDD - 1.6) volts. An external refer-

ence voltage input s ho uld not ex ceed this val ue o r the

reference DAC output will become indeterminate.

17.9 Comparator Registers

The Comparator module is controlled by the following

registers:

• Compara tor Contr ol Re gisterx (CMPCONx)

• Comparator DAC Control Registerx (CMPDACx)

dsPIC30F1010/202X

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

CMPON — CMPSIDL — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0

INSEL<1:0> EXTREF — CMPSTAT — CMPPOL RANGE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CMPON: A/D Operating Mode bit

1 = Comparator module is enabled

0 = Comparator module is disabled (reduces power consumption)

bit 14 Unimplemented: Read as ‘0’

bit 13 CMPSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode.

0 = Continue module operation in Idle mode.

If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables ALL comparators while in

Idle mode.

bit 12-8 Reserved: Read as ‘0’

bit 7-6 INSEL<1:0>: Input Source Select for Comparator bits

00 = Select CMPxA input pin

01 = Select CMPxB input pin

10 = Select CMPxC input pin

11 = Select CMPxD input pin

bit 5 EXTREF: Enable External Reference bit

1 = External source provides reference to DAC

0 = Internal reference sources provide source to DAC

bit 4 Reserved: Read as ‘0’

bit 3 CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit

bit 2 Reserved: Read as ‘0’

bit 1 CMPPOL: Comparator Output Polarity Control bit

1 = Output is inverted

0 = Output is non inverted

bit 0 RANGE: Selects DAC Output Voltage Range bit

1 = High Range: Max DAC value = AVDD / 2, 2.5V @ 5 volt VDD

0 = Low Range: Max DAC val ue = IN TREF, 1.2V ±1%

dsPIC30F1010/202X

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — —CMREF<9:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CMREF<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-10 Reserved: Read as ‘0’

These bits are reserved for possible future expansion of the DAC from 10 bits to more bits.

bit 9-0 CMREF<9:0>: Comp arator Reference Voltage Select bits

1111111111 = (CMREF * INTREF/102 4) or (CMREF * (AVDD/2)/10 24) vo lt s dependi ng on Ran ge bi t

·····

0000000000 = 0.0 v o lts

dsPIC30F1010/202X

TABLE 17-1: ANALOG COMPARATOR CONTROL REGISTER MAP

File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

CMPCON1 04C0 CMPON —CMPSIDL — — — — — INSEL<1:0> EXTREF —CMPSTAT —CMPPOL RANGE 0000

CMPDAC1 04C2 — — — — — — CMREF<9:0> 0000

CMPCON2 04C4 CMPON —CMPSIDL — — — — — INSEL<1:0> EXTREF —CMPSTAT —CMPPOL RANGE 0000

CMPDAC2 04C6 — — — — — — CMREF<9:0> 0000

CMPCON3 04C8 CMPON —CMPSIDL — — — — — INSEL<1:0> EXTREF —CMPSTAT —CMPPOL RANGE 0000

CMPDAC3 04CA — — — — — — CMREF<9:0> 0000

CMPCON4 04CC CMPON —CMPSIDL — — — — — INSEL<1:0> EXTREF —CMPSTAT —CMPPOL RANGE 0000

CMPDAC4 04CE — — — — — — CMREF<9:0> 0000

dsPIC30F1010/202X

NOTES:

dsPIC30F1010/202X

18.0 SYSTEM INTEGRATION

There are several features intended to maximize sys-

tem reliability, minimize cost through elimination of

external components, provide power-saving operating

modes and of fer code protecti on:

• Oscillator Selection

• Reset:

- Power-on Reset (P OR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT)

• Power-Saving modes (Sleep and Idle)

• Code Protection

• Unit ID Locations

• In-Circuit Serial Programming (ICSP)

programming capability

dsPIC30F devices have a Watchdog Timer, which can

be permanently enabled via the Configuration bits or

can be soft w are co ntro ll ed. It run s off its own RC os ci l-

lator f or added reliabilit y . Ther e are two timers that of fer

necessary delays on power-up. One is the Oscillator

Start-up Timer (OST), intended to keep the chip in

Reset until the crystal oscillator is stable. The other is

the Power-up Timer (PWRT), which provides a delay

on power-up only, designed to keep the part in Reset

mode w hile th e power supply stab ilizes. With thes e two

timers on-chip, most applications need no external

Reset circuitry.

Sleep mode is designed to offer a very low-current

Power-Down mode. The us er ca n wake -up fro m Slee p

mode through external Reset, Watchdog Timer Wake-

up or through an interrupt. Several oscillator options

are also made available to allow the part to fit a wide

variety of applications. In the Idle mode, the clock

sources are st ill a ctive , but the CP U is shut of f. The RC

oscillator opt ion saves system cost, while the LP cryst al

option saves power.

18.1 Oscillator System Overview

The dsPIC30F oscillator system has the following

modules and features:

• Various external and internal oscillator options as

clock sources

• An on-chip PLL to boost internal operating

frequency

• A clock switching mechanism between various

clock sources

• Programm abl e c loc k pos t s ca ler for system po w er

savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe meas ures

• Clock Control register OSCCON

• Configuration bits for main oscillator selection

Configuration bits determine the clock source upon

Power-on Reset (POR). Thereafter, the clock source

can be changed between permissible clock sources.

The OSC CON re gister c ontrols th e clock swit ching an d

reflects system clock related status bits.

A simplified diagram of the oscillator system is shown

in Figure 18-1.

18.2 Oscillator Control Registers

The oscillators are controlled with these registers:

• OSCCON: Oscillat or Control Register

• OSCTUN2: Oscillator Tuning Register 2

• LFSR: Linear Feedback Shift Register

• FOSCSEL: Oscillator Selection Configuration Bits

• FOSC: Osci lla tor Selection C onfi gu ratio n Bit s

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

For more information on the device instruction set and pro-

gramming, refer to the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157).

Note: 32 kHz crystal operation is not enabled on

dsPIC30F1010/202X devices.

dsPIC30F1010/202X

FIGURE 18-1: OSCILLATOR SYSTEM BLOCK DIAGRAM

Primary

OSC1

OSC2 Oscillator

Clock

and Control

Block

Switching

x32

PLL

Primary

Oscillator

Stability Detector

Oscillator

Start-up

Timer

Fail-Safe Clock

Monitor (FSCM )

Internal Fast RC

Oscillator (FRC)

Internal

Low-Power RC

Oscillator (LPRC)

PWRSAV Instruction

Wake-up Request

Oscillator Configuration Bits

System Cl ock FCY

Oscillator Trap

POR Done

Primary Osc

FPLL

FCKSM<1:0> 2

PLL Lock

COSC<2:0>

NOSC<2:0>

OSWEN

TUN<3:0>

FPWM

Clock Dither

Circuit

x16

dsPIC30F1010/202X

U-0 R-y

HS,HC R-y

HS,HC U-0 R/W-y R/W-y R/W-y

—COSC<2:0>—NOSC<2:0>

bit 15 bit 8

R/W-0 U-0 R-0

HS,HC R/W-0 R/C-0

HS,HC R/W-0 U-0 R/W-0

CLKLOCK — LOCK PRCDEN CF TSEQEN — OSWEN

bit 7 bit 0

Legend: x = Bit is unknown

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR

HC = Cleared by hardware ‘1’ = Bit is set

HS = Set by hardware ‘0’ = Bit is cleared

-y = Value set from Configuration bits on POR

bit 15 Unimplemented: Read as ‘0’

bit 14-12 COSC<2:0>: Current Oscillator Group Selection bits (read-only)

000 = Fast RC Oscillator (FRC)

001 = Fast RC Oscillator (FRC) with PLL Module

010 = Primary Oscillator (HS, EC)

011 = Primary Oscillator (HS, EC) with PLL Module

100 = Reserved

101 = Reserved

110 = Reserved

111 = Reserved

This bit is Reset upon:

Set to FRC value (‘000’) on POR

Loaded with NOSC<2:0> at the completion of a successful clock switch

Set to FRC value (‘000’) when FSCM detects a failure and switches clock to FRC

bit 11 Unimplemented: Read as ‘0’

bit 10-8 NOSC<2:0>: New Oscillator Group Selection bits

000 = Fast RC Oscillator (FRC)

001 = Fast RC Oscillator (FRC) with PLL Module

010 = Primary Oscillator (HS, EC)

011 = Primary Oscillator (HS, EC) with PLL Module

100 = Reserved

101 = Reserved

110 = Reserved

111 = Reserved

bit 7 CLKLOCK: Clock Lock Enab led bit

1 = If (FCKSM1 = 1), then clock and PLL configurations are locked

If (FCKSM1 = 0), then clock and PLL configurations may be modified

0 = Clock and PLL selection are not locked, configurations may be modified

Note: Once set, this bit can only be cleared via a Reset.

bit 6 Unimplemented: Read as ‘0’

dsPIC30F1010/202X

bit 5 LOCK: PLL Lock Sta tus bit (read-o nly)

1 = Indicates that PLL is in lock

0 = Indicates that PLL is out of lock (or disabled)

This bit is Reset upon:

Reset on POR

Reset when a valid clock switching sequence is initiated by the clock switch state machine

Set when PLL lock is achieved after a PLL start

Reset when lock is lost

Read zero when PLL is not selected as a Group 1 system clock

bit 4 PRCDEN: Pseudo Random Clock Dither Enable bit

1 = Pseudo random clock dither is enabled

0 = Pseudo random clock dither is disabled

bit 3 CF: Clock Fail Detect bit (read/clearable by application)

1 = FSCM has detected clock failure

0 = FSCM has NOT detected clock failure

This bit is Reset upon:

Reset on POR

Reset when a valid clock switching sequence is initiated by the clock switch state machine

Set when clock fail detected

bit 2 TSEQEN: FRC Tune Sequencer Enable bit

1 = The TUN<3:0>, TSEQ1<3:0>, ... , TSEQ7<3:0> bits in the OSCTUN and the OSCTUN2 regis-

ters sequentially tune the FRC oscillator. Each field being sequentially selected via the

ROLL<2:0> signals from the PWM module.

0 = The TUN<3:0> bits in OSCTUN register tunes the FRC oscillator

bit 1 Unimplemented: Read as ‘0’

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Request oscillator switch to selection specified by NOSC<1:0> bits

0 = Oscillator switch is complete

This bit is Reset upon:

Reset on POR

Reset after a successful clock switch

Reset after a redundant clock switch

Reset after FSCM switches the oscillator to (Group 3) FRC

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TSEQ3<3:0> TSEQ2<3:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TSEQ1<3:0> TUN<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 TSEQ3<3:0>: Tune Sequence Value #3 bits

When PWM ROLL<2:0> = 011, this field is used to tune the FRC instead of TUN<3:0>

bit 11-8 TSEQ2<3:0>: Tune Sequence Value #2 bits

When PWM ROLL<2:0> = 010, this field is used to tune the FRC instead of TUN<3:0>

bit 7-4 TSEQ1<3:0>: Tune Sequence Value #1 bits

When PWM ROLL<2:0> = 001, this field is used to tune the FRC instead of TUN<3:0>

bit 3-0 TUN<3:0>: Specifies the user tuning capability for the internal fast RC oscillator . If the TSEQEN bit

in the OSC CON registe r is set, thi s field, along with bit s TSEQ1-TSEQ 7, will sequ entially tune the

FRC oscillator.

0111 = Maximu m frequency

0110 =

0101 =

0100 =

0011 =

0010 =

0001 =

0000 = Center frequency, oscillator is running at calibrated frequency

1111 =

1110 =

1101 =

1100 =

1011 =

1010 =

1001 =

1000 = Minimum fre quenc y

dsPIC30F1010/202X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TSEQ7<3:0> TSEQ6<3:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TSEQ5<3:0> TSEQ4<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 TSEQ7<3:0>: Tune Sequence value #7 bits

When PWM ROLL<2:0> = 111, this field is used to tune the FRC instead of TUN<3:0>

bit 11-8 TSEQ6<3:0>: Tune Sequence value #6 bits

When PWM ROLL<2:0> = 110, this field is used to tune the FRC instead of TUN<3:0>

bit 7-4 TSEQ5<3:0>: Tune Sequence value #5 bits

When PWM ROLL<2:0> = 101, this field is used to tune the FRC instead of TUN<3:0>

bit 3-0 TSEQ4<3:0>: Tune Sequence value #4 bits

When PWM ROLL<2:0> = 100, this field is used to tune the FRC instead of TUN<3:0>

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—LFSR<14:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LFSR<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

When PWM ROLL<2:0> = 111, this field is used to tune the FRC instead of TUN<3:0>

bit 14-8 LFSR <14:8>: Most Significant 7 bits of the pseudo random FRC trim value bits

bit 7-0 LFSR <7:0>: Least Significant 8 bits of the pseudo random FRC trim value bits

dsPIC30F1010/202X

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/P R/P

— — — — — — FNOSC1 FNOSC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 23-2 Unimplemented: Read as ‘0’

bit 1-0 FNOSC<1:0>: Initial Oscillator Group Selection on POR bits

00 = Fast RC Oscillator (FRC)

01 = Fast RC Oscillator (FRC) divided by N, with PLL module

10 = Primary Oscillator (HS,EC)

11 = Primary Oscillator (HS,EC) with PLL module

dsPIC30F1010/202X

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/P R/P R/P U-0 U-0 R/P R/P R/P

FCKSM<1:0> FRANGE —— OSCIOFNC POSCMD<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 23-8 Unimplemented: Read as ‘0’

bit 7-6 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits

1x = Clock switching is disabled, fail-safe clock monitor is disabled

01 = Clock switching is enabled, fail-safe clock monitor is disabled

00 = Clock switching is enabled, fail-safe clock monitor is enabled

bit 5 FRANGE: Frequency Range Select for FRC and PLL bit

Acts like a “Gear Shift” feature that enables the dsPIC DSC device to operate at reduced MIPS at a

reduced supply voltage (3.3V)

FRANGE

Bit Value

Temperature

Rating FRC Frequency

(Nominal) PLL VCO

(Nominal)

1 = High Range Industrial

Extended 14.55 MHz

9.7 MHz 466 MHz (480 MHz max.)

310 MHz (320 MHz max.)

0 = Low Range Industrial

Extended 9.7 MHz

6.4 MHz 310 MHz (320 MHz max.)

205 MHz (211 MHz max.)

bit 4-3 Unimplemented: Read as ‘0’

bit 3 OSCIOFNC: OSC2 Pin I/O Enable bit

1 = CLKO output signal active on the OSCO pin

0 = CLKO output disabled

bit 1-0 POSCMD<1:0>: Primary Oscillator Mode

11 = Primary Oscillator Disabled

10 = HS oscillat or mode selected

01 = Reserved

00 = External clock mode selected

dsPIC30F1010/202X

18.2.1 ACCIDENTAL WRITE PROTECTION

Because the OSCCON register allows clock switching

and clock scaling, a write to OSCCON is intentionally

made difficult. To write to the OSCCON low byte, this

exact sequence must be executed without any other

instruc tions in betwe en:

• Byte Write “46h” to OSCCON low

• Byte Write “57h” to OSCCON low

• Byte Write is allowed for one instruction cycle

mov.b W0,OSCCON

To write to the OSCCON high byte, this exact

sequence must be executed without any other instruc-

tions in between:

• Byte Write “78h” to OSCCON high

• Byte Write “9Ah” to OSCCON high

• Byte Write is allowed for one instruction cycle

mov.b W0,OSCCON + 1

18.3 Oscillator Configurations

Figure 18-2 shows the derivation of the system clock

FCY. The PLL in Figure 18-1 outputs a maximum fre-

quency of 480MHz (high-range FRC option for

industrial temperature parts with PLL and TUN<3:0> =

0111 bit settings). This signal is used by the Power

Supply PW M modul e, and is 32 t imes the input PLL fre-

quency.

Assumi ng the h igh-ran ge F RC opti on is s elect ed on a n

industrial temperature rated part, the 480 MHz PLL

clock signal is divided by 2, providing a 240 MHz signal,

which drive s the ADC Mo dule. The same 480 M Hz si g-

nal is also divided by 8 to produce the 60 MHz signal,

which is one of the inputs to the FCY multiplexer. The

other input to this multiplexer is the FOSC input clock

source (either the Primary Oscillator or the FRC)

divide d by 2. W hen the PLL i s e na ble d, FCY = FPLL/16.

When the P LL is disabled, F CY = FOSC/2.

This method derives the 480 MHz clock:

• FRC Clock with high-range Option and TUN<3: 0>

= 0111 is = 15 MHz

• PLL enabled

• PW M clock = 15 x 32 = 480 MHz

•F

CY = 480 MHz/16 = 30 MHz = 30 MIPS

If the PLL is disabled ,

• FRC Clock (with high-range Option and

TUN<3:0> = 0111) is = 15 MHz

•FCY = 15 MHz/2 = 7.5 MHz = 7.5 MIPS

FIGURE 18-2: SYSTEM CLOCK AND FADC DERIVATION

Divide

By 2

Divide

By 2

Divide

By 8

FOSC

FRC

Primary Oscillator

Oscillator Configuration Bits

PLL – 192-480 MHZ24-60 MHZ

96-240 MHZ

FCY

PLL Enable

FADC

FPLL

dsPIC30F1010/202X

18.3.1 INITIAL CLOCK SOURCE

SELECTION

While coming out of a Power-on Reset, the device

selects its clock source based on:

a) FNOSC<1:0> Configuration bits that select one

of three oscillator groups (HS, EC or FRC)

b) POSCMD1<1:0> Configuration bits that select

the Prima r y Os ci lla tor Mo de

c) OSCIOFNC selects if the OSC2 pin is an I/O or

clock output

The selection is as shown in Table 18-1.

TABLE 18-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

18.3.2 OSCILLATOR START-UP TIMER

(OST)

In order to ensure that a crystal oscillator (or ceramic

resonator) has started and stabilized, an Oscillator

Start-up Timer is included. It is a simple 10-bit counter

that counts 1024 TOSC cycles before releasing the

oscil lator clock t o th e rest of the syste m. The t ime-ou t

period is designated as TOST. Th e TOST time is involve d

every time the oscillator has to restart (i.e., on POR and

wake-up from Sleep). The Oscillator Start-up Timer is

applied to the HS Oscillator mode (upon

wake-up from Sleep and POR) for the primary

oscillator.

18.3.3 PHASE LOCKED LOOP (PLL)

The PLL mul tiplies th e clock, w hich is gene rated by the

primary os ci llator. Th e PL L i s select abl e to have a gain

of x32 only. Input and output frequency ranges are

summa riz ed in Table 18-2.

TABLE 18-2: PLL FREQUENCY RANGE

The PLL fe atures a loc k output, which is asserted whe n

the PLL enters a phase locked state. Should the loop

fall out of lock (e.g. , due to no ise), the lock signal will b e

rescinded. The state of this signal is reflected in the

read-only LOCK bit in the OSCCON register.

Oscillator

Mode Oscillator

Source

FNOSC<1:0> POSCMD<1:0> OSCIOFNC OSC2

Function OSC1

Function

Bit 1 Bit 0 Bit 1 Bit 0

HS w/PLL 32x PLL 11 1 0 N/A CLKO(1) CLKI

FRC w/PLL 32x PLL 01 1 1 1 CLKO I/O

FRC w/PLL 32x PLL 01 1 1 0 I/O I/O

EC w/PLL 32x PLL 11 0 0 1 CLKO CLKI

EC w/PLL 32x PLL 11 0 0 0 I/O CLKI

EC(2) External 10 0 0 1 CLKO CLKI

EC(2) External 10 0 0 0 I/O CLKI

HS(2) External 10 1 0 N/A CLKO(1) CLKI

FRC(2) Internal RC 00 1 1 0 I/O I/O

FRC(2) Internal RC 00 1 1 1 CLKO I/O

Note 1: CLKO is not recommended to drive external circuits.

2: This mode is not recommended for some applications; disabling 32x PLL will not allow operation of

high-speed ADC and PWM.

FIN PLL

Multiplier FOUT

6.4 MHz x32 205 MHz

9.7 MHz x32 310 MHz

14.55 MHz x32 466 MH z

dsPIC30F1010/202X

18.4 PRIMARY OSCILLATOR ON OSC1/

OSC2 PINS:

The primary oscillator uses is shown in Figure 18-3.

FIGURE 18-3: PRIMARY OSCILLATOR

18.5 EXTERNAL CLOCK INPUT

Two of the primary Oscillator modes use an external

clock. These modes are EC and EC with IO.

In the EC mode (Figure 18-4), the OSC1 pin can be

driven by CMOS driv ers. In thi s m od e, t he OSC 1 p i n i s

high-impedance and the OSC2 pin is the clock output

(FOSC/2). This output clock is useful for testing or

synchronization purpose s .

In the EC with IO mode (Figure 18-5), the OSC1 pin

can be driven by CMOS drivers. In this mode, the

OSC1 pin is high-impedance and the OSC2 pin

becomes a general purpose I/O pin. The feedback

device between OSC1 and OSC2 is turned off to save

current.

FIGURE 18-4: EXTERNAL CLOCK INPUT OPERATION (EC OSCILLATOR CONFIGURATION)

FIGU RE 18-5: EXTERNAL CLOCK INPUT OPERATION (ECIO OSCILLATOR CONFIGURATION)

XTAL

OSC2/CLKO

Rs (1)

OSC1/CLKI

RF (2)

Note 1: A serie s resistor, Rs, may be requir ed for AT strip cut crystals .

2: The feedback resistor, RF, is typically in the range of 2 to 10 MΩ.

To CLKGEN

CLKO/RC15

OSC1

OSC2

FOSC/2

dsPIC30F

Clock from Ext Syst em

OSC1

I/O (OSC2)

I/O

dsPIC30F

Clock from Ext System

dsPIC30F1010/202X

18.6 INTERNAL FAST RC OSCILLATOR

(FRC)

FRC is a fast, precise frequency internal RC oscillator.

The F RC oscillator is desig ned to run at a fre quency of

6.4/9.7/14.55 MHz (<±2% accuracy). The FRC oscilla-

tor optio n is in tended to be ac c urat e e nough to pro vid e

the clock frequency necessary to maintain baud rate

tolerance for serial data transmissions. The user has

the ability to tune the FRC frequency by +-3%.

The FRC oscillator is powered:

a) Any time the EC or HS Oscillator modes are

NOT selected.

b) When the fail-safe clock monitor is enabled and

a clock fail is detected, forcing a switch to FRC.

18.6.1 FREQUENCY RANGE SELECTION

The FRC module has a “Gear Shift” control signal that

selects low range (9.7 MHz for industrial temperature

rated parts and 6.4 MHz for extended temperature

rated parts) or high range (14.55 MHz for industrial

temperture rated parts and 9.7 MHz for extended tem-

perature rated parts) frequency of operation. This fea-

ture enables a dsPIC DSC device to operate up to a

maiximum speed of 20 MIPS at 3.3V or up to a maxi-

mum speed of 30 MIPS at 5.0V and remain with

system specifications.

18.6.2 NOMINAL FREQUENCY VALUES

The FRC module is calibrated to a nominal 9.7 MHz

for industrial temperature rated parts and 6.4 MHz for

extended temperature rated parts in low range and

14.55 MHz for industrial temperture rated parts and

9.7 MHz for extended temperature rated parts in high

range This feature enables a user to “tune” the dsPIC

DSC device frequency of operation by +-3% and still

remain within system specifications.

18.6.3 FRC FREQUENCY USER TUNING

The FRC is calibrated at the factory to give a nominal

6.4/9.7/14.55 MHz. The TUN<3:0> field in the OSC-

TUN register is available to the user for trimming the

FRC oscillator frequency in applications.

The 4-bit tuning control signals are supplied by the

OSCTUN or the OSCTUN2 registers depending on

the TSEQEN bit in the OSCCON register.

The tuning range of the 14.55 MHz oscillator is

±0.45 MHz (±3%) nominal.

The base frequency can be tuned in the user's appli-

cation. This fre qu enc y tuning c apability al lows the us er

to deviate from the factory calibrated frequency. The

user can tune the fr equ enc y by wri t ing to th e O SC TUN

18.6.4 CLOCK DITHERING LOGIC

In power conversion applications, the primary electri-

cal nois e emis sion that the de signe rs wa nt to reduc e is

caused by the power transistors switching at the PWM

frequency. By changing the system clock frequency of

the SMPS dsPIC DSC, the resultant PWM frequency

will change and the peak EMI will be reduced at the

noise is spread over a wider frequency range.

Typically, the range of frequency variation is few

percent. The dsPIC30F1010/202X can provide two

ways to vary system clock frequency on a PWM cycle

basis. These are Frequency Sequencing mode and

Pseudo Random Clock Dithering mode. Table 18-8

shows the implementation details of both these

methods.

18.6.5 FREQUENCY SEQUENCING MODE

The Frequency Sequencing mode enables the PWM

module to select a sequence of eight different FRC

TUN values to vary the system frequency with each

rollover of the primary PWM time base. The OSCTUN

and the OSCTUN2 registers allow the user to specify

eight seq uentia l tune va lues if the TSEQ EN bit is set in

the OSCCON register. If the TSEQEN bit is zero, then

only the TUN bits affect the FRC frequency.

A 4-bit wide multiplexer with eight sets of inputs

selects the tuning value from the TUN and the TSEQx

bit fields. The multiplexer is controlled by the

ROLL<5:3> counter in the PWM module. The

ROLL<5:3> coun ter i nc rem ents every time the prim ar y

time base rolls over after reaching the period value.

18.6.6 PSEUDO RANDOM CLOCK

DITHERING MODE

The Pseudo Random Clock Dither (PRCD) logic is

implemented with a 15-bit LFSR (Linear Feedback

Shift Register), which is a shift register with a few

exclusive OR gates. The lower four bits of the LFSR

provides the FRC TUNE bits. The PRCD feature is

enabled by setting the PRCDEN bit in the OSCCON

once every time the ROLL<3> bit changes state,

which occurs once every 8 PWM cycles.

18.6.7 FAIL-SAFE CLOCK MONITOR

The Fail-Saf e Cl oc k Mo nito r (FSCM) all ow s the devic e

to conti nue to o pe rate eve n in th e even t of an oscil lator

failure. The FSC M f unc tio n i s e nab led by ap prop ria tel y

programming the FCKSM Configuration bits (Clock

Switch and Monitor Selection bits) in the FOSC

Configuration register.

In the event of an oscillator failure, the FSCM will

generate a clock failure trap event and will switch the

system clock over to the FRC oscillator. The user will

then have the option to either attempt to restart the

oscillator or execute a controlled shutdown. The user

may decide to treat the trap as a warm Reset by sim-

dsPIC30F1010/202X

ply loading the Reset address into the oscillator fail

trap vector. In this event, the CF (Clock Fail) status bit

(OSCCON<3>) is also set whenever a clock failure is

recognized.

In the event of a clock failure, the WDT is unaffected

and continues to run on the LPRC clock.

If the oscillator has a very slow start-up time coming

out of POR or Sle ep, it is possible that the PWRT timer

will expire before the oscillator has started. In such

cases, the FSCM will be activated and the FSCM will

initiate a clock failure trap, and the COSC<2:0> bits

are loaded with FRC oscillator selection. This will

effective ly shut of f th e orig ina l os ci lla tor th at was trying

to start.

The user may detect this situation and restart the

oscillator in the clock fail trap, ISR.

Upon a clock failure detection, the FSCM module will

initiate a clock switch to the FRC oscillator as follows:

1. The COSC bits (OSCCON<14:12>) are loaded

with the FRC oscillator selection value

2. CF bit is set (OSCCON<3>)

3. OSWEN control bit (OSCCON<0>) is cleared

For the purpose of clock switching, the clock sources

are sectioned into two gr oups:

1. Primary

2. Internal FRC

The user can switch between thes e functional groups,

but canno t switch between opt ions within a group. If the

primary group is selected, then the choice within the

group is always determined by the FNOSC<1:0>

Configuration bits.

The OSC CON register h olds the co ntrol and status bits

related to clock switching. If Configuration bits

FCKSM<1:0> = 1x, then the clock switching and Fail-

Safe Clock Monitor functions are disabled. This is the

default Configuration bit setting.

If clock switching is disabled, then the FNOSC<1:0>

and POSCMD<1:0> bits directly control the oscillator

selection and the COSC<2:0> bits do not control the

clock selection. However, these bits will reflect the

clock sour ce selection.

18.7 Reset

The PIC18F1220/1320 differentiates between

vari ous kinds of Reset:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during Sleep

d) Watchdog Timer (WDT) Reset (during normal

operation)

e) RESET Instruction

f) Reset cause by trap lock-up (TRAPR)

g) Reset caused by illegal opcode, or by using an

uninitialized W register as an Address Pointer

(IOPUWR)

Dif fer ent regi sters a re a ffe cted in dif fe rent w ays by var-

ious Reset conditions. Most registers are not affected

by a WD T wake-up, since this is viewed as the resump-

tion of normal operation. Status bits from the RCON

situations, as indicated in Table 18-3. These bits are

used in s oftwa re to dete rmi ne th e na ture of the Reset.

A block di agram of the on-ch ip Reset circuit is shown in

Figure 18-7.

A MCLR noise filter is provided in the MCLR Reset

path. The filter detects and ignores small pulses.

Internall y generated Res ets do not drive M CLR pin low.

Note: The application should not attempt to

switc h t o a cl ock fre quency l ow er tha n 100

KHz when the Fail-Safe Clock Monitor is

enabled. If clock switching is performed,

the device may generate an oscillator fail

trap and switch to the Fast RC oscillator.

dsPIC30F1010/202X

FIGURE 18-6: FRC TUNE DITHER LOGIC BLOCK DIAGRAM

FIGURE 18-7: RESET SYSTEM BLOCK DIAGRAM

CLK

TUN E B It s to F R C

All Zero Det e c t

TSEQEN in OSCCON

ROLL<3>

TSEQ7

DQ0

CLK Q

DQ1

CLK Q

DQ2

CLK Q

DQ3

CLK Q

DQ4

CLK Q

DQ5

CLK Q

DQ6

CLK Q

DQ7

CLK Q

DQ8

CLK Q

DQ9

CLK Q

DQ10

CLK Q

DQ11

CLK Q

DQ12

CLK Q

DQ13

CLK Q

DQ14

CLK Q

LFSR

PWM PS

TSEQ6 TSEQ5 TSEQ4

OSCTUN2

TSEQ3 TSEQ2 TSEQ1 TUN

OSCTUN

12 11

711

MUX

ROLL Counter

ROLL<5:3> ROLL<2:0>

MUX

Shift Ena b le for L F S R

PRCDEN in OSCCON

MCLR

VDD

VDD Rise

Detect POR

SYSRST

Sleep or Idle

WDT

Module

Digital

Glitch Filter

Trap Conflict

Illegal Opcode/

Uninitialized W Register

RESET Instructio n

dsPIC30F1010/202X

18.7.1 POR: POWER-O N RESE T

A power-on event will generate an internal POR pulse

when a VDD rise is detected. The Reset puls e will occur

at the POR circuit threshold voltage (VPOR), which is

nominally 1.85V. The device supply voltage character-

istics mus t meet spec ified sta rting v olt ag e and rise ra te

requirements. The POR pulse will reset a POR timer

and place the device in the Reset state. The POR also

selects the device clock source identified by the

oscillator configuration fuses.

The POR circuit inserts a small delay, TPOR, which is

nominally 10 μs and ensures that the device bias

circuit s are stable. Furthermore, a user selected po wer-

up time-out (TPWRT) is applied. The TPWRT par am e te r

is based on Configuration bits and can be 0 ms (no

delay), 4 ms, 16 ms or 64 ms. The total delay is at

device power-up TPOR + TPWRT. When these delays

have expired, SYSRST will be negated on the next

leading edge of the Q1 clock, and the PC will jump to

the Reset vector.

The timing for the SYSRST signal is shown in

Figure 18-8 through Figure 18-10.

FIGURE 18-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

FIGURE 18-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIE D TO VDD): CASE 1

TPWRT

TOST

VDD

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

MCLR

TPWRT

TOST

VDD

Internal POR

PWRT T ime-out

OST Time-out

Internal Reset

MCLR

dsPIC30F1010/202X

FIGURE 18-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

18.7.1.1 POR with Long Crystal Start-up Time

(with FSCM Enabled)

The osci ll ator s tart- up c ircuitry is not linked to the P OR

circuitry. Some crystal circuits (especially low

frequency crystals) will have a relatively long start-up

time. Th erefore, one or more of the foll owing condit ions

is possible after the POR timer and the PWRT have

expired:

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has NOT expired (if

a crystal oscillator is used) .

• The PLL has not achieved a L OCK (if PLL is

used).

If th e FSCM is enabled and one of th e above c onditions

is true, then a clock failure trap will occur. The device

will automatically switch to the FRC oscillator and the

user can switch to the desired crystal oscillator in the

trap, ISR.

18.7.1.2 Operating without FSCM and PWRT

If the FSCM is disabled and the Power-up Timer

(PWRT) is also disabled, then the device will exit rap-

idly fro m Reset o n power- up. If the clock sou rce is FRC

or EC, it will be active immediately.

If the FSCM is disabled and the system clock has not

start ed, the de vice w ill be in a frozen st ate at th e Res et

vector until the system clock starts. From the user’s

perspective, the device will appear to be in Reset until

a system clock is available.

FIGURE 18-11: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

TPWRT

TOST

Note: Dedicated supervisory devices, such as

the MCP1XX and MCP8XX, may also be

used as an external Power-on Reset

circuit.

Note 1: External Power-on Reset circuit is

requ ir ed on ly if the VDD power-up slope

is too s low . Th e dio de D help s dis charge

the c apacitor quickly when VDD powers

down.

2: R should be suitably chosen so as to

make sure that the voltage drop across

R does not vio late the devi ce’s electrical

specification.

3: R1 should be suitably chosen so as to

limit any curren t flo wing into MCL R from

external capacitor C, in the event of

MCLR/VPP pin breakdown due to Elec-

trostatic Discharge (ESD) or Electrical

Overstress (EOS).

VDD

dsPIC30F

MCLR

dsPIC30F1010/202X

Table 18-3 shows the Reset conditions for the RCON

are R/W , the information in the table implies that all the

bits are negated prior to the action specified in the

conditi on column.

TABLE 18-3: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1

Table 18-4 shows a second example of the bit

conditions for the RCON register. In this case, it is not

assu med th e use r has s et/ cle ared s peci fic bits pr ior to

action specified in the condition column.

TABLE 18-4: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2

Condition Program

Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR

Power-on Reset 0x000000 00000001

MCLR Reset during normal

operation 0x000000 00100000

Software Reset during

normal ope rati on 0x000000 00010000

MCLR Reset during Sleep 0x000000 00100010

MCLR Reset during Idle 0x000000 00100100

WDT Time-out Reset 0x000000 00001000

WDT Wake-up PC + 2 00001010

Interrupt Wake-up from

Sleep PC + 2(1) 00000010

Clock Failure Trap 0x000004 00000000

Trap Reset 0x000000 10000000

Illegal Operation Trap 0x000000 01000000

Note 1: When the wake-up is due to an enabled inte rrupt, the PC is load ed with the corres ponding in terrupt vector.

Condition Program

Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR

Power-on Reset 0x0000 00 0000000 1

MCLR Reset during normal

operation 0x000000 uu10000 u

Software Reset during

normal ope rati on 0x000000 uu01000 u

MCLR Reset during Sleep 0x000000 uu1u001 u

MCLR Reset during Idle 0x000000 uu1u010 u

WDT Time-out Reset 0x000000 uu00100 u

WDT Wake-up PC + 2 uuuu1u1 u

Interrupt Wake-up from

Sleep PC + 2(1) uuuuuu1 u

Clock Failure Trap 0x000004 uuuuuuu u

Trap Reset 0x000000 1uuuuuu u

Illegal Operation Reset 0x000000 u1uuuuu u

Legend: u = unchanged

Note 1: When the wake-up is due to an enab led interrup t, the PC is loade d with the corre sponding interrupt vector.

dsPIC30F1010/202X

18.8 Watchdog Timer (WDT)

18.8.1 WATCHDOG TIMER OPERATION

The primary function of the Watchdog Timer (WDT) is

to reset the processor in the event of a software

malfunction. The WDT is a free-running timer, which

runs off an on-chip RC oscillator, requiring no external

component. Therefore, the WDT timer will continue to

operate even if the main processor clock (e.g., the

crystal oscillator) fails.

18.8.2 ENABLING AND DISABLING THE

WDT

The Watchdog Timer can be “enabled” or “disabled”

only through a Configuration bit (FWDTEN) in the

Configuration register FWDT.

Setting FWDTEN = 1 enables the Watchdog Timer.

The enabling is done when programming the device.

By default, after chip-erase, FWDTEN bit = 1. Any

device programmer capable of programming

dsPIC30F devices allows programming of this and

other Configuration bits.

If enabled , the WDT will increment until it overflows or

“times out”. A WDT time-out will force a device Reset

(except during Sleep). To prevent a WDT time-out, the

user must clear the Watchdog Timer using a CLRWDT

instruction.

If a WDT times out during Sleep, the device will wake-

up. The WDT O bit in the RCO N register wil l be cleare d

to indicate a wake-up resulting from a WDT time-out.

Setting FWDTEN = 0 allows user software to enable/

disable the Watchdog Timer via the SWDTEN

(RCON<5>) control bit.

18.9 Power-Saving Modes

There are tw o powe r-savi ng state s that c an be en tered

through the execution o f a spe ci al ins tru cti on, PWRSAV.

These are: Sleep and Idle.

The format of the PWRSAV instructi on is as fol lows :

PWRSAV <parameter>, where ‘parameter’ defines

Idle or Sleep mode.

18.9.1 SLEEP MODE

In Sleep m ode, t he clo ck to t he CPU a nd peri pheral s is

shutdown. If an on-chip oscillator is being used, it is

shutdown.

The Fail-Safe Clock Monitor is not functional during

Sleep, since there is no clock to monitor. However,

LPRC clock remains active if WDT is operational during

Sleep.

The processor wakes up from Sleep if at least one of

the following conditions has occurred:

• any interrupt that is individually enabled and

meets the required priority level

• any Reset (POR and MCLR)

• WDT time-out

On waking up from Sleep mode, the processor will

restart the same clock that was active prior to entry

into Sleep mode. When clock switching is enabled,

bits COSC<2:0> will determine the oscillator source

that will be used on wake-up. If clock switch is

disabled, then there is onl y one sy ste m cl ock .

If the clock source is an oscillator, the clock to the

device is held off until OST times out (indicating a sta-

ble oscillator). If PLL is used, the system clock is held

off until LOCK = 1 (indicating that the PLL is stable).

Eith er way, T

POR

, T

LOCK

and T

PWRT

delays are applied

If EC, FRC, oscillators are used, then a delay of TPOR

(~10 μs) is applied. This is the smallest delay possible

on wake-up from Sleep.

Moreover, if LP oscillator was active during Sleep, and

LP is the oscillator used on wake-up, then the start-up

delay will be equal to TPOR. PWRT delay and OST

timer delay are not applied. In order to have the small-

est poss ible sta rt-up delay when waking up fro m Sleep,

one of these faste r wake-up optio ns shoul d be selecte d

before entering Sleep.

Any interrupt that is individually enabled (using the

corresponding IE bit) and meets the prevailing priority

level will be able to wake-up the processor. The proces-

sor will process the interrupt and branch to the ISR. The

Sleep status bit in the RCON register is set upon

wake-up

All Resets will wake-up the processor from Sleep

mode. Any Reset, other than POR, will set the Sleep

status bit. In a POR, the Sleep bit is cleared.

If Watchdog Timer is enabled, then the processor will

wake-up from Sleep mode upon WDT time-out. The

Sleep and WDTO status bits are both set.

Note: If a POR occurred, the selection of the

oscill ato r is bas ed on the FO SC <2:0 > an d

FOSCSEL<1:0> Configuration bits.

Note:

In spite of various delays applied (T

POR

LOCK

and T

PWRT

), the crystal oscillator

(and PLL) may not be active at the end of

the time-out (e.g., for low frequency crys-

tals). In such cases, if FSCM is enabled, the

devic e w ill dete ct this as a cloc k fa ilure a nd

process the clock failure trap, the FRC

oscillator will be enabled, and the user will

have to re-enable the crystal oscillator. If

FSCM is not enabled, then the device will

simply suspend exec utio n of code unt il th e

clock is stable, an d will rema in in Sle ep until

the osc illato r clo ck has st a r ted .

dsPIC30F1010/202X

18.9.2 IDLE MODE

In Idle mode, the clock to the CPU is shutdown while

periphera ls keep running. Unlike Sleep mode, the clock

sour ce rem ains active .

Several peripherals have a control bit in each module

that allows them to operate during Idle.

LPRC fail-safe clock remains active if clock failure

detect is enabled.

The processor wakes up from Idle if at least one of the

following conditions is true:

• on any interrupt that is individually enabled (IE bit

is ‘1’) and meets the required priority level

• on any Reset (POR, MCLR)

• on WDT time-out

Upon wake -up from Idle mode, the cloc k is reappli ed to

the CPU and inst ructio n executio n begin s imm ediate ly,

starting with the instruction following the PWRSAV

instruction.

Any interrupt that is individually enabled (using IE bit)

and meets the prevailing priority level will be able to

wake-u p th e p roc es sor. The process or wi ll p r oces s the

interrupt and branch to the ISR. The Idle status bit in

RCON register is set upon wake-up.

Any Reset, other than POR, will set the Idle status bit.

On a POR, the Idle bit is cleared.

If Watchdog Timer is enabled, then the processor will

wake-up from Idle mode upon WDT time-out. The Idle

and WDTO status bits are both set.

Unlike wake-up from Sleep, there are no time delays

involv ed in wake -up from Idle.

18.10 Device Configuration Registers

The Configuration bits in each device Configuration

prog ramme d by a de vice prog ra mmer, or b y us ing t he

In-Circuit Serial Programming (ICSP) feature of the

device. Each device Configuration register is a 24-b it

used to hold configuration data. There are six

Configuration registers available to the user:

1. FBS (0xF80000): Boot Code Segment

Configu ration Register

2. FGS (0xF80004): General Code Segment

Configu ration Register

3. FOSCEL (0xF80006): Oscillator Selection

Configu ration Register

4. FOSC (0xF80008): Oscillator Configuration

5. FWDT (0xF8000A): Watchdog Timer

Configu ration Register

6. FPOR (0xF8000C): Power-On Reset

Configu ration Register

The placement of the Configuration bits is automati-

cally ha ndled when you sel ect the device in your device

programmer . The desired st ate of the Configuration bits

may be sp ecified i n the source code (depen dent on the

language tool used), or through the programming

interface. After the device has been programmed, the

application software may read the Configuration bit

values through the table read instructions. For addi-

tional information, please refer to the programming

specifications of the device.

Table 18-5 shows the bit descriptions of the FGS and

FBS registers for the dsPIC30F1010. Table 18-6

shows the bit descriptions of the FGS and FBS regis-

ters for dsPIC30F202x devices. Table 18-7 shows the

bit descriptions of FWDT and the FPOR registers for

dsPIC30F1010/202X devices.

Note: If the code protection configuration fuse

bits (GSS<1:0> and GWRP in the FGS

erase of the entire code-protected device

is only possible at voltages VDD ≥ 4.5V.

dsPIC30F1010/202X

TABLE 18-5: FGS AND FBS BIT DESCRIPTIONS FOR THE dsPIC30F1010

Bit Field Register Description

BWRP FBS Boot Segment Program Flash Write Protection

1 = Boot segment may be written

0 = Boot segment is write-protected

BSS<2:0> FBS Boot Segment Program Flash Code Protection Size

x11 = No boot program Flash segment

x00 = No boot program Flash segment

x01 = No boot program Flash segment

110 = Standard security; small boot segment; boot program Flash seg-

ment starts at the end of the Interrupt Vector Segment and ends

at 0003FFH

010 = High security ; small boot segment; boot pro gram Flash s egment

starts at the end of the Interrupt Vector Segment and ends at

0003FFH

GRWP FGS General Segment Program Flash Write Protection

1 = General segment may be written

0 = General segme nt is w rite - prot ect ed

GSS<1:0> FGS General Segment Program Flash Code Protection

11 = No Protection

10 = Standard security; general program Flash segment starts at the

end of the boot segment and ends at the end of program Flash

0x = Reserved

TABLE 18-6: FGS AND FBS BIT DESCRIPTIONS FOR THE dsPIC30F202X

Bit Field Register Description

BWRP FBS Boot Segment Program Flash Write Protection

1 = Boot segment may be written

0 = Boot segment is write-protected

BSS<2:0> FBS Boot Segment Program Flash Code Protection Size

x11 = No boot program Flash segment

x00 = No boot program Flash segment

110 = Standard security; small boot segment; boot program Flash seg-

ment st art s at the end of th e Int errup t Vector Segment and e nd s

at 0003FFH

010 = High security ; small boot segment; boot pro gram Flash s egment

starts at the end of the Interrupt Vector Segment and ends at

0003FFH

101 = Standard security; medium boot segment; boot program Flash

segment starts at the end of the Interrupt Vector Segment and

ends at 000FFFH

001 = High security; medium boot segment; boot program Flash seg-

ment st art s at the end of th e Int errup t Vector Segment and e nd s

at 000FFFH

GWRP FGS General Segment Program Flash Write Protection

1 = General segment may be written

0 = General segme nt is w rite - prot ect ed

GSS<1:0> FGS General Segment Program Flash Code Protection

11 = No Protection

10 = Standard security; general program Flash segment starts at the

end of the Boot Segment and ends at the end of program Flash

0x = Reserved

dsPIC30F1010/202X

18.11 In-Circuit Debugger

When MPLAB® ICD 2 is selected as a debugger, the

in-circuit debugging functionality is enabled. This func-

tion al lows simple debug ging functi ons whe n use d wi th

MPLAB IDE. When the device has thi s feature enable d,

some of the resources are not available for general

use. These resources include the first 80 bytes of data

RAM and two I/O pins.

One of four pairs of Debug I/O pins may be selected by

the user using configuration options in MPLAB IDE.

These pin pairs are named EMUD/EMUC, EMUD1/

EMUC1 and EMUD2/EM UC2.

In each c as e, th e se le cte d EM UD p in i s th e Emulation/

Debug Data line, and the EMUC pin is the Emulation/

Debug Clock line. These pins will interface to the

MPLAB ICD 2 module available from Microchip. The

selected pair of Debug I/O pins is used by

MPLAB ICD 2 to send commands and receive

respons es, as well as to sen d and rec eive data . To use

the in-circuit debugging function of the device, the

design must implement ICSP connections to MCLR,

VDD, VSS, PGC , PGD and the selected

EMUDx/EMUCx pin pair.

This gives rise to two possibilities:

1. If EMUD/EMUC is selected as the debug I/O pi n

pair, then only a 5-pin interface is required, as

the EMUD and EMUC pin functions are multi-

plexed with the PGD and PGC pin functions in

all dsPIC30F devices.

2. If EMUD1/EMUC1 or EMUD2/EMUC2 is

selected as the debug I/O pin pair, then a 7-pin

interfac e i s re qui red , as th e EM UD x/E MUC x pi n

function s (x = 1 or 2) are not m ultiplexed with the

PGD and PGC pin functions.

TABLE 18-7: FWDT AND FPOR BIT DESCRIPTIONS FOR dsPIC30F1010/202X

Bit Field Register Description

FWDTEN FWDT Watch dog T im er Enab le bit

1 = Watchdog Timer always enabled. (LPRC oscillator cannot be dis-

abled. C lea ring the SWDT EN b it i n the RC ON re gis te r w ill hav e n o

effect.)

0 = Watchdog Timer enabled/disabled by user software (LPRC can be

disabled by clearing the SWDTEN bit in the RCON register)

WWDTEN FWDT Watchdog Timer Window Enable bit

1 = Watchdog Timer in Non-Window mode

0 = Watchdog Timer in Window mode

WDTPRE FWDT Watchdog Timer Prescaler bit

1 = 1:128

0 = 1:32

WDTPOST<3:0> FWDT Watchdog Timer Postscaler bits

1111 = 1:32, 768

1110 = 1:16, 384

0001 = 1:2

0000 = 1:1

FPWRT<2:0> FPOR Power-on Reset Timer Value Select bits

111 = PWRT = 128 ms

110 = PWRT = 64 ms

101 = PWRT = 32 ms

100 = PWRT = 16 ms

011 = PWRT = 8 ms

010 = PWRT = 4 ms

001 = PWRT = 2 ms

000 = PWRT = Disabled

dsPIC30F1010/202X

TABLE 18-8: SYSTEM INTEGRATION REGISTER MAP FOR dsPIC30F202X

SFR

Name Addr

.Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

RCON 0740 TRAPR IOPUWR — — — — — — EXTR SWR SWDTEN WDTO SLEEP IDLE — POR Depends on type of Reset.

OSCCON 0742 — COSC<2:0> — NOSC<2:0> CLKLOCK — LOCK PRCDEN CF TSEQEN — OS WEN Depends on Configuration bits.

OSCTUN 0748 TSEQ3<3:0> TSEQ2<3:0> TSEQ1<3:0> TUN<3:0>

0000 0000 0000 0000

OSCTUN2 074A TSEQ7<3:0> TSEQ6<3:0> TSEQ5<3:0> TSEQ4<3:0>

0000 0000 0000 0000

LFSR 074C —LFSR<14:0>

0000 0000 0000 0000

PMD1 0770 ——T3MDT2MDT1MD — PWMMD —I2CMD—U1MD — SPI1MD ——ADCMD

0000 0000 0000 0000

PMD2 0772 — — — — — — —IC1MD — — — — — —OC2MDOC1MD

0000 0000 0000 0000

PMD3 0774 — — — — CMP_PSMD — — — — — — — — — — —

0000 0000 0000 0000

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

TABLE 18-9: DEVICE CONFIGURATION REGISTER MAP

File Name Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FBS F80000 — — — — — — — — — — — — — BSS<2:0> BWRP

FGS F80004 — — — — — — — — — — — — — — GSS1 GSS0 GWRP

FOSCSEL F80006 — — — — — — — — — — — — — — —FNOSC<1:0>

FOSC F80008 — — — — — — — — — FCKSM<1:0> FRANGE — —

OSCIOFNC

POSCMD<1:0>

FWDT F8000A — — — — — — — — — FWDTEN WWDTEN —

WDTPRE

WDTPOST<3:0>

FPOR F8000C — — — — — — — — — — — — — —FPWRT<2:0>

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F1010/202X

19.0 INSTRUCTION SET SUMMARY

The dsPIC30F instruction set adds many

enhancements to the previous PIC® MCU instruction

sets, while maintaining an easy migration from PIC

MCU instruction sets.

Most instructions are a single program memory word

(24 bits). Only three instructions require two program

memory locations.

Each single-word instruction is a 24-bit word divided

into an 8-bit opcode which specifies the instruction

type, and one or more operands which further specify

the operation of the instruction.

The instruction set is highly orthog onal and is grouped

into five bas ic ca tego ries:

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• DSP operations

• Control operations

Table 19-1 shows the general symbols used in

des c ribing t he instructions.

The dsPIC30F instruction set summary in Table 19-2

lists all the instructions along with the status flags

affected by each instruction.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The first source operand, which is typically a

• The second source operand, which is t ypically a

• The destination of the result, which is typically a

However , word or byte-ori ented file register instructions

have two operands:

• The file register specified by the value ‘f’

• The destination, which could either be the file

‘WREG’

Most bit-oriented instructions (including simple rotate/

shift instructions) have two operands:

• The W register (with or without an address modi-

fier) or file register (specified by the value of ‘Ws’

or ‘f’)

• The bit in the W register or file register

(specified by a literal value, or indirectly by the

contents of register ‘Wb’)

The litera l instruct ions that invo lve data m ovement ma y

use some of the following operands:

• A lite ral value to be lo aded i nto a W regi ster or file

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

• The first source operand, which is a register ‘Wb’

without any addre s s modifier

• The second source operand, which is a literal

value

• The dest ination of the result (only if not the same

as the first source operand), which is typically a

The MAC class of DSP instruct ions may use some of the

following operands:

• The accumulator (A or B) to be used (required

operand)

• The W regis ters t o be used as the two operands

• The X and Y address space prefetch operations

• The X and Y address space prefetch destinations

• The accum ula tor wr ite bac k destination

The other DSP instructions do not involve any

multipl ic ati on, and may include:

• The accumul ator to be used (requ ired )

• The source o r destin ation ope rand (des ignated as

Wso or Wdo, respectively) with or without an

address modifier

• The amount of shift, specified by a W register

‘Wn’ or a literal value

The control instructions may use some of the following

operands:

• A program memory address

• The mode of the Table Read and Table Write

instructions

All instructions are a single word, except for certain

double word instructions, which were made double

word instructions so that all the required information is

available in these 48 bits. In the second word, the

8MSbs are ‘0’s. I f t hi s se cond w o rd i s ex ec ut e d as an

instruction (by itself), it will execute as a NOP.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

dsPIC30F1010/202X

Most single-word instructions are executed in a single

instruc tion cyc le , u nle ss a conditio nal test is tru e o r th e

Program Counter is changed as a result of the instruc-

tion. In these cases, the executio n takes tw o instructio n

cycles with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-

tional/computed branch), indirect CALL/GOTO, all

Table Reads and W rites and RETURN/RETFIE instru c-

tions, which are single-word instructions, but take two

or three cycles. Certain instructions that involve

skippi ng over the subs equent in struction , require e ither

two or three cycles if the skip is performed, depending

on whether the instruction being skipped is a single-

word or two-word instruction. Moreover, double word

moves require two cycles. The double word

ins truct ions execute in two instructi on cycles.

Note: For more details on the instruction set,

refer to the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157).

TABLE 19-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description

#text Me ans literal defined by “text”

(text) Mean s “content of text”

[text] Means “the location addressed by text”

{ } Optional field or operation

<n:m> Register bit field

.b Byte mode selection

.d Double Word mode selection

.S Shadow register select

.w Word mode selection (default)

Acc One of two accumulators {A, B}

AWB Accumula tor writ e back des tin ation addres s regis te r ∈ {W13, [W13] + = 2}

bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15}

C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Zero

Expr Absolute address, label or expression (resolved by the linker)

fFile register address ∈ {0x0000...0x1FFF}

lit1 1-bit unsigned literal ∈ {0,1}

lit4 4-bit unsigned literal ∈ {0...15}

lit5 5-bit unsigned literal ∈ {0...31}

lit8 8-bit unsigned literal ∈ {0...255}

lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode

lit14 14-bit unsigned literal ∈ {0...16384}

lit16 16-bit unsigned literal ∈ {0...65535}

lit23 23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’

None Field does not require an entry, may be blank

OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate

PC Program Counter

Slit10 10-bit signed literal ∈ {-512...511}

Slit16 16-bit signed literal ∈ {-32768...32767}

Slit6 6-bit signed literal ∈ {-16...16}

dsPIC30F1010/202X

Wb Base W register ∈ {W0..W15}

Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo Destination W register ∈

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn Dividend, Divisor working register pair (direct addressing)

Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈

{W4 * W4,W5 * W5,W6 * W6,W7 * W7}

Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈

{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}

Wn One of 16 working registers ∈ {W0..W15}

Wnd One of 16 destination working registers ∈ {W0..W15}

Wns One of 16 source working registers ∈ {W0..W15}

WREG W0 (working register used in file register instructions)

Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Wso Source W register ∈

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

Wx X data space prefetch address register for DSP instructions

∈ {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] – = 6, [W8] – = 4, [W8] – = 2,

[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] – = 6, [W9] – = 4, [W9] – = 2,

[W9 + W12],none}

Wxd X data space prefetch destination register for DSP instructions ∈ {W4..W7}

Wy Y data space prefetch address register for DSP instructions

∈ {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,

[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] – = 6, [W11] – = 4, [W11] – = 2,

[W11 + W12], none}

Wyd Y data space prefetch destination register for DSP instructions ∈ {W4..W7}

TABLE 19-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)

Field Description

dsPIC30F1010/202X

TABLE 19-2: INSTRUCTION SET OVERVIEW

Base

Instr

Assembly

Mnemonic Assemb ly Sy ntax Desc ri pt ion # of

word

# of

cycles Status Flags

Affected

1ADD ADD Acc Add Accumulators 1 1 OA,OB, SA,S B

ADD f f = f + WREG 1 1 C,DC,N,OV,Z

ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z

ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z

ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z

ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z

ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB

2ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z

3AND AND f f = f .AND. WREG 1 1 N,Z

AND f,WREG WREG = f .AND. WREG 1 1 N,Z

AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z

AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z

AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z

4ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z

ASR Wb,Wns,Wnd Wnd = Ari thmetic Right Shift Wb by Wns 1 1 N,Z

ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z

5BCLR BCLR f,#bit4 Bit Clear f 1 1 None

BCLR Ws,#bit4 Bit Clear Ws 1 1 None

6BRA BRA C,Expr Branch if Carry 1 1 (2) None

BRA GE,Expr Branch if greater than or equal 1 1 (2) None

BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None

BRA GT,Expr Branch if greater than 1 1 (2) None

BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None

BRA LE,Expr Branch if less than or equal 1 1 (2) None

BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None

BRA LT,Expr Branch if less than 1 1 (2) None

BRA LTU,Expr Branch if unsigned less than 1 1 (2) None

BRA N,Expr Branch if Negative 1 1 (2) None

BRA NC,Expr Branch if Not Carry 1 1 (2) None

BRA NN,Expr Branch if Not Negative 1 1 (2) None

BRA NOV,Expr Branch if Not Overflow 1 1 (2) None

BRA NZ,Expr Branch if Not Zero 1 1 (2) None

BRA OA,Expr Branch if accumulator A overflow 1 1 (2) None

BRA OB,Expr Branch if accumulator B overflow 1 1 (2) None

BRA OV,Expr Branch if Overflow 1 1 (2) None

BRA SA,Expr Branch if accumulator A saturated 1 1 (2) None

BRA SB,Expr Branch if accumulator B saturated 1 1 (2) None

BRA Expr Branch Unconditionally 1 2 None

BRA Z,Expr Branch if Zero 1 1 (2) None

BRA Wn Comput ed Br an ch 1 2 None

7BSET BSET f,#bit4 Bit Set f 1 1 None

BSET Ws,#bit4 Bit Set Ws 1 1 None

8BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None

BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None

9BTG BTG f,#bit4 Bit Toggle f 1 1 None

BTG Ws,#bit4 Bit Toggle Ws 1 1 None

10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1

(2 or 3) None

BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1

(2 or 3) None

dsPIC30F1010/202X

11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1

(2 or 3) None

BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1

(2 or 3) None

12 BTST BTST f,#bit4 Bit Test f 1 1 Z

BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C

BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z

BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C

BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z

13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z

BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C

BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z

14 CALL CALL lit23 Call subroutine 2 2 None

CALL Wn Call indirect subroutine 1 2 None

15 CLR CLR f f = 0x0000 1 1 None

CLR WREG WREG = 0x0000 1 1 None

CLR Ws Ws = 0x0000 1 1 None

CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB

16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep

17 COM COM f f = f 11N,Z

COM f,WREG WREG = f 11N,Z

COM Ws,Wd Wd = Ws 11N,Z

18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z

CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z

CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z

19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z

CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z

20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,Ws Compare Wb with Ws, with Borrow

(Wb – Ws – C)1 1 C,DC,N,OV,Z

21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1

(2 or 3) None

22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1

(2 or 3) None

23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1

(2 or 3) None

24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠11

(2 or 3) None

25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C

26 DEC DEC f f = f –1 1 1 C,DC,N,OV,Z

DEC f,WREG WREG = f –1 1 1 C,DC,N,OV,Z

DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z

27 DEC2 DEC2 f f = f –2 1 1 C,DC,N,OV,Z

DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z

DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z

28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 Non e

29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C, OV

DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C, OV

DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C, OV

DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C, OV

30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C, OV

31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None

DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None

32 ED ED Wm * Wm,Acc,Wx,Wy,Wxd Euclidean Dis tance (no accumu late ) 1 1 OA,OB, OA B,

SA,SB,SAB

33 EDAC EDAC Wm * Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,

SA,SB,SAB

TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assemb ly Sy ntax Desc ri pt ion # of

word

# of

cycles Status Flags

Affected

dsPIC30F1010/202X

34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None

35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C

36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C

37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C

38 GOTO GOTO Expr Go to address 2 2 Non e

GOTO Wn Go to indirect 1 2 None

39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z

INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z

INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z

INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z

41 IOR IOR f f = f .IOR. WREG 1 1 N,Z

IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z

IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z

IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z

IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z

42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

43 LNK LNK #lit14 Link frame pointer 1 1 None

44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z

LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z

LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z

LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z

LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z

45 MAC MAC Wm *

Wn,Acc,Wx,Wxd,Wy,Wyd,

AWB

Multiply and Accumulate 1 1 OA,OB,OAB,

SA,SB,SAB

MAC Wm *

Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB,

SA,SB,SAB

46 MOV MOV f,Wn Move f to Wn 1 1 None

MOV f Move f to f 1 1 N,Z

MOV f,WREG Move f to WREG 1 1 N,Z

MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None

MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None

MOV Wn,f Move Wn to f 1 1 None

MOV Wso,Wdo Move Ws to Wd 1 1 None

MOV WREG,f Move WREG to f 1 1 N,Z

MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None

MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None

47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None

48 MPY MPY Wm *

Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

MPY Wm *

Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

49 MPY.N MPY.N Wm *

Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None

50 MSC MSC Wm *

Wm,Acc,Wx,Wxd,Wy,Wyd,

AWB

Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None

MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None

MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None

MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(Ws) 11None

MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None

MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(lit5) 11None

MUL f W3:W2 = f * WREG 1 1 None

TABLE 19-2: INSTRUCTION SET OVERVI EW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assemb ly Sy ntax Desc ri pt ion # of

word

# of

cycles Status Flags

Affected

dsPIC30F1010/202X

52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

NEG f f = f + 1 1 1 C,DC,N,OV,Z

NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

53 NOP NOP No Operation 1 1 None

NOPR No Operation 1 1 None

54 POP POP f Pop f from Top -of- Stack (TOS) 1 1 None

POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None

POP.D Wnd Pop from Top-of-St ack (TOS) to

W(nd):W(nd + 1) 12None

POP.S Pop Shadow Registers 1 1 All

55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None

PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None

PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack

(TOS) 12None

PUSH.S Push Shadow Registe rs 1 1 None

56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep

57 RCALL RCALL Expr Relative Call 1 2 None

RCALL Wn Computed Call 1 2 None

58 REPEAT REPEAT #lit14 Repeat Next Instruct ion lit 14 + 1 times 1 1 None

REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None

59 RESET RESET Software device Reset 1 1 None

60 RETFIE RETFIE Return from interrupt 1 3 (2) None

61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None

62 RETURN RETURN Return from Subroutine 1 3 (2) None

63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z

RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z

RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z

64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z

RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z

RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z

65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z

RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z

RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z

66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z

RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z

RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z

67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None

SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None

68 SE SE Ws,Wnd Wnd = sign extended Ws 1 1 C,N,Z

69 SETM SETM f f = 0xFFFF 1 1 None

SETM WREG WREG = 0xFFFF 1 1 None

SETM Ws Ws = 0xFFFF 1 1 None

70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,

SA,SB,SAB

SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,

SA,SB,SAB

71 SL SL f f = Left Shift f 1 1 C,N,OV,Z

SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z

SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z

SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z

SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z

TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assemb ly Sy ntax Desc ri pt ion # of

word

# of

cycles Status Flags

Affected

dsPIC30F1010/202X

72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,

SA,SB,SAB

SUB f f = f – WREG 1 1 C,DC,N,OV,Z

SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z

SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z

SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z

SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z

73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z

SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z

SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z

SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z

SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z

74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z

SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z

SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z

SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z

75 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z

SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z

76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None

SWAP Wn Wn = byte swap Wn 1 1 None

77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None

78 TBLRDL TBLRDL Ws,Wd Read Prog< 15:0> to Wd 1 2 None

79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None

80 TBLWTL TBLWTL Ws,Wd W rite Ws to P rog<15:0> 1 2 None

81 ULNK ULNK Unlink frame pointer 1 1 None

82 XOR XOR f f = f .XOR. WREG 1 1 N,Z

XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z

XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z

XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z

XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z

83 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N

TABLE 19-2: INSTRUCTION SET OVERVI EW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assemb ly Sy ntax Desc ri pt ion # of

word

# of

cycles Status Flags

Affected

dsPIC30F1010/202X

20.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C18 and MPLAB C30 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Progra mmers

- PICSTART® Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

20.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- Emulator (sold separatel y)

- In-Circuit Deb ugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Visual device initializer for easy register

initialization

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Exten si ve on-l in e help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

The MPLAB IDE allows you to:

• Edit your source files (eithe r assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug us ing :

- Source files (assemb ly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

dsPIC30F1010/202X

20.2 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assemb ler for all PIC MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

sour ce fil es

• Directives that allow complete control over the

assembly process

20.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC18 family of microcontrollers and the

dsPIC30, dsPIC33 and PIC24 family of digital signal

controllers. These compilers provide powerful integra-

tion capabilities, superior code optimization and ease

of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

20.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB O bject Li brarian manag es the cre ation an d

modification of library files of precompiled code. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, de letion and extraction

20.5 MPLAB ASM30 Assembler, Linker

and Librarian

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or lin ked with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

20.6 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most periph erals and inte rnal regi sters.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

dsPIC30F1010/202X

20.7 MPLAB ICE 2000

High-Performance

In-Circui t Emu lator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing feat ures. Interc hangeabl e proces sor modul es allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows® 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

20.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash D SC® and MCU devic es. It debugs and

programs PIC® and dsPIC® Flash microcontrollers with

the easy-to-use, powerful graphical user interface of the

MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE pro be is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high speed, noise tolerant, low-

voltage differential signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB ID E, new devic es w ill be supported,

and new features will be add ed, such as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advant ages over competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables .

20.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial ProgrammingTM (ICSPTM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug sou rce code by s etting bre akpoi nts , singl e step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

20.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64 ) for men us an d error m essages and a m odu-

lar, detachable socket assembly to support various

pack age types. The ICSP™ cable assembly is in cluded

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Devic e Programmer ca n read, verif y and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 h as high-spe ed co mmunicat ions and

optimized algorithms for quick programming of large

memory devices and in corporates an SD/MMC card for

file storage and secure data applications.

dsPIC30F1010/202X

20.11 PICSTART Plus Development

Programmer

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Inte grated Dev elopmen t En vironme nt so ftware makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76 X, may be sup ported with an a dapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

20.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’ s baseline, mid-range and PIC18F families of

Flash m emory microcontrol lers. The PICkit 2 S tarter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler , and is desig ned to hel p get up to s peed

quickly using PIC® microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

20.13 Demonstration, Development and

Evaluation Boards

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards incl ude prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The board s suppo rt a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory .

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart® battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

dsPIC30F1010/202X

21.0 ELECTRICAL CHARACTERISTICS

This section provid es an overview of dsPIC30 F electrical charac teristics. Additional information will be provided in future

revisions of this document as it becomes available.

For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual”

(DS70046).

Absolute maximum ratings for the device family are listed below. Exposure to these maximum rating conditions for

extende d peri ods may aff ec t devi ce re liabil ity. Functio nal o peratio n of t he devi ce at these or a ny other condi tions abov e

the parameters indicated in the operation listings of this specification is not implied.

Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR)(1)................................................-0.3V to (VDD + 0.3V)

Volta ge on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V

Volta ge on MCLR with respect to VSS(1).........................................................................................-0.3V to (VDD + 0.3V)

Maximum curr ent o ut of VSS pin ...........................................................................................................................300 mA

Maximum curr ent i nto VDD pin(2)...........................................................................................................................300 mA

Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports.......................................................................................................................200 mA

Maximum current sourced by all ports(2)...............................................................................................................200 mA

Note 1: V olt age spik es below VSS at the MCLR/VPP pin, in ducin g curr ents gr eater than 8 0 mA, may caus e latc h-up.

Thus, a se ries resi sto r of 50-100Ω sho ul d b e u sed when appl yi ng a “low ” l ev el to the MC L R/VPP pin, rather

than pulling this pin directly to VSS.

2: Maximum allowable current is a function of device maximum power dissipation. See Table 21-2.

21.1 DC Characteristics

†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a stres s rating onl y and funct ional ope ration of the device at tho se or any other co nditio ns above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

TABLE 21-1: OPERATING MIPS VS. VOLTAGE

VDD Range Temp Range Max MIPS

dsPIC30FXXX-30I dsPIC30FXXX-20E

4.5-5.5V -40°C to 85°C 30 —

4.5-5.5V -40°C to 125°C — 20

3.0-3.6V -40°C to 85°C 20 —

3.0-3.6V -40°C to 125°C — 15

dsPIC30F1010/202X

TABLE 21-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min Typ Max Unit

dsPIC30F1010/202X-30I

Operating Junction Temperature Range TJ-40 +125 °C

Operating Ambient Temperature Range TA-40 +85 °C

dsPIC30F1010/202X-20E

Operati ng Junction Temperature Range TJ-40 +150 °C

Operating Ambient Temperature Range TA-40 +125 °C

Power Dissipation:

Internal ch ip pow er dis sip ation:

PDPINT + PI/OW

I/O Pin power dissipation:

Maximum Allowed Power Dissipation PDMAX (TJ - TA) / θJA W

TABLE 21-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ Max Unit Notes

Package Thermal Resistance, 28-pin SO IC (SO) θJA 48.3 °C/W 1, 2

Package Thermal Resistance, 28-pin QFN θJA 33.7 °C/W 1, 2

Package Thermal Resistance, 28-pin SPDIP (SP) θJA 42 °C/W 1, 2

Package Thermal Resistance, 44-pin QFN θJA 28 °C/W 1, 2

Package Thermal Resistance, 44-pin TQFP θJA 39.3 °C/W 1, 2

Note 1: Junction to ambient thermal resistance, Theta-ja (θJA) numbers are achieved by package simulations.

2: Depending on operating conditions, air flow may be required for improved thermal performance.

TABLE 21-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10% )

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

Operating Voltage(2)

DC10 VDD Supply Voltage 3.0 — 5.5 V Industrial tem pera ture

DC11 VDD Supply Voltage 3.0 — 5.5 V Extended temperature

DC12 VDR RAM Data Retention Voltag e(3) —1.5—V

DC16 VPOR VDD Start Voltage

to ensure internal

Power-on Rese t signal

—VSS —V

DC17 SVDD VDD Rise Rate

to ensure internal

Power-on Rese t signal

0.05 V/ms 0-5V in 0.1 sec

0-3.3V in 60 ms

Note 1: Data in “Typ” colu mn is a t 5V, 25°C unless othe rwis e st ated. Par ameters are for d esign guidan ce onl y and

are not t ested.

2: These parameters are characterized but not tested in manufacturing.

3: This is the limit to which VDD can be lowered without losing RAM data.

PINT VDD IDD IOH

∑

–()×=

I/O

–

{}

×()

∑VOL IOL

()

∑

dsPIC30F1010/202X

TABLE 21-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

DC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No. Typical(1) Max Units Conditions

Operating Current (IDD)(2)

DC20a 13 16 mA 25°C 3.3V

FRC 3.2 MIPS, PLL disabled

DC20b 14 16 mA 85°C

DC20c 14 17 mA 125°C

DC20d 22 26 mA 25°C 5VDC20e 22 26 mA 85°C

DC20f 22 27 mA 125°C

DC22a 19 22 mA 25°C 3.3V

FRC, 4.9 MIPS, PLL disabled

DC22b 19 23 mA 85°C

DC22c 19 23 mA 125°C

DC22d 30 36 mA 25°C 5VDC22e 30 37 mA 85°C

DC22f 31 37 mA 125°C

DC23a 27 33 mA 25°C 3.3V

FRC, 7.3 MIPS, PLL disabled

DC23b 28 33 mA 85°C

DC23c 28 34 mA 125°C

DC23d 44 53 mA 25°C 5VDC23e 45 53 mA 85°C

DC23f 45 54 mA 125°C

DC24a 66 79 mA 25°C 3.3V

FRC 13 MIPS, PLL enabled

DC24b 67 80 mA 85°C

DC24c 68 81 mA 125°C

DC24d 108 129 mA 25°C 5VDC24e 109 130 mA 85°C

DC24f 110 131 mA 125°C

DC26a 98 118 mA 25°C 3.3V

FRC 20 MIPS, PLL enabled

DC26b 99 118 mA 85°C

DC26d 159 191 mA 25°C 5VDC26e 160 192 mA 85°C

DC26f 161 193 mA 125°C

DC27d 222 267 mA 25°C 5V FRC, 30 MIPS, PLL enabled

DC27e 223 267 mA 85°C

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows:

- All I/O pins are configured as Outputs and pulled to VSS.

- MCLR = VDD, WDT and FSCM are disab led .

- CPU, SRAM, Program Memory and Data Memory are operational.

- No peripheral modules are operating.

dsPIC30F1010/202X

DC28a 96 116 mA 25°C 3.3V

EC, 20 MIPS, PLL enabled

DC28b 97 116 mA 85°C

DC28d 157 188 mA 25°C 5VDC28e 158 189 mA 85°C

DE28f 159 191 mA 125°C

DC29d 227 273 mA 25°C 5V EC, 30 MIPS, PLL enabled

DC29e 228 273 mA 85°C

TABLE 21-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CON TI N U ED)

DC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operating temp erature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No. Typical(1) Max Units Conditions

Operating Current (IDD)(2)

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows:

- All I/O pins are configured as Outputs and pulled to VSS.

- MCLR = VDD, WDT and FSCM are disab led .

- CPU, SRAM, Program Memory and Data Memory are operational.

- No peripheral modules are operating.

dsPIC30F1010/202X

TABLE 21-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

DC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No. Typical(1) Max Units Conditions

Idle Current (IIDLE): Core OFF Clock ON Base Current(2)

DC40a 8 9 mA 25°C 3.3V

FRC, 3.2 MIPS, PLL disabled

DC40b 8 9 mA 85°C

DC40c 8 10 mA 125°C

DC40d 12 15 mA 25°C 5VDC40e 13 15 mA 85°C

DC40f 13 16 mA 125°C

DC42a 10 12 mA 25°C 3.3V

FRC, 4.9 MIPS, PLL disabled

DC42b 11 13 mA 85°C

DC42c 11 13 mA 125°C

DC42d 17 20 mA 25°C 5VDC42e 17 21 mA 85°C

DC42f 18 21 mA 125°C

DC43a 15 18 mA 25°C 3.3V

FRC, 7.3 MIPS, PLL disabled

DC43b 15 18 mA 85°C

DC43c 15 18 mA 125°C

DC43d 24 29 mA 25°C 5VDC43e 24 29 mA 85°C

DC43f 25 30 mA 125°C

DC44a 44 53 mA 25°C 3.3V

FRC, 13 MIPS, PLL enabled

DC44b 45 54 mA 85°C

DC44c 46 55 mA 125°C

DC44d 72 87 mA 25°C 5VDC44e 73 88 mA 85°C

DC44f 74 89 mA 125°C

DC46a 66 79 mA 25°C 3.3V

FRC 20 MIPS, PLL enabled

DC46b 67 80 mA 85°C

DC46d 108 129 mA 25°C 5VDC46e 109 131 mA 85°C

DC45f 110 132 mA 125°C

DC47d 152 182 mA 25°C 5V FRC, 30 MIPS, PLL enabled

DC47e 153 183 mA 85°C

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Base IIDLE current is measured with Core off, Clock on and all modules turned off. All I/Os are configured

as inputs and pulled high. WDT, etc. are all switched off.

dsPIC30F1010/202X

DC48a 65 78 mA 25°C 3.3V

EC, 20 MIPS, PLL enabled

DC48b 66 79 mA 85°C

DC48d 105 127 mA 25°C 5VDC48e 107 128 mA 85°C

DC48f 108 130 mA 125°C

DC49d 155 186 mA 25°C 5V EC, 30 MIPS, PLL enabled

DC49e 156 187 mA 85°C

TABLE 21-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)

DC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operating temp erature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No. Typical(1) Max Units Conditions

Idle Current (IIDLE): Core OFF Clock ON Base Current(2)

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Base IIDLE current is measured with Core off, Clock on and all modules turned off. All I/Os are configured

as inputs and pulled high. WDT, etc. are all switched off.

dsPIC30F1010/202X

TABLE 21-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No. Typical(1) Max Units Conditions

Power-Down Current (IPD)

DC60a 1.2 2.4 mA 25°C 3.3V

Base Power-Down Current(2)

DC60b 1.2 2.4 mA 85°C

DC60c 1.3 2.6 mA 125°C

DC60e 2.1 4.2 mA 25°C 5VDC60f 2.1 4.2 mA 85°C

DC60g 2.3 4.6 mA 125°C

DC61a 15 30 μA 25°C 3.3V

Watchdog Timer Current: ΔIWDT(3)

DC61b 14 30 μA 85°C

DC61c 14 30 μA 125°C

DC61e 30 60 μA 25°C 5VDC61f 29 60 μA 85°C

DC61g 30 60 μA 125°C

Note 1: Data in the Typical column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IPD is measured with all peripherals and clocks shutdown. All I/Os are configured as inputs and

pulled high. WDT, etc. are all switched off.

3: The Δ current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

dsPIC30F1010/202X

TABLE 21-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extende d

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

VIL Input Low Voltage(2)

DI10 I/O pins:

with Schmitt Trigger buffer VSS —0.2VDD V

DI15 MCLR VSS —0.2VDD V

DI16 OSC1 (in HS mode) VSS —0.2VDD V

DI18 SDA, SCL VSS —0.3VDD V SMbus disabled

DI19 SDA, SCL VSS —0.2VDD V SMbus enabled

VIH Input High Voltage(2)

DI20 I/O pins:

with Schmitt Trigger buffer 0.8 VDD —VDD V

DI25 MCLR 0.8 VDD —VDD V

DI26 OSC1 (in HS mode) 0.7 VDD —VDD V

DI28 SDA, SCL 0.7 VDD —VDD V SMbus disabled

DI29 SDA, SCL 0.8 VDD —VDD V SMbus enabled

IIL Input Leakage Current(2)(3)(4)

DI50 I/O ports — 0.01 ±1 μAVSS ≤ VPIN ≤ VDD,

Pin at high-impedance

DI51 Analog input pins — 0.50 — μAV

SS ≤ VPIN ≤ VDD,

Pin at high-impedance

DI55 MCLR —0.05±5μAVSS ≤ VPIN ≤ VDD

DI56 OSC1 — 0.05 ±5 μAVSS ≤ VPIN ≤ VDD, HS

Osc mode

Note 1: Data in “Typ” colu mn is a t 5V, 25°C unless othe rwis e st ated. Par ameters are for d esign guidan ce onl y and

are not t ested.

2: These parameters are characterized but not tested in manufacturing.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

4: Negative current is defined as current sourced by the pin.

dsPIC30F1010/202X

TABLE 21-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10% )

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

VOL Output Low Voltage(2)

DO10 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 5V

——TBDVIOL = 2.0 mA, VDD = 3.3V

DO16 OSC2/CLKO — — 0.6 V IOL = 1.6 mA, VDD = 5V

(RC or EC Osc mode) — — TBD V IOL = 2.0 mA, VDD = 3.3V

VOH Output High Voltage(2)

DO20 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 5V

TBD — — V IOH = -2.0 mA, VDD = 3.3V

DO26 OSC2/CLKO VDD – 0.7 — — V IOH = -1.3 mA, VDD = 5V

(RC or EC Osc mode) TBD — — V IOH = -2.0 mA, VDD = 3.3V

Capacitive Loading Specs

on Output Pins(2)

DO50 COSC2 OSC2 pin — — 1 5 pF In HS mode when external

clock is used to drive OSC1.

DO56 CIO All I/O pins and OSC2 — — 50 pF RC or EC Osc mode

DO58 CBSCL, SDA — — 400 pF In I2C mode

Legend: TBD = To Be Determined

Note 1: Data i n “Typ” column is at 5V, 25°C unless o the rw is e s t ate d. Pa ram ete rs ar e for design guidanc e on ly and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

TABLE 21-10: DC CHARACTERISTICS: PROGRAM AND EEPROM

DC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Ex tended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

Program Flash Memory(2)

D130 EPCell Endurance 10 K 100K — E/W

D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating

voltage

D132 VEB VDD for Bulk Erase 4.5 — 5.5 V

D133 VPEW VDD for Erase/Wr ite 3.0 — 5.5 V

D134 TPEW Erase/Write Cycle Time — 2 — ms

D135 TRETD Characteristic Retention 40 100 — Year Provided no other specifications

are violated

D136 TEB ICSP Block Erase Time — 4 — ms

D137 IPEW IDD During Programming — 10 30 mA Row Erase

D138 IEB IDD During Programming — 10 30 mA Bulk Erase

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

2: These parameters are characterized but not tested in manufacturing.

dsPIC30F1010/202X

21.2 AC Characteri stics and Ti ming Parameters

The information contained in this section defines dsPIC30F AC characteristics and timing parameters.

TABLE 21-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGU RE 21-1: LOAD C O ND ITIONS FOR D E VI CE TIMING SP E CI FI CA T IO N S

FIGU RE 21-2: EXTERNA L C LOC K TIMING

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Operati ng voltage VDD range as described in DC Spec Section 21.0.

VDD/2

VSS

RL= 464 Ω

CL= 50 pF for all pins except OSC2

5 pF for OSC2 output

Load Cond itio n 1 – for all pins except OSC2 Load Condition 2 – for OSC2

OSC1

CLKO

Q1 Q2 Q3 Q4

OS20

OS25 OS30 OS30

OS40 OS41

OS31 OS31

Q1 Q2 Q3 Q4

dsPIC30F1010/202X

TABLE 21-12: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operating temp erature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

OS10 FIN External CLKI Frequency(2)

(External clocks allowed only

in EC mode)

6—

—15.00

15.00 MHz

MHz EC

EC with 32x PLL

Oscillator Frequency(2) 6

6—

—15.00

15.00 MHz

MHz HS

FRC internal

OS20 TOSC TOSC = 1/FOSC(3) 16.5 — DC ns

OS25 TCY Instruction Cycle Time(2)(4) 33 — DC ns

OS30 TosL,

TosH External C lock(2) in (OSC1 )

High or Low Time .45 x

TOSC ——nsEC

OS31 TosR,

TosF External C lock(2) in (OSC1 )

Rise or Fall Time — — 20 ns EC

OS40 TckR CLKO Rise Time(2)(5) — 6 10 ns

OS41 TckF CLKO Fall Time(2)(5) — 6 10 ns

Note 1: Data in “Typ” colu mn is a t 5V, 25°C unless othe rwis e st ated. Par ameters are for d esign guidan ce onl y and

are not t ested.

2: These parameters are characterized but not tested in manufacturing.

3: The oscillator frequency (FOSC) is equal to FIN when the PLL is disabled. FOSC is equal to 4 x FIN when

the PLL is enabled.

4: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”

values with an external clock applied to the OSC1/CLK1 pin. When an external clock input is used, the

“Max.” cycle time limit is “DC” (no clock) for all devices.

5: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.

dsPIC30F1010/202X

TABLE 21-13: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0 AND 5.0V )

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (± 10% )

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OS50 FPLLI PLL Input Frequency Range(2) 6 — 15 MHz EC, HS modes with PLL

x32

OS51 FSYS On-chip PLL Output(2) 192 — 480 MHz EC, HS modes with PLL

x32

OS52 TLOC PLL Start-up Time (Lock Time) — 20 50 μs

OS53 DCLK CLKO Stability (Jitter) — — 1 % Measured over 100 ms

period

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” column is at 5V, 25°C unless o the rwis e s t ated. Param ete rs ar e for design guidanc e on ly and

are not tested.

TABLE 21-14: INTERNAL CLOCK TIMING EXAMPLES

Clock

Oscillator

Mode FIN (MHz)(1) TCY (μsec)(2) MIPS(3)

w/o PLL MIPS(4)

w/PLL x32

EC 10 0.2 5.0 20

15 0.133 7.5 30

HS 10 0.2 5.0 20

15 0.133 7.5 30

Note 1: Assumption: Oscillator Postscaler is divide by 1.

2: Ins truction Execut ion Cycle Time: TCY = 1/MIPS.

3: Ins truction Execution Frequency with out PLL: MIPS = FIN/2 (since there are 2 Q clocks per instruction

cycle).

4: Instruction Execution Fr equency with PLL: MIPS = (FIN * 2).

dsPIC30F1010/202X

TABLE 21-15: AC CHARACTERISTICS: INTERNAL RC ACCURACY

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (± 10%)

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Characteristic Min Typ Max Units Conditions

Internal FRC Accuracy @ FRC Freq = 6.4 MHz(1)

FRC -0.06 — +0.06 % +25°C VDD = 3.0-3.6V

-0.06 — +0.06 % +25°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V

Internal FRC Accuracy @ FRC Freq = 9.7 MHz(1)

FRC -0.06 — +0.06 % +25°C VDD = 3.0-3.6V

-0.06 — +0.06 % +25°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V

Internal FRC Accuracy @ FRC Freq = 14.55 MHz(1)

FRC -0.06 — +0.06 % +25°C VDD = 3.0-3.6V

-0.06 — +0.06 % +25°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V

Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift.

dsPIC30F1010/202X

TABLE 21-16: AC CHARACTERISTICS: INTERNAL RC JITTER

AC CHARACTERISTICS

Standard Operating Conditions:

3.3V and 5.0V (±10% )

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85° C for industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Characteristic Min Typ Max Units Conditions

Internal FRC Jitter @ FRC Freq = 6.4 MHz(1)

FRC -1 — +1 % +25°C VDD = 3. 0-3.6V

-1 — +1 % +25°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V

Internal FRC Jitter @ FRC Freq = 9.7 MHz(1)

FRC -1 — +1 % +25°C VDD = 3. 0-3.6V

-1 — +1 % +25°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V

Internal FRC Jitter @ FR C Freq = 14.55 MHz(1)

FRC -1 — +1 % +25°C VDD = 3. 0-3.6V

-1 — +1 % +25°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V

-1 — +1 % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V

-1 — +1 % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V

Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift.

dsPIC30F1010/202X

FIGURE 21-3: CLKO AND I/O TIMING CHARACTERISTICS

TABLE 21-17: CLKO AND I/O TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1)(2) Min Typ(3) Max Units Conditions

DO31 TIOR Port output rise time — 10 25 ns —

DO32 TIOF Port output fall time — 10 25 ns —

DI35 TINP INTx pin high or low ti me (output) 20 — — ns —

DI40 TRBP CNx high or low time (input) 2 TCY ——ns —

Note 1: These parameters are asynchronous events not related to any internal clock edges.

2: These parameters are characterized but not tested in manufacturing.

3: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

Note: Refer to Figur e 21-1 for load conditions.

I/O Pin

(Input)

I/O Pin

(Output)

DI35

Old Value New Value

DI40

DO31

DO32

dsPIC30F1010/202X

FIGURE 21-4: RESET, W ATCHDOG T I MER, OSCILLATOR START-UP T IMER AND POWER -UP

TIMER TIMING CHARACTERISTICS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

SY11

SY10

SY20

SY13

I/O Pins

SY13

Note: Refer to Figure 21-1 for load conditions.

FSCM

Delay

SY35

SY30

SY12

dsPIC30F1010/202X

TABLE 21-18: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TI MER, POWER-UP TIMER

AND TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10% )

(unless otherwise stated)

Ope rati ng temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SY10 TmcL MCLR Pulse Width (low) 2 — — μs -40°C to +125°C

SY11 TPWRT Power-up Timer Period 0. 75

1.5

128

1.25

2.5

160

ms -40°C to +125°C

User program ma ble

SY12 TPOR Power-On Reset Delay 3 10 30 μs -40°C to +125°C

SY13 TIOZ I/O High-impedance from MCLR

Low or Watchdog Timer Reset —0.81.0μs

SY20 TWDT1 Watchdog T imer T ime-out Period

(No Prescaler) 1.4 2.1 2.8 ms VDD = 5V, -40°C to

+125°C

TWDT2 1.4 2.1 2.8 ms VDD = 3.3V, -40°C to

+125°C

SY30 TOST Oscillation St art-u p Timer Period — 1024 TOSC ——TOSC = OSC1 period

SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 — μs -40°C to +125°C

Note 1: These parameters are characterized but not te sted in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

dsPIC30F1010/202X

FIGURE 21-5: BAND GAP START-UP T IME CHARACTERISTICS

TABLE 21-19: BAND GAP START-UP TIME REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SY40 TBGAP Band Gap Start-up Time — 40 65 µs Defined as the time between the

instant that the band gap is enabled

and the moment that the band gap

reference voltage is stabl e.

RCON<13> status bit.

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

VBGAP

Enable Band Gap

Band Gap

(see Note)

Stable

SY40

dsPIC30F1010/202X

FIGU RE 21-6: TIMER E XTE RNAL CL OC K T IMIN G CHA RACTE RIST ICS

TABLE 21-20: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operati ng tem pe rature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TA10 TTXH TxCK High Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TA15

Synchronous,

with prescaler 10 — — ns

Asynchronous 10 — — ns

TA11 TTXL TxCK Low Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TA15

Synchronous,

with prescaler 10 — — ns

Asynchronous 10 — — ns

TA15 TTXP TxCK Input Period Synchronous,

no prescaler TCY + 10 — — ns

Synchronous,

with prescaler Greater of:

20 ns or

(TCY + 40)/N

———N = prescale

value

(1, 8, 64, 256)

Asynchronous 20 — — ns

OS60 Ft1 SOSC1/T1CK oscillator input

frequency range (oscillator enabled

by setting bit TCS (T1CON, bit 1))

DC — 50 kHz

TA20 TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment 0.5 TCY 1.5 TCY —

Tx11

Tx15

Tx10

Tx20

TMRX OS60

TxCK

Note: “x” refers to Timer Ty pe A or Timer Type B.

Refer to Figure 21-1 for load conditions.

dsPIC30F1010/202X

TABLE 21-21: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENT S

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10% )

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TB10 TtxH Tx CK High Time S ync hronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

param eter TB15

Synchronous,

with prescaler 10 — — ns

TB11 TtxL TxCK Low Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

param eter TB15

Synchronous,

with prescaler 10 — — ns

TB15 TtxP TxCK Input Period Synchronous,

no prescaler TCY + 10 — — ns N = prescale

value (1, 8, 64, 256)

Synchronous,

with prescaler Greater of:

20 ns or

(TCY + 40)/N

TB20 TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment 0.5 TCY — 1.5 TCY —

TABLE 21-22: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENT S

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10% )

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet

parameter TC15

TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet

parameter TC15

TC15 TtxP TxCK Inpu t Period S ync hronous,

no prescale r TCY + 10 — — ns N = prescale

value (1, 8, 64,

256)

Synchronous,

with prescaler Greater of:

20 ns or

(TCY + 40) /

TC20 TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment 0.5 TCY —1.5

TCY —

dsPIC30F1010/202X

FIGU RE 21-7: INPUT CAPT URE ( CAPx) TIMI NG CH ARACT ERI STIC S

FIGURE 21-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

TABLE 21-23: INPUT CAPTURE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10% )

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Max Units Conditions

IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns

With Prescaler 10 — ns

IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns

With Prescaler 10 — ns

IC15 TccP ICx Input Period (2 TCY + 40) / N — ns N = prescale

value (1, 4, 16)

Note 1: These parameters are characterized but not te sted in manufacturing.

TABLE 21-24: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10% )

(unless otherwise stated)

Ope rati ng temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OC10 TccF OCx Output Fall Time — — — ns See parameter D0 32

OC11 TccR OCx Outpu t Rise Time — — — ns See parameter D031

Note 1: These parameters are characterized but not te sted in manufacturing.

2: Dat a in “Typ” colu mn is at 5V, 25°C unless otherwi se st ated. Para meters are for desi gn guida nce onl y and

are not t ested.

ICX

IC10 IC11

IC15

Note: Refer to Figure 21-1 for load conditions.

OCx

OC11 OC10

(Output Compare

Note: Refer to Figure 21-1 for load conditions.

or PWM Mode)

dsPIC30F1010/202X

FIGURE 21-9: OC/PWM MODULE TIMING CHARACTERISTICS

TABLE 21-25: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10% )

(unless otherwise stated)

Ope rati ng temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OC15 TFD Fault Input to PWM I/O

Change ——25nsVDD = 3.3V -40°C to +85°C

TBD ns VDD = 5V

OC20 TFLT Fault Input Pulse Width — — 50 ns VDD = .33V -40°C to +85°C

TBD ns VDD = 5V

Legend: TBD = To Be Determined

Note 1: These parameters are characterized but not te sted in manufacturing.

2: Dat a in “Typ” colu mn is a t 5V, 25°C unless othe rwis e st ated. Par ameters are for d esign guidan ce onl y and

are not t ested.

OCFA/OCFB

OCx

OC20

OC15

dsPIC30F1010/202X

FIGURE 21-10: POWER SUPPLY PWM MODULE FAULT TIMING CHARACTERISTICS

FIGURE 21-11: POWER SUPPLY PWM MODULE T I MING CHARAC TERISTICS

TABLE 21-26: POWER SUPPLY PWM MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

MP10 TFPWM PWM Output Fall Time — 10 25 ns VDD = 5V

MP11 TRPWM PWM Output Rise Time — 10 25 ns VDD = 5V

MP12 TFPWM PWM Output Fall Time — TBD TBD ns VDD = 3.3V

MP13 TRPWM PWM Output Rise Time — TBD TBD ns VDD = 3.3V

MP20 TFD Fault Input ↓ to PWM

I/O Chan ge ——TBDns VDD = 3.3V

25 ns VDD = 5V

MP30 TFH Mi nimum P ulse Width — — TBD ns VDD = 3.3V

50 ns VDD = 5V

Legend: TBD = To Be Determined

Note 1: These parameters are characterized but not te sted in manufacturing.

2: Dat a in “Typ” colu mn is a t 5V, 25°C unless othe rwis e st ated. Par ameters are for d esign guidan ce onl y and

are not t ested.

FLTA/B

PWMx

MP30

MP20

PWMx

MP11 MP10

Note: Refer to Figure 21-1 for load cond iti ons .

dsPIC30F1010/202X

FIGURE 21-12: SPI MO DULE MA STER MOD E (CKE = 0) TIMING CHARACTERISTICS

TABLE 21-27: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10% )

(unless otherwise stated)

Ope rati ng temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Para

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscL SCKX Output Low Time(3) TCY/2 — — ns —

SP11 TscH SCKX Output High Time(3) TCY/2 — — ns —

SP20 TscF SCKX Output Fall Time(4) — — — n s See parameter D032

SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter D031

SP30 TdoF SDOX Data Output Fall Time(4) — — — ns See parameter D032

SP31 TdoR SDOX Data Output Rise Time(4) — — — ns See parameter D031

SP35 TscH2doV,

TscL2doV SDOX Data Output Valid after

SCKX Edge — — 30 ns —

SP40 TdiV2scH,

TdiV2scL Setup Ti me of SDIX Data Input

to SCKX Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIX Data Input

to SCKX Edge 20 — — ns —

Note 1: These parameters are characterized but not te sted in manufacturing.

2: Dat a in “Typ” column is at 5V, 25°C u nless ot herwi se st ated . Pa rameters a re f or desi gn gu idanc e only and

are not t ested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

SP11 SP10

SP40 SP41

SP21

SP20

SP35

SP20

SP21

MSb LSb

BIT14 - - - - - -1

MSb IN LSb IN

BIT14 - - - -1

SP30

SP31

Note: Refer to Figur e 21-1 for load conditio ns.

dsPIC30F1010/202X

FIGURE 21-13: SPI MO DULE MA STER MOD E (CKE = 1) TIMING CHARACTERISTICS

TABLE 21-28: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (± 10% )

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscL SCKX output low time(3) TCY / 2 — — ns —

SP11 TscH SCKX output high time (3) TCY / 2 — — ns —

SP20 TscF SCKX output fall time(4) — — — ns See parameter D032

SP21 TscR SCKX output rise time(4) — — — ns See parameter D031

SP30 TdoF SDOX data output fall time(4) — — — ns See parameter D032

SP31 TdoR SDOX data output rise time(4) — — — ns See parameter D031

SP35 TscH2doV,

TscL2doV SDOX data output valid after

SCKX edge — — 30 ns —

SP36 TdoV2sc,

TdoV2scL SDOX data output setup to

first SCKX edge 30 — — ns —

SP40 TdiV2scH,

TdiV2scL Setup time of SDIX dat a input

to SCKX edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold time of SDIX data input

to SCKX edge 20 — — ns —

Note 1: These parameters are characterized but not te sted in manufacturing.

2: Dat a in “Typ” colu mn is a t 5V, 25°C unless othe rwis e st ated. Par ameters are for d esign guidan ce onl y and

are not t ested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

SCKX

(CKP = 0)

SCKX

(CKP = 1)

SDOX

SDIX

SP36

SP30,SP31

SP35

MSb

MSb IN

BIT14 - - - - - -1

LSb IN

BIT14 - - - -1

LSb

Note: Refer to Figure 21-1 for load conditions.

SP11 SP10 SP20

SP21

SP20

SP40

SP41

dsPIC30F1010/202X

FIGU RE 21-14: SPI M O DU LE SL AV E MOD E (C KE = 0) TIMING CHARACTERISTICS

TABLE 21-29: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C fo r Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscL SCKX Input Low Ti me 30 — — ns —

SP71 TscH SCKX Input High Time 30 — — ns —

SP72 TscF SCKX Input Fall Time(3) —1025 ns —

SP73 TscR SCKX Input Rise Time(3) —1025 ns —

SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter D032

SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter D031

SP35

TscH2doV

TscL2doV

SDOX Data Output Valid after

SCKX Edge ——30ns —

SP40

TdiV2scH,

TdiV2scL

Setup Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP41

TscH2diL,

TscL2diL

Hold Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP50

TssL2scH ,

TssL2scL

SSX↓ to SCKX↑ or SCK X↓ Inp ut 120 — — ns —

SP51

TssH2doZ

SSX↑ to SDOX Output

High-impedance(3) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSX after SCK Edge 1.5 TCY

+ 40 ——ns —

Note 1: These parameters are characterized but not te sted in manufacturing.

2: Dat a in “Typ” colu mn is a t 5V, 25°C unless othe rwis e st ated. Par ameters are for d esign guidan ce onl y and

are not t ested.

3: Assumes 50 pF load on all SPI pins.

SCK

(CKP =

)

SCK

(CKP =

)

SDO

SDI

SP50

SP40 SP41

SP30,SP31 SP51

SP35

SDI

MSb LSb

BIT14 - - - - - -1

MSb IN BIT14 - - - -1 LSb IN

SP52

SP73

SP72

SP73

SP71 SP70

Note: Refer to Figure 21-1 for load conditions.

dsPIC30F1010/202X

FIGU RE 21-15: SPI M O DU LE SL AV E MOD E (C KE = 1) TIMING CHARACTERISTICS

SSX

SCKX

(CKP = 0)

SCKX

(CKP = 1)

SDOX

SDI

SP50

SP60

SDIX

SP30,SP31

MSb BIT14 - - - - - -1 LSb

SP51

MSb IN BIT14 - - - -1 LSb IN

SP35

SP52

SP73

SP72

SP73

SP71 SP70

SP40 SP41

Note: Refer to Figure 21- 1 for l oad conditions.

dsPIC30F1010/202X

TABLE 21-30: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscL SCKX Input Low Time 30 — — ns —

SP71 TscH SCKX Input High Time 30 — — ns —

SP72 TscF SCKX Input Fall Time(3) —1025ns —

SP73 TscR SCKX Input Rise Time(3) —1025ns —

SP30 TdoF SDOX Data Output Fall Ti me(3) — — — ns See parameter D0 32

SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parame ter D031

SP35 TscH2doV,

TscL2doV SDOX Data Output Valid after

SCKX Edge ——30ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP50 TssL2scH,

TssL2scL SSX↓ to SCKX↓ or SCKX↑ inpu t 120 — — ns —

SP51 TssH2doZ SS↑ to SDOX Output

High-impedance(4) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSX↑ after SCKX Edge 1.5 TCY

+ 40 ——ns —

SP60 TssL2doV SDOX Data Output Valid after

SSX Edge ——50ns —

Note 1: These parameters are characterized but not te sted in manufacturing.

2: Dat a in “Typ” colu mn is a t 5V, 25°C unless othe rwis e st ated. Par ameters are for d esign guidan ce onl y and

are not t ested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

dsPIC30F1010/202X

FIGURE 21-16: I2C™ BUS ST ART/STOP BITS T IMING CHARACTERISTICS (MASTER MODE)

FIGURE 21-17: I2C™ BUS DATA TIMING CH AR AC T ERI ST IC S ( M AST ER MO D E)

IM31 IM34

SCL

SDA

Start

Condition Stop

Condition

IM30 IM33

Note: Refer to Figure 21-1 for load conditions.

IM11 IM10 IM33

IM11 IM10

IM20

IM26 IM25

IM40 IM40 IM45

IM21

SCL

SDA

Out

Note: Refer to Figure 21-1 for load conditions.

dsPIC30F1010/202X

TABLE 21-31: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (± 10% )

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min(1) Max Units Conditions

IM10 TLO:SCL Clock Low Time 100 kHz mode TCY / 2 (BRG + 1) — µs —

400 kHz mode TCY / 2 (BRG + 1) — µs —

1 MHz mode(2) TCY / 2 (BRG + 1) — µs —

IM11 THI:SCL Clock High Time 100 kHz mode TCY / 2 (BRG + 1) — µs —

400 kHz mode TCY / 2 (BRG + 1) — µs —

1 MHz mode(2) TCY / 2 (BRG + 1) — µs —

IM20 TF:SCL SDA and SCL

Fall Time 100 kHz mode — 300 ns CB is specified to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(2) — 100 ns

IM21 TR:SCL SDA and SCL

Rise Time 100 kHz mode — 1000 ns CB is specified to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(2) — 300 ns

IM25 TSU:DAT Data Input

Setup Time 100 kHz mode 250 — ns —

400 kHz mode 100 — ns

1 MHz mode(2) TBD — ns

IM26 THD:DAT Data Input

Hold Time 100 kHz mode 0 — ns —

400 kHz mode 0 0.9 µs

1 MHz mode(2) TBD — ns

IM30 TSU:STA Start Condition

Setup Time 100 kHz mode TCY / 2 (BRG + 1) — µs Only relevant for

repeated Sta rt

condition

400 kHz mode TCY / 2 (BRG + 1) — µs

1 MHz mode(2) TCY / 2 (BRG + 1) — µs

IM31 THD:STA Start Condition

Hold Time 100 kHz mode TCY / 2 (BRG + 1) — µs After this period the

first clock pulse is

generated

400 kHz mode TCY / 2 (BRG + 1) — µs

1 MHz mode(2) TCY / 2 (BRG + 1) — µs

IM33 TSU:STO Stop Condition

Setup Time 100 kHz mode TCY / 2 (BRG + 1) — µs —

400 kHz mode TCY / 2 (BRG + 1) — µs

1 MHz mode(2) TCY / 2 (BRG + 1) — µs

IM34 THD:STO Stop Condition 100 kHz mode TCY / 2 (BRG + 1) — ns —

Hold Time 400 kHz mode TCY / 2 (BRG + 1) — ns

1 MHz mode(2) TCY / 2 (BRG + 1) — ns

IM40 TAA:SCL Output Valid

From Clock 100 kHz mode — 3500 ns —

400 kHz mode — 1000 ns —

1 MHz mode(2) ——ns —

IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — µ s Time the bus must be

free before a new

transmission can start

400 kHz mode 1.3 — µs

1 MHz mode(2) TBD — µs

Legend: TBD = To Be Determined

Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to the “Inter-Integrated Circuit™ (I2C)”

section in the “ds PIC30F Family Reference M anual” (DS70046).

2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).

dsPIC30F1010/202X

FIGURE 21-18: I2C™ BUS ST ART/STOP BITS T IMING CHARACTERISTICS (SLAVE MODE)

FIGURE 21-19: I2C™ BUS DATA TIMING CH AR AC T ERI ST IC S ( SL AV E MO DE)

IM50 CBBus Capacitive Loading — 400 pF

TABLE 21-31: I2C™ BUS DATA TI MING REQUIREMENTS (MASTER MODE) (CONTINUED)

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (± 10% )

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min(1) Max Units Conditions

Legend: TBD = To Be Determined

Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to the “Inter-Integrated Circuit™ (I2C)”

section in the “dsPIC30F Family Reference Manual” (DS70046).

2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).

IS31 IS34

SCL

SDA

Start

Condition Stop

Condition

IS30 IS33

IS30 IS31 IS33

IS11

IS10

IS20

IS26 IS25

IS40 IS40 IS45

IS21

SCL

SDA

Out

dsPIC30F1010/202X

TABLE 21-32: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Max Units Conditions

IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 1.3 — μs Device must operate at a

minimum of 10 MHz.

1 MHz mode(1) 0.5 — μs—

IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 — μs Device must operate at a

minimum of 10 MHz

1 MHz mode(1) 0.5 — μs—

IS20 TF:SCL SDA and SCL

Fall Time 100 kHz mode — 300 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 100 ns

IS21 TR:SCL SDA and SCL

Rise Time 100 kHz mode — 1000 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 300 ns

IS25 TSU:DAT Data Input

Setup Time 100 kHz mode 250 — ns —

400 kHz mode 100 — ns

1 MHz mode(1) 100 — ns

IS26 THD:DAT Data Input

Hold Time 100 kHz mode 0 — ns —

400 kHz mode 0 0.9 μs

1 MHz mode(1) 00.3μs

IS30 TSU:STA Start Condition

Setup Time 100 kHz mode 4.7 — μs Only relevant for repeated

Start condition

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.25 — μs

IS31 THD:STA Start Condition

Hold Time 100 kHz mode 4.0 — μs After this period the first

clock pulse is generated

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.25 — μs

IS33 TSU:STO Stop Condition

Setup Time 100 kHz mode 4.7 — μs—

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.6 — μs

IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns —

Hold Time 400 kHz mode 600 — ns

1 MHz mode(1) 250 ns

IS40 TAA:SCL Output V alid From

Clock 100 kHz mode 0 3500 ns —

400 kHz mode 0 1000 ns

1 MHz mode(1) 0 350 ns

IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free

before a new transmission

can start

400 kHz mode 1.3 — μs

1 MHz mode(1) 0.5 — μs

IS50 CBBus Capacitive

Loading — 400pF —

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).

dsPIC30F1010/202X

TABLE 21-33: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (± 10% )

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Device Supply

AD01 AVDD Module VDD Supply Greater of

VDD – 0.3

or 2.7

Lesser of

VDD + 0.3

or 5.5

V—

AD02 AVSS Module VSS Supply Vss – 0.3 VSS + 0.3 V —

Analog Input

AD10 VINH-VINL Full -Scale Input Sp an VSS VDD V—

AD11 VIN Absolute Input Voltage AVSS – 0.3 AVDD + 0.3 V —

AD12 — Leakage Current — ±0.001 ±0.244 μAV

INL = AVSS = 0V,

AVDD = 5V

Source Impedance = 1 kΩ

AD13 — Leakage Current — ±0.001 ±0.244 μAV

INL = AVSS = 0V,

AVDD = 3.3V

Source Impedance = 1 kΩ

AD17 RIN Recom m end ed Impedanc e

Of Analog Voltage Source —1KΩ—

DC Accuracy

AD20 Nr Resolution 10 data bits bits —

AD21 INL Integral Nonline ari ty — ± 0.5 < ±1 LSb V INL = AVSS = 0V

AVDD = 5V

AD21A INL Integral Nonl ine ari ty — ±0.5 < ± 1 LSb V INL = AVSS = 0V

AVDD = 3.3V

AD22 DNL Differential Nonlinearity — ±0.5 < ±1 LSb VINL = AVSS = 0V

AVDD = 5V

AD22A DNL Differential Nonlinearity — ±0.5 < ±1 LSb VINL = AVSS = 0V

AVDD = 3.3V

AD23 GERR Gain Error — ±0.75 <±4.0 LSb VINL = AVSS = 0V

AVDD = 5V

AD23A GERR Gain Error — ±0.75 <±3.0 LSb VINL = AVSS = 0V

AVDD = 3.3V

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

2: The A/D conversio n resul t neve r decre as es w ith an inc rea se in the inp ut vol t ag e, and has no miss in g

codes.

dsPIC30F1010/202X

FIGURE 21-20: A/D CONVERSI ON TIMING PER INPUT

AD24 EOFF Offset Error — ±0.75 <±2.0 LSb VINL = AVSS = VSS = 0V,

AVDD = VDD = 5V

AD24A EOFF Offset Error — ±0.75 <±2 .0 LSb VINL = AVSS = VSS = 0V,

AVDD = VDD = 3.3V

AD25 — Monotonicity(2) — — — — Guaranteed

Dynamic Performance

AD30 THD Total Harmonic Distortion -77 -73 -68 dB —

AD31 SINAD Signal to Noise and

Distortion —58—dB —

AD32 SFDR Spurious Free Dynamic

Range —-73—dB —

AD33 FNYQ Input Signal Bandwidth — — 0.5 MHz —

AD34 ENOB Effective Number of Bits — 9.4 — bits —

TABLE 21-33: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS (CONTINUED)

AC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (± 10% )

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

2: The A/D conversio n resul t neve r decre as es w ith an inc rea se in the inp ut vol t ag e, and has no miss in g

codes.

TAD

A/D Data

ADBUFxx

90 210

Old Data New Data

CONV

A/D Clock

Trigger Pulse

Tconv

dsPIC30F1010/202X

TABLE 21-34: COMPARATOR OPERATING CONDITIONS

Symbol Characteristic Min Typ Max Units Comments

VDD Voltage Range 3.0 — 3.6 V Operating range of 3.0 V-3.6V

VDD Voltage Range 4.5 — 5.5 V Operating range of 4.5 V-5.5 V

TEMP Temperature Range -40 — 105 °C Note that junction temperature can

exceed 125°C under these ambient

conditions.

TABLE 21-35: COMPARATOR AC AND DC SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operating temperature: -40°C ≤ TA ≤ +105°C

Symbol Characteristic Min Typ Max Units Comments

VIOFF Input offset voltage ±5 ±15 mV

VICM Input common mode

voltage range 0VDD –

1.5 V

VGAIN Open loop gain 90 db

CMRR Common mode rejection

ratio 70 db

TRESP Larg e signal response 20 30 ns V+ input st ep o f 100mv while V- input held

at AVDD/2. Delay measured from analog

input pin to PWM output pin.

TABLE 21-36: DAC DC SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operating temperature: -40°C ≤ TA ≤ +105°C

Symbol Characteristic Min Typ Max Units Comments

CVRSRC Input reference voltage 0 AVDD –

1.6 V

CVRES Resolution 10 Bits

INL

DNL

Transfer Function Accuracy

Integral Non-Linearity Error

Differential Non-Linearity

Error

Offset Error

Gain Error

—

±1

±0.8

±2

±2.0

LSB

AVDD = 5 V,

DACREF = (AVDD/2) V

Legend: TBD = To Be Determined

TABLE 21-37: DAC AC SPECIFICATIONS

Standard Operating Conditions (unle ss otherw is e stated)

Operating temperature: -40°C ≤ TA ≤ +125°C

Symbol Characteristic Min Typ Max Units Comments

TSET Settling Time 2.0 µs Measured when range = 1 (High

Range), and cmref<9:0> transitions

from 0x1FF to 0x300.

dsPIC30F1010/202X

NOTES:

dsPIC30F1010/202X

22.0 PACKAGE MARKING INFORMATION

XXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead PDIP (Skinny DIP) Example

XXXXXXXXXXXXXXXXX

0348017

dsPIC30F202X-30I/SP

28-Lead SOIC

YYWWNNN

Example

XXXXXXXXXXXXXXXXXXXX

XXXXXXXXXXXXXXXXXXXX 0348017

dsPIC30F202X-30I/SO

28-Lead QFN-S

XXXXXXX

YYWWNNN

Example

dsPIC30F1010

-30I/MM

040700U

44-Lead TQFP

XXXXXXXXXX

YYWWNNN

Example

dsPIC30F202X

-I/PT0510017

XXXXXXXXXX

44-Lead QFN

XXXXXXXXXX

YYWWNNN

dsPIC30F202X

Example

-I/ML

0510017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01 ’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

dsPIC30F1010/202X

28-Lead Plastic Quad Flat, No Lead Package (MM) - 6x6x0.9 mm Body (QFN-S)

With 0.40 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

NOTE 1 BOTTOM VIEW

TOP VIEW

EXPOSED

PAD

Number of Pins

Pitch

Overall Height

Standoff

Contact Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length §

Contact-to-Exposed Pad §

Units

Dimension Limits

0.80

0.00

3.65

0.23

0.30

0.20

0.65 BSC

0.90

0.02

0.20 REF

6.00 BSC

3.70

6.00 BSC

3.70

0.38

0.40

—

1.00

0.05

4.70

0.43

0.50

—

MIN NOM MAX

MILLIMETERS

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

3. Package is saw singulated

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04–124, Sept. 8, 2006

dsPIC30F1010/202X

28-Lead Skinny Plasti c Dual In-line (SP) – 300 mil Body (PDIP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

1510515105

Mold D raft An gl e Bottom 1510515105

Mold D raft An gl e Top 10.928.898.13.430.350.320

Overall Row Spacing

0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008

Lead Thicknes s 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOvera ll Length 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shoulder Width 0.38.015A1Base to Seat ing Plane 3.433.303.18.135.130.125A2Molded Package Thickness 4.063.813.56.160.150.140ATop to Se ating Plan e 2.54.100

Pitch 2828

Num ber of Pin s MAXNOMMINMAXNOMMINDime nsion Limits MILLIMETERSINCHES

Units

Notes:

JEDEC Equivalent: MO-095

Drawing No. C04-070

Controlling Para meter

Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

Significant C haracteris tic

dsPIC30F1010/202X

28-Lead Plasti c Small Outline (SO) – Wide, 300 mil Body (SOIC)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Foot Angle Top φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009

Lead Thickness

1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff §2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27

.050

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimensi on Limit s MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

§ Significant Characteristic

dsPIC30F1010/202X

44-Lead Plastic Thin Quad Flatp ack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

A1 A2

#leads=n1

D1 D

CH x 45°

1.140.890.64.045.035.025CH

Pin 1 Corner Chamfer

1.00 REF..039 REF.F

Footprint (Reference)

Units INCHES MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX

Number of Pins n44 44

Pitch p.031 0.80

Overall Height A .039 .043 .047 1.00 1.10 1.20

Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05

Standoff A1 .002 .004 .006 0.05 0.10 0.15

Foot Length L .018 .024 .030 0.45 0.60 0.75

Foot Angle

03.5 7 03.5 7

Overall Width E .463 .472 .482 11.75 12.00 12.25

Overall Length D .463 .472 .482 11.75 12.00 12.25

Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10

Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10

Pins per Side n1 11 11

Lead Thickness c.004 .006 .008 0.09 0.15 0.20

Lead Width B .012 .015 .017 0.30 0.38 0.44

Mold Draft Angle Top

5 10 15 5 10 15

Mold Dra ft An g le Bottom

5 10 15 5 10 15

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

Notes:

JEDEC Equivalent: MS-026 Revised 07-22-05

Controlling Parameter

REF: Reference Dimension, usually without tolerance, for information purposes only.

See ASME Y14.5M

Drawing No. C04-076

dsPIC30F1010/202X

44-Lead Plasti c Quad Flat, No Lead Package (ML) - 8x8 mm Body (QFN)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Number of Pins

Pitch

Overall Height

Standoff

Contact Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length §

Contact-to-Exposed Pad §

Units

Dimension Limits

0.80

0.00

6.30

0.25

0.30

0.20

0.65 BSC

0.90

0.02

0.20 REF

8.00 BSC

6.45

8.00 BSC

6.45

0.30

0.40

—

1.00

0.05

6.80

0.38

0.50

—

MIN NOM MAX

MILLIMETERS

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

3. Package is saw singulated

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04–103, Sept. 8, 2006

A3A1

TOP VIEW BOTTOM VIEW

NOTE 1

EXPOSED

PAD

dsPIC30F1010/202X

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microc hi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following informa-

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•Product Support – Da ta sheet s an d errata , appli-

cation note s and samp le prog ram s, des ig n

resources, user’s guides and hardware support

docume nts , latest softw are releas es and archived

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Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Microchip consul t a n t

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will receive e-mail notification whenever there are

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CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

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• Technical Support

Customers should contact their distributor, representa-

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Local sales offices are also available to help custom-

ers. A l isting of sal es offic es and locat ions is inc luded in

the back of this document.

Technic al suppo rt is avail able throug h the web si te

at: http://support.microchip.com

dsPIC30F1010/202X

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DS70178CdsPIC30F1010/202X

1. What are the best f eatures of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

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© 2006 Microchip Technology Inc. Preliminary DS70178C-page 275
dsPIC30F1010/202X
APPENDIX A: REVISION HISTORY
Revision A (June 2006)
• Initial release of this document.
Revision B (August 2006)
This r evision includes:
Updated  Section 5.0 “Interrupts” to include
INTTR EG regi ster .
Updated device configuration registers to include FBS
Boot Code  Segment  and FOSCEL O scillator Selectio n
configuration registers (see Section 18.10 “Device
Configuration Registers”).
Updated Electrical Characteristics:
•I
IDLE Parameter DC43f Max Value revised to 
87 ma (see Table 21-6)
Typographical corrections:
•
dsPIC30F1010/2020 Port Registers
 (see Table 6-1)
- TRISA SFR bit 9 corrected to “TRISA9”
- TRISD SFR Reset State correct ed to 
“0000 0000 0000 0011”
• dsPIC3 0F2 023  Port Registe r s (see  Table 6-2)
- TRISA SFR bit 0 corrected to “unused”
- PORTA SFR bit 0 corrected to “unused”
- LATA SFR bit 0 corrected to “unused”
- TRISD SFR bit 0 corrected to “TRISD0”
- PORTD SFR bit 0 correc ted to “RD0”
- LATD SFR bit 0 corrected to “LATD0”
- TRISD SFR reset state corrected to
“0000 0000 0000 0011”
• dsPIC30F1010/202X CNEN1 SFR reset state 
corrected to “0000 0000 0000 0000“
(see Table 6-3)
• PWMCONx (see Register 12-5) 
- Bit 13 description corrected to “TRGSTAT”
- Bit 10 description corrected to “TRGIEN”
• ALTDTRx (see Register 12-9)
- Bits 15-14 corrected to “unused”
• ADCPC1 (see Register 16-6)
- TRGSRC2<4:0 > correc ted  to inclu de bit 4
Revision C (November 2006)
This revision includes:
Update d RC, EC an d HS Cr ystal  operatin g frequencie s
for Industrial and Ex tended Temperatures.
Revised SPI section to reflect updated operating fre-
quencies (see Section 13.0 “Serial Peripheral Inter-
face (SPI)”).
Revised oscillator configurations (see Section 18.3
“Oscillator Configurations”).
Updated Electrial Characteristics:
• Supply voltage parameter DC11 minimum value 
changed to 3.0V (see Table 21-4)
• Operating current (IDD) (see Table 21-5)
• Idle cur rent (IIDLE) (see Table 21-6)
• I/O Pin Input specifications (see Table 21-8)
• I/O Pin Output specifications (see Table 21-9)
• External Clock Timing (see Figure 21-2 and 
Table 21-12)
• PLL Clock Timing (see Table 21-13)
• Internal RC Accuracy (see Table 21-15)
• Power-up Timer Period (see Table 2 1-18)

dsPIC30F1010/202X

NOTES:

© 2006 Microchip Technology Inc. Preliminary DS70178C-page 277
dsPIC30F1010/202X
INDEX
A
A/D....................................................................................169
Configuring Analog Port............................................188
A/D Control Regis ter (ADCON)..... ....... .......... ........... ........171
A/D Convert Pair Control Register #0 (ADCPC0).............175
A/D Convert Pair Control Register #1 (ADCPC1).............177
A/D Convert Pair Control Register #2 (ADCPC2).............179
A/D Port Config u ration  Regis te r (ADPCFG).....................174
A/D Statu s Register (A DSTAT)............ ................... ..........1 7 3
AC Characteristics............................................................240
Load Conditions...................... ....... .. .. .. .. .. .. ....... .. .. .. ..240
AC Temperature and Voltage Specifications....................240
ADC Register Map............................................................190
Address Generator Units ....................................................41
Alternate Vector Table........................................................51
Analog Comparator Control Register Map........................195
Assembler
MPASM Assembler...................................................228
Automatic Clock Stretc h....................................................156
During 10-bit Addressing (STREN = 1).....................156
During 7-bit Addressing (STREN = 1).......................156
Receive Mode...........................................................156
Transmit Mode... .............................. ....................... ..156
B
Band Gap Start-up Time
Requirements............................................................248
Timing Cha racteris tics .. .......... ........... .......................248
Barrel Shifter.......................................................................27
Baud Rate Error Calculation (BRGH = 0) .........................162
Bit-Reversed Add ressing.... ............... ......................... ........45
Example......................................................................45
Implementation ...........................................................45
Modifier Values (table )........ ................... .....................46
Sequence Table (16-Entry)....................................... ..46
Block Diagrams
16-bit Timer1 Module..................................................88
DSP Engine............ ................................. ...................24
dsPIC30F1010............................................................10
dsPIC30F2020............................................................13
dsPIC30F2023............................................................16
External Power-on Reset Circuit...............................212
I2C.............................................................................154
Input Capture Mode.............. .. ....... .. .... .. .. .... ..... .... .. .. ..97
Oscillator System......................................................198
Output Co mpa re Mode ....... ............... ................... ....1 0 1
Reset System..... .............................. ................... ......210
Shared Po rt Structure........................ .........................7 7
SPI............................................................................146
UART........................................................................161
C
C Compilers
MPLAB C18. ............... ................... ...........................22 8
MPLAB C30. ............... ................... ...........................22 8
CLKO and I/O Timing
Characteristics..........................................................245
Requirements............................................................245
Code Examples
Erasing a Row of Program Memory............................83
Initiating a Programming Sequence..... .... .... ......... .... ..84
Loading Write Latches............................. .. .. ....... .. .. .. ..84
Code Protection ................................................................197
Comparat or Con tr o l Register (CMPCONx)............. .......... 193
Comparator DAC Control Registerx (CMPDACx)............. 194
Config u ring Analog Port Pins........... ............................. ...... 78
Control Reg i s te rs................ ........... .............. ..................... .. 82
NVMADR.................................................................... 82
NVMADRU ................................................................. 82
NVMCON.................................................................... 82
NVMKEY .................................................................... 82
Core Architecture
Overview..................................................................... 19
Core Register Map........................................................ 37, 38
Customer Change Notification Service............................. 273
Custome r Notification  Se rvice ........................ .............. .... 273
Customer Support............................ ...... .... ........... .... .... .... 273
D
Data Access from Program Memory Using 
Program Space Visibility............................................. 32
Data Accumulators and Adder/Subtracter.......................... 25
Data Space Write Saturation............ .......................... 27
Overflow and Saturation......................................... .... 25
Round Logic ............................................................... 26
Write Back.................................................................. 26
Data Addre ss Space............. .............................. ................ 33
Alignment.................................................................... 36
Alignment (Figure)...................................................... 36
MCU and DSP (MAC Class) Instructions . .................. 35
Memory Map......................................................... 33, 34
Near Data Space........................................................ 37
Softwar e  Stack ... ............... ......................................... 37
Spaces........................................................................ 36
Width .......................................................................... 36
DC Characteristics
I/O Pin Input Specifications ........................ .... .. .... .. .. 238
I/O Pin Outpu t Specification s......... ........... ................ 239
Idle Current (IIDLE).................................................... 235
Operating Current (IDD) ............................................ 233
Power-Down Current (IPD)........................................ 237
Program and EEPROM ............................................ 239
Development Support....................................................... 227
Device Configuration Register Map.................................. 218
Device Configuration Registers........................................ 215
Device Overview................................................................... 9
Divide Support.................. .... .. ....... .... .. .... .. ....... .... .. .... .. .... .. 22
DSP Engine..... .................................. ....................... .......... 23
Multiplier..................................................................... 25
dsPIC30F2020 Block Diagram ........................................... 13
Dual Output Compare Match Mod e....... ............... ............ 102
Contin u ous  Pu lse Mode ........ ............................. ...... 102
Single Pulse Mode.................................................... 102

dsPIC30F1010/202X
DS70178C-page 278 Preliminary © 2006 Microchip Technology Inc.
E
Electrical Characteristics...................................................231
AC.............................................................................240
Equations
I2C.............................................................................158
Relationship Between Device and SPI 
Clock Speed......................................................148
UART Baud Rate with BRGH = 0 .............................162
UART Baud Rate with BRGH = 1 .............................162
Errata ....................................................................................8
External Clock Input..........................................................207
External Clock Timing Characteristics
Type A, B and C Timer .............................................249
External Clock Timing Requirements. ...............................241
Type A Time r .................. ................................. .........249
Type B Time r .................. ................................. .........250
Type C Timer..... ............... ............................. ...........250
External Interrupt Requests ................................................51
F
Fast Context Saving............................................................51
Firmware Instructions........................................................219
Flash Pr o g ram Memory..................... ..................................81
In-Circuit Serial Programming (ICSP).........................81
Run-Time Self-Programming (RTSP).........................81
Table Instruction Operation Summary........................81
I
I/O Pin Specifications
Input..........................................................................239
Output .......................................................................239
I/O Ports........ .................................. ....................... .............77
Paral l e l  I/O (PIO)................. ................... .....................77
I2C.....................................................................................153
I2C 10-bit Slave Mode Operation......................................155
Reception..................................................................155
Transmission.............................................................155
I2C 7-bit Slave Mode Operation........................................155
Reception..................................................................155
Transmission.............................................................155
I2C Master Mode
Baud Rate Generator................................................158
Clock Arbitration........................................................158
Multi-Master Communication, Bus Collision 
and Bus Arbitration .................................. .........158
Reception..................................................................157
Transmission.............................................................157
I2C Module
Addresses.................................................................155
Bus Data Timing Characteristics
Master Mode.....................................................259
Slave Mode.......................................................261
Bus Data Timing Requirements
Master Mode.....................................................260
Slave Mode.......................................................262
Bus Start/Stop Bits Timing Characteristics
Master Mode.....................................................259
Slave Mode.......................................................261
General Call Address Support ..................................157
Interrupts...................................................................156
IPMI Support............................................ ...... .... .......157
Master Operation......................................................157
Master Support .........................................................157
Operating Function Description ................................153
Operation During CPU Sleep and Idle Modes..........158
Pin Configuration...................................................... 153
Programm er’s Model ................................................ 153
Registers .................................................................. 153
Slope Control............................................................ 157
Software Controlled Clock Stretching (STREN = 1). 156
Various Modes...................... .. ....... .... .. .. .... .. ....... .... .. 153
I2C Registe r Map.............................................................. 159
Idle Current (IIDLE)............................................................ 235
In-Circuit Debugger ........................................................... 217
In-Circuit Serial Programming (ICSP)...............................197
Initialization Condition for RCON Register Case 1 ........... 213
Initialization Condition for RCON Register Case 2 ........... 213
Input Capture (CAPX) Timing Characteristics ................ .. 251
Input Capture Interrupts...................................................... 99
Input Capture Module......................................................... 97
Simple Capture Event Mode ....................................... 98
Sleep and Idle Modes......... .... ..... .. .... .. .. .. .... ..... .. .... .. .. 99
Input Capture Register Map.............................................. 100
Input Capture Timing Requirements................................. 251
Input Change Notification ................................................... 78
Input Change Notification Register Map............................. 80
Instruction Addressing Modes ............................................ 41
File Register Instructions............................................ 41
Fundamental Modes Supported .............. .... ....... .. .... .. 41
MAC Instru ctions................ ................... ............... ...... 42
MCU Instru ction s................ .............................. .......... 4 2
Move and Accumulator Instructions ............................ 42
Other Ins tructions .................................... ................... 42
Instruction Set................................................................... 219
Instruction Set Overview................................................... 222
Inter-Integrated Circuit. See I2C
Internal Clock Timing Examples....................................... 242
Inter n e t Ad d ress .. .................................. ....................... .... 273
Interrupt Control and Status Register (INTTREG).............. 74
Interrupt Control Register 1 (INTCON1)............................. 52
Interrupt Control Register 2 (INTCON2)............................. 54
Interrupt Controller Register Map ....................................... 75
Interrupt Enable Control Register 1 (IEC1)......................... 61
Interrupt Enable Control Register 2 (IEC2)......................... 62
Interrupt Flag Status Register 0 (IFS0)............................... 55
Interrupt Flag Status Register 1 (IFS1)............................... 57
Interrupt Flag Status Register 2 (IFS2)............................... 58
Interrupt Priority.................................................................. 48
Interrupt Priority Control Register 0 (IPC0)......................... 63
Interrupt Priority Control Register 1 (IPC1)......................... 64
Interrupt Priority Control Register 10 (IPC10)..................... 73
Interrupt Priority Control Register 2 (IPC2)......................... 65
Interrupt Priority Control Register 3 (IPC3)......................... 66
Interrupt Priority Control Register 4 (IPC4)......................... 67
Interrupt Priority Control Register 5 (IPC5)......................... 68
Interrupt Priority Control Register 6 (IPC6)......................... 69
Interrupt Priority Control Register 7 (IPC7)......................... 70
Interrupt Priority Control Register 8 (IPC8)......................... 71
Interrupt Priority Control Register 9 (IPC9)......................... 72
Interrupt Sequence ............................................................. 51
Interrupt Stack Frame................................................. 51
Interrupts............................................................................. 47
Traps .......................................................................... 49
L
Leading Edge Blanking Control Register (LEBCONx). ..... 120
Linear Feedback Register (LFSR).................................... 202
Load Conditions................................................................ 240

© 2006 Microchip Technology Inc. Preliminary DS70178C-page 279
dsPIC30F1010/202X
M
Memory Organization..........................................................29
Microc h i p  In ternet  Web Site........ .............................. ........2 7 3
Modulo Addressing .............................................................43
Applicability.................................................................45
Operation Example.....................................................44
Start and End Address................................................43
W Addres s Reg ister Selec tio n... .............. ............... ....43
MPLAB ASM30 Assembler, Linker, Librarian ...................228
MPLAB ICD 2 In-Circuit Debugger ...................................229
MPLAB ICE 2000 High-Perform ance Universal 
In-Circuit Emulator....................................................229
MPLAB Integrated Development Environment Software..227
MPLAB PM3 Device Programmer ....................................229
MPLAB REA L  IC E In -Circuit Emula to r System.................229
MPLINK Object Linker/MPLIB Object Librarian...... ..........228
N
NVM Registe r  Map........ .............. ............... .........................85
O
OC/PWM Module Timing Characteristics..........................252
Operating Current (IDD).....................................................233
Oscillator
Syste m Over view.... ................... ............................. ..197
Oscillator Configurations...................................................205
Fail-Safe Clock Monitor.............................................208
Initial Clock Source Selection...................................206
Phase Locked Loop (PLL) .................................... .. ..206
Start- u p  Timer (OST )...... ....................... ...................2 0 6
Oscillator Control Register (OSCCON).............................199
Oscillator Selection...........................................................197
Oscillator Selection Configuration Bits (FOSC) ................204
Oscillator Selection Configuration Bits (FOSCSEL)..........203
Oscillator Start-up Timer
Timing Cha racteris tics .. .......... ........... .......................246
Timing Requirements............................... .. ....... .. .. ....247
Oscillator Tuning Register (OSCTUN)..............................201
Oscillator Tuning Register 2 (OSCTUN2).........................202
Output Co mpa re Interrupts.................... .............. .............104
Output Compare Module.............................. .. .. .... ....... .. ....101
Timing Cha racteris tics .. .......... ........... .......................251
Timing Requirements............................... .. ....... .. .. ....251
Output Compare Operation During CPU Idle Mode..........103
Output Co mpa re Register  Map.................... .....................105
Output Compare Sleep Mode Operation ..........................103
P
Packaging Information
Marking.....................................................................267
PICSTART Plus Development Programmer.....................230
Pinout Descriptions..................... .. ....... .... .. .... .. .. .....11, 14, 17
PLL Clock Timing Specifications .......................................242
POR. See Power-on Reset
Port Register Map (dsPIC30F1010/2020)...........................79
Port Register Map (dsPIC30F2023)....................................80
Port Write/Read Example ...................................................78
Power Supply PWM................ .... .... ......... .... .... ........... .... ..107
Power Supply PWM Module
Timing Requirements............................... .. ....... .. .. ....253
Power Supply PWM Register Map....................................142
Power-Down Current (IPD)................................................237
Power-on  Res e t (POR)............. ................... ................... ..197
Oscillator Start-up Timer (OST)................................197
Power-up  Timer (PWRT) .. ............... ............... ..........1 9 7
Power-Saving Modes.................................................... .... 214
Idle............................................................................ 215
Sleep ........................................................................ 214
Power-Saving Modes (Sleep and Idle)............................. 197
Power-up Timer
Timing Ch a rac te rist ics.... ............... ............... ............ 246
Timing Re q uirements ..... ................... ................... .... 247
Primary Time Base Register (PTPER) ............................. 111
Product Identification System........................................... 283
Program Address Space..................................................... 29
Construction ............................................................... 30
Data Access from Program Memory Using 
Table Ins tructions........................... .................... 31
Data Acce ss  fr o m, Address Gener a tion..... .............. .. 30
Memory Map............................................................... 29
Table Instructions
TBLRDH............................................................. 31
TBLRDL.............................................................. 31
TBLWTH............................................................. 31
TBLWTL ............................................................. 31
Program and EEPRO M Charac terist ics ............................ 239
Program Counter................................................................ 20
Program Data Table Access.......... ................... .................. 32
Program Space Visibility
Window into Program Space Operation ....... .. .... .. .. .... 33
Programm er’s Model .......................................................... 20
Diagram...................................................................... 21
Programming Opera tio n s.... ......................... ................... .... 83
Algor ith m for Progr a m Flash..................... .................. 83
Erasing a Row of Program Memory ........................... 83
Initiating the Programming Sequence ........................ 84
Loading Write Latches............. .. .. .... .. .. ..... .. .... .. .. .. .. .. .. 84
Programming, Device Instructions.................................... 219
PWM Alternate Dead-Time Register (ALTDTRx)............. 115
PWM Control Register (PWMCONx).................. .......... .... 112
PWM Dead-Time Register (DTRx)............................. ...... 114
PWM Fault Current-Limit Control Register (FCLCONx)... 117
PWM I/O Control Register (IOCONx)............................... 116
PWM Master Duty Cycle Register (MDC)......................... 112
PWM Phase-Shift Re g i s te r (PHASEx)..... ................... ...... 114
PWM Time Base Control Register (PTCON).................... 110
PWM Trigger Compare Value Register (TRIGx) .............. 119
PWM Trigger Control Register (TRGCONx)..................... 115
R
Reader Response............................................................. 274
Register Map
ADC Registe r........ ................... ................... .............. 190
Analog Compara tor Control Register ........... .......... .. 195
Core Registers............................................................ 38
Device Configuration Register.................................. 218
I2C Registe r.............................................................. 159
Input Capture Registers............................................ 100
Input Change Notification Registers........................... 80
Interrupt Controller Registers ..................................... 75
NVM Regist e rs . .............. ................... ............... .......... 85
Output Com p a re Register s................ ............... ........ 105
Port Registers (dsPIC30F1010/2020) ........................ 79
Port Registers (dsPIC30F2023) . ................................ 80
Power Supply PWM Registers ................................. 142
SPI1 Register ........................................................... 152
System Integration Register (dsPIC30F202X ) ......... 218
Timer 1 Registers....................................................... 90
Timer2 /3  Re g i sters...................... ................... ............ 95
UART1 Register ....................................................... 168

dsPIC30F1010/202X
DS70178C-page 280 Preliminary © 2006 Microchip Technology Inc.
Registers
ADCON.....................................................................171
ADCPC@..................................................................179
ADCPC0 ...................................................................175
ADCPC1 ...................................................................177
ADPCFG...................................................................174
ADSTAT....................................................................173
ALTDTRx ..................................................................115
CMPCONx ................................................................193
CMPDACx.................................................................194
DTRx.........................................................................114
FCLCONx .................................................................117
FOSC........................................................................204
FOSCSEL.................................................................203
IEC1............................................................................61
IEC2............................................................................62
IFS1 ............................................................................57
IFS2 ............................................................................58
IFSO............................................................................55
INTCON1 ....................................................................52
INTCON2 ....................................................................54
INTTREG ....................................................................74
IOCONx ....................................................................116
IPC0............................................................................63
IPC1............................................................................64
IPC10..........................................................................73
IPC2............................................................................65
IPC3............................................................................66
IPC4............................................................................67
IPC5............................................................................68
IPC6............................................................................69
IPC7............................................................................70
IPC8............................................................................71
IPC9............................................................................72
LEBCONx .................................................................120
LFSR.........................................................................202
MDC..........................................................................112
OSCCON ..................................................................199
OSCTUN...................................................................201
OSCTUN2.................................................................202
PHASEx....................................................................114
PTCON .....................................................................110
PTPER......................................................................111
PWMCONx ...............................................................112
SEVTCMP.................................................................111
SPIxCON1 (SPIx Control 1)......................................150
SPIxCON2 (SPIx Control 2)......................................151
SPIxSTAT (SPIx Status and Control) .......................149
TRGCONx.................................................................115
TRIGx........................................................................119
U1MODE...................................................................164
U1STA ......................................................................166
Reset.........................................................................197, 209
Reset Sequence.............................. .. .... ....... .... .... .. .... .........49
Reset Sources ..... ................... ................... .................49
Reset Timin g  Char acteris tic s...... ...... ........... .............. .......246
Reset Timing Requirements................................... .. .... .....247
Resets
POR..........................................................................211
POR with Long Crystal Start-up Time.......................212
POR, Operating without FSCM and PWRT ......... .....212
RTSP Operation..................................................................82
S
Sales and Support........................ .. ....... .... .. .... .. .. ......... .. .. 282
Serial Peripheral Interface (SPI)....................................... 145
Simple Capture Event Mode
Capture Bu ffer Operation.. .............................. ............ 98
Capture Prescaler....... ............................. ................... 98
Hall Sensor Mode............... ........... .............. ............... 98
Input Capture in CPU Idle Mode................................. 99
Timer2 and Timer3 Selection Mode...................... .... .. 98
Simple OC/PWM Mode Timing Requirements ................. 252
Simp le  Outp ut Co mp a re Ma tc h Mo d e ........ ...... ..... .......... . 102
Simple PWM Mode........................................................... 102
Period ....................................................................... 103
Softwar e  Simulat or ( MP L AB SIM) ............... ................... ..228
Softwar e  Stack Poin ter, Fram e  Poin te r ......... ..................... 2 0
CALL Stack Fr a me.................... .............. ................... 37
Special Event Compare Register (SEVTCMP)................. 111
SPI Master, Frame Mast er Connection........................... 147
Master/Slave Connection.................................. .... .. .. 147
Slave, Frame Master Connection............................. 148
Slave, Frame Slave Connection............................... 148
SPI Mode
SPI1 Register Map.................................................... 152
SPI Module
Timing Characteristics
Master Mode (CKE = 0). ................................... 254
Master Mode (CKE = 1). ................................... 255
Slave Mode (CKE = 1).............................. 256,  257
Timing Requirements
Master Mode (CKE = 0). ................................... 254
Master Mode (CKE = 1). ................................... 255
Slave Mode (CKE = 0)..................... ............... .. 256
Slave Mode (CKE = 1)..................... ............... .. 258
SPI1 Register Map............................................................ 152
STATUS Regi ster.... .............................. ................... .......... 2 0
Symbols used in Opcode Descriptions............................. 220
System Integration............................................................ 197
System Integration Register Map (dsPIC30F202X ).......... 218
T
Temperature and Voltage Specifications
AC............................................................................. 240
Timer1 Module.................................................................... 87
16-bit Asynchronous Counter Mode........................... 87
16-bit Synchronous Counter Mode............................. 87
16-bit Timer Mode.......................... ............................. 87
Gate Operation........................................................... 88
Interrupt ...................................................................... 89
Operation During Sleep Mode.................................... 88
Prescaler .................................................................... 88
Timer1 Register Map.......................................................... 90
Timer2 and Timer3 Selection Mode............................ .. ....102
Timer2/3 Module................... .. .... .. ....... .... .. .. .... .. .. ....... .... .. .. 91
16-bit Timer Mode.......................... ............................. 91
32-bit Synchronous Counter Mode............................. 91
32-bit Timer Mode.......................... ............................. 91
ADC Event Trigger.................................................... .. 94
Gate Operation........................................................... 94
Interrupt ...................................................................... 94
Operation During Sleep Mode.................................... 94
Timer Prescaler .......................................................... 94
Timer2 /3  Re g i ster Map............. ................... ................... .... 95

© 2006 Microchip Technology Inc. Preliminary DS70178C-page 281
dsPIC30F1010/202X
Timing Characteristics
A/D Conversion
10-Bit High-speed (CHPS = 01, 
SIMSAM = 0, ASAM = 0, SSRC = 000)....264
Band Gap Start-up Time...........................................248
CLKO and I/O ...........................................................245
External Clock...........................................................240
I2C Bus Data
Master Mode.....................................................259
Slave Mode.......................................................261
I2C Bus Start/Stop Bits
Master Mode.....................................................259
Slave Mode.......................................................261
Input Capture (CAPX)............................ .... .. ....... .... ..251
Motor Control PWM Module......................................253
Motor Control PWM Module Falult............................253
OC/PWM Module. .....................................................252
Oscillator Start-up Timer...........................................246
Output Co mpa re Module.................. ................... ......251
Power-up  Timer ........ .............. .......................... ........24 6
Reset.........................................................................246
SPI Module
Master Mode (CKE = 0)....................................254
Master Mode (CKE = 1)....................................255
Slave Mode (CKE = 0)......................................256
Slave Mode (CKE = 1)......................................257
Type A, B and C Timer External Clock.....................249
Watchdog Timer...................... ....... .. .. .... .. .... ..... .... .. ..246
Timing Diagrams
PWM Output......... ............................. .......................104
Time-out Sequence on Power-up (MCLR 
Not Tied to VDD), Case 1..................................211
Time-out Sequence on Power-up (MCLR 
Not Tied to VDD), Case 2..................................212
Time-out Sequence on Power-up (MCLR Tied 
to VDD)..............................................................211
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy...............242
Timing Diagrams.See Timing Characteristics
Timing Requirements
Band Gap Start-up Time...........................................248
Brown-out Reset.......................................................247
CLKO and I/O ...........................................................245
External Clock...........................................................241
I2C Bus Data (Master Mode) .....................................260
I2C Bus Data (Slave Mode).......................................262
Input Capture.......................... ....... .... .. .... .. .. ....... .... ..251
Motor Control PWM Module......................................253
Oscillator Start-up Timer...........................................247
Output Co mpa re Module.................. ................... ......251
Power-up  Timer ........ .............. .......................... ........24 7
Reset.........................................................................247
Simple OC/PWM Mode.............................................252
SPI Module
Master Mode (CKE = 0)....................................254
Master Mode (CKE = 1)....................................255
Slave Mode (CKE = 0)......................................256
Slave Mode (CKE = 1)......................................258
Type A Time r Ex ternal Clo c k................. ...................249
Type B Time r Ex ternal Clo c k................. ...................250
Type C Timer Ext e rnal Clock............... ............... ......250
Watchdog Timer...................... ....... .. .. .... .. .... ..... .... .. ..247
Timing Specifications
PLL Clock..................................................................242
Traps
Trap Sources . .................................. ....................... ....4 9
U
UART
Baud Rate Generator (BRG) .................................... 162
Enabling and Setting Up UART................ .. .. .... .. .. .. .. 162
IrDA Built-in Encoder and Decoder........................... 163
Receiving
8-bit or 9-bit Data Mode .................................... 163
Transmitting
8-bit Data Mode................................................ 163
9-bit Data Mode................................................ 163
Break and Sync Sequence............................... 163
UART1 Mode Register (U1MODE )................................... 164
UART1 Register Map........................................................ 168
UART1 Status and Control Register (U1STA).................. 166
Unit ID Locations.............................................................. 197
Universal Asynchronous Receiver Transmitter. See UART
W
Wake-up from Sleep......................................................... 197
Wake-up from Sleep and Idle............................................. 51
Watchdog Timer
Timing Ch a rac te rist ics.... ............... ............... ............ 246
Timing Re q uirements ..... ................... ................... .... 247
Watchdog Timer (WDT)..................... .. .... .... ....... .. .... 197, 214
Enabling and Disabling............................................. 214
Operation.................................................................. 214
WWW Addres s..................... .................................. .......... 273
WWW, On-Line Support....................................................... 8

dsPIC30F1010/202X

NOTES:

dsPIC30F1010/202X

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

dsPIC30F2020AT-30 I/ SO-ES

Example:

dsPIC30F2020AT-30I/SO = 30 MIPS, Industrial temp., SOIC package, Rev. A

Trademark

Architecture

Flash

E = Extended High Tem p -40°C to +125°C

I = Industrial -40°C to +85°C

Temperature

Device ID

Package

MM = QFN

PT = TQFP

SP = SPDIP

SO = SOIC

S = Die (Waf fl e Pack)

W = Die (Wafers)

Memory Size in Bytes

0 = ROMless

1 = 1K to 6K

2 = 7K to 12K

3 = 13K to 24K

4 = 25K to 48K

5 = 49K to 96K

6 = 97K to 192K

7 = 193K to 384K

8 = 385K to 768K

9 = 769K and Up

Custom ID (3 digits) or

T = Tape and Reel

A,B,C… = Revision Level

Engineering Sample (ES)

Speed

20 = 20 MIPS

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10/19/06

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dsPIC30F1010-20E/MM dsPIC30F1010-20E/SO dsPIC30F1010-20E/SP dsPIC30F1010-30I/MM dsPIC30F1010-

30I/SO dsPIC30F1010-30I/SP dsPIC30F1010T-30I/MM dsPIC30F1010T-30I/SO dsPIC30F2020-20E/MM

dsPIC30F2020-20E/SO dsPIC30F2020-20E/SP dsPIC30F2020-30I/MM dsPIC30F2020-30I/SO dsPIC30F2020-

30I/SP dsPIC30F2020T-30I/MM dsPIC30F2020T-30I/SO dsPIC30F2023-20E/ML dsPIC30F2023-20E/PT

dsPIC30F2023-30I/ML dsPIC30F2023-30I/PT dsPIC30F2023T-30I/ML dsPIC30F2023T-30I/PT AC164335

AC164336 AC164337 DSPIC30F1010-20E/MM DSPIC30F1010-20E/SO DSPIC30F1010-20E/SP DSPIC30F1010-

30I/MM DSPIC30F1010-30I/SO DSPIC30F1010-30I/SP DSPIC30F1010T-30I/MM DSPIC30F2020-20E/MM

DSPIC30F2020-20E/SO DSPIC30F2020-20E/SP DSPIC30F2020-30I/MM DSPIC30F2020-30I/SO DSPIC30F2020-

30I/SP DSPIC30F2020T-30I/MM DSPIC30F2020T-30I/SO DSPIC30F2023-20E/ML DSPIC30F2023-20E/PT

DSPIC30F2023-30I/ML DSPIC30F2023-30I/PT DSPIC30F2023T-30I/ML DSPIC30F2023T-30I/PT