TSC695 Evaluation Kit - Atmel Corporation

Rev. 1.1 - 22 March, 2001 Application Lab 1

APPLAB/GB/00/010

Getting Started with

the TSC695 Evaluation Kit

2 Rev. 1.1 - 22 March, 2001
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Table of Contents
TSC695 evaluation kit contents ...................................................3
Supported platforms ............................................................3
Getting started with the evaluation kit ..............................................3
Installing the software development package ........................................3
Connecting the serial links .......................................................4
Connecting the power supply .....................................................4
Compiling and linking your program ..............................................4
Opening the application terminal window ...........................................5
Transfering the executable file to the board RAM ....................................5
Remote debugging your program .................................................5
Using the TSC695 VHDL Model .................................................6
CDROM Organization ..........................................................7
Where to go from here ..........................................................7

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1. TSC695 evaluation kit contents

The TSC695 starter kit contains the following parts:

●Evaluation board equipped with:

•TSC695

•4Mbytes RAM and 512Kbytes FLASH containing the rdbmon monitor program

●Documentation

•Getting Started with the TSC695 Evaluation Kit

●CDROM (see the Section "CDROM Organization", page 7)

•ESA/ESTEC ERC32CCS software package (V2.0.6 release - gzipped tar file)

including software tools documentation (PDF format)

•Compiled TSC695 VHDL structural model and related files

•TSC695 BSDL file

•TSC695 evaluation board EDIF netlist

•TSC695 documentation (PDF format)

-TSC695 Data Sheet

-TSC695 User’s Manual

- Evaluation board "Hardware User’s Manual"

- Getting Started with the TSC695 Evaluation Kit

2. Supported platforms

The ERC32CCS package only supports Solaris 2 operating system running on a SUN platform.

3. Getting started with the evaluation kit

To get software running on the TSC695 evaluation board, you will follow these steps (detailed in the next paragraphs):

1. Install the ESA/ESTEC ERC32CCS software development package from the CDROM on your Solaris platform.

2. Connect the evaluation board serial connectors A and B to the Solaris platform serial ports.

3. Connect the evaluation board to a 5V / 2A DC power supply.

4. Compile and link your program.

5. Transfer your program executable file to the evaluation board RAM.

6. Debug/Run your program on board with GDB and its graphical user interface DDD.

4. Installing the software development package

The ERC32CCS directory tree is compiled to reside in /opt/gnu on Solaris platforms. If the installation directory

is not /opt/gnu, then you will have to create a link to the location of the ERC32CCS directory after installation.

1. Copy the erc32ccs-2.0.6-solaris.tar.gz file from the CDROM to your disk.

2. Un-compress and un-tar the file.

3. Create the link:

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Solaris1> cd /opt/gnu

Solaris1> ln -s <install_dir>/erc32ccs-2.0.6-solaris/erc32 erc32

4. Add /opt/gnu/erc32/bin to your search path.

5. Connecting the serial links

Connect the board J10 connector to the Solaris platform serial port Aand the J11 one to the platform serial port B.

The Solaris platform port A will be used to establish a full-duplex connection with the board UART-A; this

connection will allow the application running on the evaluation board to display output.

The Solaris platform port B will be used by GDB to communicate with RDBMON, the evaluation board monitor

program.

6. Connecting the power supply

Connect the board to a 5V-2A DC power supply as follows:

J28-C to VCC,J20-C to GND.

7. Compiling and linking your program

Compile and link your application program as follows:

Solaris1> sparc-rtems-gcc -g -O3 application.c -o application

Solaris Platform J10

J11

application

output

messages

DDD/GDB

window

uses port A uses port B

TSC695

RDBMON

5V-2A DC

J28 J20

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8. Opening the application terminal window

You must open a terminal window on the Solaris platform so that your application can display results. You do

this with the command:

Solaris1> xterm -e tip -19200 /dev/ttya &

9. Transfering the executable file to the board RAM

You may load and debug your application through GDB only, but working with GDB through DDD is much more

easier.

To start DDD with the debugger, use:

Solaris1> ddd --debugger sparc-rtems-gdb --no-data-window --attach-source-window

<your_application>

A script, dddx is provided to start DDD in this configuration. Use dddx as follows:

Solaris1> dddx <your_application>

You may also type dddx only and then specify the application to be loaded with the DDD File > Open Program...

command.

10. Remote debugging your program

You should now have two windows opened to debug your application: a terminal window and a DDD one.

Reset the board with the S1 RESET switch. The terminal window should display:

ERC32 boot loader v1.0

initializing RAM

loading .text

loading .data

starting mon

In the DDD command window, perform the following steps:

(gdb) set remotebaud 19200

(gdb) target erc32 /dev/ttyb

Remote debugging using /dev/ttyb

0x2000000 in ?? ()

(gdb) load

Loading section .text, size 0x69a0 vma 0x2000000

Loading section .data, size 0x530 vma 0x20069a0

(gdb)

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You are now ready for a remote debugging session. The following figure shows a session example:

(gdb) run

11. Using the TSC695 VHDL Model

The starter kit contains a precompiled VHDL model of the TSC695 device. The model has been compiled for use

with the ModelSim V5.2e VHDL simulator. The model is already back-annotated by a SDF file in typical conditions

(5V, 25C).

Before using the model, you must copy the VITAL libraries and the modelsim.ini file from the CDROM; then,

modify the modelsim.ini file so that it fits with the libraries installation directory path.

For the VHDL model to operate properly, you must force some internal nets for a few cycles. A bus called D_INIT

(33 bits wide) is declared in the model entity. This bus is for the TSC695 VHDL model initialization purpose only;

there is no D_INIT bus on the device.

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When writing your VHDL test bench or the VHDL description of the TSC695 hardware environment, you must

declare a S_D_INIT 33-bit wide std_logic_vector signal that you will connect to the D_INIT one in the instanciation

part of your VHDL design. You then add the following three lines to your startup.do file, or you keep them in a

standalone file that you load on demand (but always at the very beginning of the simulation session).

force -freeze /<test_bench_entity>/S_D_INIT 16#0

run <10 cycles periods>

force -freeze /<test_bench_entity>/S_D_INIT 16#Z

If the system clock period is 100ns, the run statement is: run 1000ns.

S_D_INIT is a suggestion for the signal name; you may use any other signal name.

12. CDROM Organization

The CDROM is organized as follows:

/BSDL contains the TSC695 BSDL file

/EDIF contains the TSC695 evaluation board EDIF netlist

/ESA_ESTEC_CCS contains the V2.0.6 ESA/ESTEC cross compiler software package

/Patches contains files to patch the CCS package

README_FIRST file

/VHDL contains the TSC695 VHDL model and related files

/doc contains the TSC695 data sheet, the TSC695 User’s Manual, the TSC695 Hardware User’s Manual and this

Getting Started manual. All these files are released in PDF format.

13. Where to go from here

The /opt/gnu/erc32/doc directory contains the DDD,GDB and GCC manuals in pdf format.

You should also read the TSC695 User’s Manual and Data Sheet as well as the evaluation board User’s Manual

which describes the numerous capabilities of the evaluation hardware.