IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
OptiMOS®2 Power-Transistor
Features
• Ideal for high-frequency dc/dc converters
• Qualified according to JEDEC1) for target application
• N-channel, logic level
• Excellent gate charge x RDS(on) product (FOM)
• Superior thermal resistance
• 175 °C operating temperature
• Pb-free lead plating; RoHS compliant
Maximum ratings, at Tj=25 °C, unless otherwise specified
Parameter Symbol Conditions Unit
Continuous drain current IDTC=25 °C2) 50 A
TC=100 °C 45
Pulsed drain current ID,pulse TC=25 °C3) 350
Avalanche energy, single pulse EAS ID=45 A, RGS=25 Ω75 mJ
Reverse diode dv/dtdv/dt
ID=50 A, VDS=20 V,
di/dt=200 A/µs,
Tj,max=175 °C
6 kV/µs
Gate source voltage4) VGS ±20 V
Power dissipation Ptot TC=25 °C 63 W
Operating and storage temperature Tj, Tstg -55 ... 175 °C
IEC climatic category; DIN IEC 68-1 55/175/56
Value
VDS 25 V
RDS(on),max (SMD version) 8.6 mΩ
ID 50 A
Product Summary
Type IPD09N03LA IPF09N03LA IPS09N03LA IPU09N03LA
Package P-TO252-3-11 P-TO252-3-23 P-TO251-3-11 P-TO251-3-21
Marking 09N03LA 09N03LA 09N03LA 09N03LA
Rev. 2.12 page 1 2008-04-14
IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
Parameter Symbol Conditions Unit
min. typ. max.
Thermal characteristics
Thermal resistance, junction - case RthJC - - 2.4 K/W
SMD version, device on PCB RthJA minimal footprint - - 75
6 cm2 cooling area5) --50
Electrical characteristics, at Tj=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage V(BR)DSS VGS=0 V, ID=1 mA 25 - - V
Gate threshold voltage VGS(th) VDS=VGS, ID=20 µA 1.2 1.6 2
Zero gate voltage drain current IDSS
VDS=25 V, VGS=0 V,
Tj=25 °C - 0.1 1 µA
VDS=25 V, VGS=0 V,
Tj=125 °C - 10 100
Gate-source leakage current IGSS VGS=20 V, VDS=0 V - 10 100 nA
Drain-source on-state resistance RDS(on) VGS=4.5 V, ID=30 A -1215
mΩ
VGS=4.5 V, ID=30 A,
SMD version - 11.8 14.8
VGS=10 V, ID=30 A - 7.4 8.8
VGS=10 V, ID=30 A,
SMD version - 7.2 8.6
Gate resistance RG-1-
Ω
Transconductance gfs
|VDS|>2|ID|RDS(on)max,
ID=30 A 23 46 - S
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm
2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Values
2) Current is limited by bondwire; with an RthJC=2.4 K/W the chip is able to carry 67 A.
3) See figure 3
4) Tj,max=150 °C and duty cycle D<0.25 for VGS<-5 V
1) J-STD20 and JESD22
Rev. 2.12 page 2 2008-04-14
IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
Parameter Symbol Conditions Unit
min. typ. max.
Dynamic characteristics
Input capacitance Ciss - 1235 1642 pF
Output capacitance Coss - 474 630
Reverse transfer capacitance Crss -6192
Turn-on delay time td(on) - 7.0 10 ns
Rise time tr- 5.6 8.4
Turn-off delay time td(off) -2030
Fall time tf- 3.4 5.1
Gate Char
g
e Characteristics6)
Gate to source charge Qgs - 4.3 5.7 nC
Gate charge at threshold Qg(th) - 2.0 2.6
Gate to drain charge Qgd - 2.8 4.3
Switching charge Qsw - 5.2 7.3
Gate charge total Qg-1013
Gate plateau voltage Vplateau - 3.5 - V
Gate charge total, sync. FET Qg(sync)
VDS=0.1 V,
VGS=0 to 5 V - 8.7 12 nC
Output charge Qoss VDD=15 V, VGS=0 V -1014
Reverse Diode
Diode continous forward current IS- - 50 A
Diode pulse current IS,pulse - - 350
Diode forward voltage VSD
VGS=0 V, IF=50 A,
Tj=25 °C - 0.97 1.2 V
Reverse recovery charge Qrr
VR=15 V, IF=IS,
diF/dt=400 A/µs - - 10 nC
6) See figure 16 for gate charge parameter definition
TC=25 °C
Values
VGS=0 V, VDS=15 V,
f=1 MHz
VDD=15 V, VGS=10 V,
ID=25 A, RG=2.7 Ω
VDD=15 V, ID=25 A,
VGS=0 to 5 V
Rev. 2.12 page 3 2008-04-14
IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
1 Power dissipation 2 Drain current
Ptot=f(TC)ID=f(TC); VGS≥10 V
3 Safe operating area 4 Max. transient thermal impedance
ID=f(VDS); TC=25 °C; D=0 ZthJC=f(tp)
parameter: tpparameter: D=tp/T
1 µs
10 µs
100 µs
1 ms
10 ms
DC
1
10
100
1000
0.1 1 10 100
VDS [V]
ID [A]
limited by on-state
resistance
single pulse
0.01
0.02
0.05
0.1
0.2
0.5
100
10-1
10-2
10-3
10-4
10-5
10-6
0.01
0.1
1
10
0000001
tp [s]
ZthJC [K/W]
0
10
20
30
40
50
60
70
0 50 100 150 200
TC [°C]
Ptot [W]
0
10
20
30
40
50
60
0 50 100 150 200
TC [°C]
ID [A]
Rev. 2.12 page 4 2008-04-14
IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
5 Typ. output characteristics 6 Typ. drain-source on resistance
ID=f(VDS); Tj=25 °C RDS(on)=f(ID); Tj=25 °C
parameter: VGS parameter: VGS
7 Typ. transfer characteristics 8 Typ. forward transconductance
ID=f(VGS); |VDS|>2|ID|RDS(on)max gfs=f(ID); Tj=25 °C
parameter: Tj
3.2 V 3.5 V 3.8 V 4.1 V
4.5 V
10 V
0
4
8
12
16
20
24
28
0204060
ID [A]
RDS(on) [mΩ]
25 °C
175 °C
0
20
40
60
80
100
012345
VGS [V]
ID [A]
0
10
20
30
40
50
60
0 102030405060
ID [A]
gfs [S]
2.8 V
3 V
3.2 V
3.5 V
3.8 V
4.1 V
4.5 V
10 V
0
10
20
30
40
50
60
0123
VDS [V]
ID [A]
Rev. 2.12 page 5 2008-04-14
IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
9 Drain-source on-state resistance 10 Typ. gate threshold voltage
RDS(on)=f(Tj); ID=30 A; VGS=10 V VGS(th)=f(Tj); VGS=VDS
parameter: ID
11 Typ. Capacitances 12 Forward characteristics of reverse diode
C=f(VDS); VGS=0 V; f=1 MHz IF=f(VSD)
parameter: Tj
typ
98 %
0
2
4
6
8
10
12
14
16
-60 -20 20 60 100 140 180
Tj [°C]
RDS(on) [mΩ]
20 µA
200 µA
0
0.5
1
1.5
2
2.5
-60 -20 20 60 100 140 180
Tj [°C]
VGS(th) [V]
Ciss
Coss
Crss
104
103
102
10110
100
1000
10000
0 5 10 15 20 25 30
VDS [V]
C [pF]
25 °C
175 °C
25 °C, 98%
175 °C, 98%
1
10
100
1000
0.0 0.5 1.0 1.5 2.0
VSD [V]
IF [A]
Rev. 2.12 page 6 2008-04-14
IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
13 Avalanche characteristics 14 Typ. gate charge
IAS=f(tAV); RGS=25 ΩVGS=f(Qgate); ID=25 A pulsed
parameter: Tj(start) parameter: VDD
15 Drain-source breakdown voltage 16 Gate charge waveforms
VBR(DSS)=f(Tj); ID=1 mA
5 V
15 V
20 V
0
2
4
6
8
10
12
0 5 10 15 20
Qgate [nC]
VGS [V]
20
21
22
23
24
25
26
27
28
29
-60 -20 20 60 100 140 180
Tj [°C]
VBR(DSS) [V]
V
GS
Q
gate
V
gs(th)
Q
g(th)
Q
gs
Q
gd
Q
sw
Q
g
25 °C100 °C
150 °C
1
10
100
1 10 100 1000
tAV [µs]
IAV [A]
Rev. 2.12 page 7 2008-04-14
IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
Package Outline PG-TO252-3-11
Rev. 2.12 page 8 2008-04-14
IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
Package Outline PG-TO252-3-23
PG-TO252-3-23: Outline
Footprint:
Rev. 2.12 page 9 2008-04-14
IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
Package Outline PG-TO251-3-11
Rev. 2.12 page 10 2008-04-14
IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
Package Outline PG-TO251-3-21
Rev. 2.12 page 11 2008-04-14
IPD09N03LA G IPF09N03LA G
IPS09N03LA G IPU09N03LA G
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of
conditions or characteristics. With respect to any examples or hints given herein, any typical
values stated herein and/or any information regarding the application of the device,
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,
including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please
contact the nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information
on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with
the express written approval of Infineon Technologies, if a failure of such components can
reasonably be expected to cause the failure of that life-support device or system or to affect
the safety or effectiveness of that device or system. Life support devices or systems are
intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user
or other persons may be endangered.
Rev. 2.12 page 12 2008-04-14
