Notes through are on page 11
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IRFB59N10D
IRFS59N10D
IRFSL59N10D
SMPS MOSFET
HEXFET® Power MOSFET
lHigh frequency DC-DC converters
Benefits
Applications
lLow Gate-to-Drain Charge to Reduce
Switching Losses
lFully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
lFully Characterized Avalanche Voltage
and Current
VDSS RDS(on) max ID
100V 0.025Ω59A
Typical SMPS Topologies
l Half-bridge and Full-bridge DC-DC Converters
PD - 93890
D2Pak
IRFS59N10D
TO-220AB
IRFB59N10D TO-262
IRFSL59N10D
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 59
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 42 A
IDM Pulsed Drain Current 236
PD @TA = 25°C Power Dissipation 3.8 W
PD @TC = 25°C Power Dissipation 200
Linear Derating Factor 1.3 W/°C
VGS Gate-to-Source Voltage ± 30 V
dv/dt Peak Diode Recovery dv/dt 3.3 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Mounting torqe, 6-32 or M3 screw 10 lbf•in (1.1N•m)
Absolute Maximum Ratings
lFull-bridge Inverters
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Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 18 ––– ––– S VDS = 50V, ID = 35.4A
QgTotal Gate Charge –– – 76 11 4 ID = 35.4A
Qgs Gate-to-Source Charge ––– 24 36 nC V DS = 80V
Qgd Gate-to-Drain ("Miller") Charge ––– 36 54 VGS = 10V,
td(on) Turn-On Delay Time ––– 16 ––– VDD = 50V
trRise Time ––– 90 ––– ID = 35.4A
td(off) Turn-Off Delay Time ––– 20 ––– R G = 2.5Ω
tfFall Time ––– 12 ––– VGS = 10V
Ciss Input Capacitance ––– 2450 ––– VGS = 0V
Coss Output Capacitance ––– 740 ––– V DS = 25V
Crss Reverse Transfer Capacitance ––– 190 ––– pF ƒ = 1.0MHz
Coss Output Capacitance ––– 3370 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 390 ––– V GS = 0V, VDS = 80V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 690 ––– VGS = 0V, V DS = 0V to 80V
Dynamic @ TJ = 25°C (unless otherwise specified)
ns
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy––– 510 mJ
IAR Avalanche Current––– 35.4 A
EAR Repetitive Avalanche Energy––– 20 mJ
Avalanche Characteristics
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 35.4A, VGS = 0V
trr Reverse Recovery Time ––– 130 2 00 n s TJ = 25°C, IF = 35.4A
Qrr Reverse RecoveryCharge ––– 0.75 1. 1 µC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Diode Characteristics
59
236 A
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 10 0 ––– –– – V VGS = 0V, I D = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.11 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.025 ΩVGS = 10V, ID = 35.4A
VGS(th) Gate Threshold Voltage 3.0 ––– 5.5 V VDS = VGS, ID = 250µA
––– ––– 25 µA VDS = 100V, VGS = 0V
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 10 0 VGS = 30V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -30V
IGSS
IDSS Drain-to-Source Leakage Current
Thermal Resistance Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.75
RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient––– 62
RθJA Junction-to-Ambient––– 40
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
T , Junction Temperature( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
59A
0.01
0.1
1
10
100
1000
0.1 1 10 100
20
µ
s PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
5.0V
0.1
1
10
100
1000
0.1 1 10 100
20
µ
s PULSE WIDTH
T = 175 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
5.0V
0.1
1
10
100
1000
4 6 8 10 12 14
V = 50V
20µs PULSE WIDTH
DS
V , Gate-to-Source Volta
g
e (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 175 C
J°
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C, Capacitance(pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = C
gs + Cgd, C
ds SHORTED
Crss
= C
gd
Coss
= C
ds + C
gd
020 40 60 80 100 120
0
4
8
12
16
20
Q , Total Gate Char
g
e (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
35.4A
V = 20V
DS
V = 50V
DS
V = 80V
DS
0.1
1
10
100
1000
0.2 0.6 1.0 1.4 1.8 2.2
V ,Source-to-Drain Volta
g
e (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 175 C
J°
1
10
100
1000
1 10 100 1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T = 175 C
= 25 C
°°
J
C
V , Drain-to-Source Volta
g
e (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
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Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RGD.U.T.
VGS
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Dut
y
factor D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(
THERMAL RESPONSE
)
25 50 75 100 125 150 175
0
10
20
30
40
50
60
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
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Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
VGS
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
15V
20V
25 50 75 100 125 150 175
0
300
600
900
1200
Starting T , Junction Temperature( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
14.5A
25.0A
35.4A
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P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFET® Power MOSFETs
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
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LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
- B -
1.3 2 (.05 2)
1.2 2 (.04 8)
3X 0.55 (.02 2)
0.46 (.01 8)
2.92 (.115 )
2.64 (.104 )
4 .69 (.18 5)
4 .20 (.16 5)
3X 0.93 (.0 37)
0.69 (.0 27)
4.06 (.160)
3.55 (.140)
1.15 (.04 5)
MIN
6.47 (.255)
6.10 (.240)
3.78 (.149)
3.54 (.139)
- A -
10.54 (.415 )
10.29 (.405 )
2.87 (.1 13)
2.62 (.1 03)
15 .24 (.60 0)
14 .84 (.58 4)
1 4.09 (.5 55)
1 3.47 (.5 30)
3X 1 .40 (.05 5)
1 .15 (.04 5)
2 .54 (.10 0)
2X
0 .36 (.0 1 4) M B A M
4
1 2 3
NOTES:
1 DIM E N S IO N IN G & TO LERA NC IN G PE R A NS I Y 14.5 M , 1 982. 3 O U TLINE C O N F O R MS TO JE D E C OUT LINE T O -2 20A B .
2 CONT ROL L ING DIM ENSIO N : IN CH 4 HEATSINK & L EAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
PART NUMBER
INTERNATIONAL
RECTIFIER
L OGO
EXAMPLE : THIS IS A N IRF1010
W IT H A SS E MBL Y
L O T COD E 9 B1 M
ASSEMBLY
L O T C OD E
DATE CODE
(YYWW)
YY = YEAR
W W = W E EK
9246
IRF1010
9B 1M
A
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D2Pak Package Outline
D2Pak Part Marking Information
10.16 (.400)
R EF.
6.47 (.2 55 )
6.18 (.2 43 )
2.61 (.1 03 )
2.32 (.0 91 )
8.89 (.350)
REF .
- B -
1.32 (.052)
1.22 (.048)
2.79 (.110)
2.29 (.090)
1.39 (.055)
1.14 (.045)
5 .28 (.20 8)
4 .78 (.18 8)
4.69 (.1 85)
4.20 (.1 65)
10.54 (.415)
10.29 (.405)
- A -
2
1 3 15.4 9 (.6 10)
14 .7 3 (.580)
3X 0.93 (.037)
0.69 (.027)
5 .08 (.20 0)
3X 1.40 (.0 55)
1.14 (.0 45)
1.78 (.070)
1.27 (.050)
1.40 (.055)
MA X.
NOTES:
1 DIMENSIONS AFTER SOLDER DIP.
2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M , 1982.
3 CONTROLLING DIMENSION : INCH.
4 HEATSINK & LEAD DIM ENSIONS DO NOT INCLUDE BURRS.
0.55 (.022)
0.46 (.018)
0.2 5 ( .0 10) M B A M MINIMUM RECOM MENDED FOOTPRINT
11.43 (.450)
8.89 (.3 50 )
17 .78 (.70 0)
3.81 (.150)
2.08 (.082)
2X
LEAD ASSIGNMENTS
1 - GAT E
2 - DRAIN
3 - SOUR CE
2.54 (.100)
2X
PAR T NU MB ER
INTERNATIONAL
RE CTIFIER
LO GO DATE CODE
(YYW W )
YY = YEAR
WW = WEEK
A S SEMBLY
LO T CO D E
F530S
9B 1M
9246
A
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TO-262 Par t Mar king Infor mation
TO-262 Package Outline
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Repetitive rating; pulse width limited by
max. junction temperature.
ISD ≤ 35.4A, di/dt ≤ 350A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Notes:
Starting TJ = 25°C, L = 0.8mH
RG = 25Ω, IAS = 35.4A.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% V DSS
This is only applied to TO-220AB package
D2Pak Tape & Reel Information
3
4
4
TRR
FEED D IRE CTION
1 .85 (.0 73)
1 .65 (.0 65)
1 .60 (.0 63)
1 .50 (.0 59)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421) 16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532 )
12.80 (.504 )
330.00
(14.173)
MAX.
2 7.4 0 (1.079)
2 3.9 0 (.9 41)
60.00 (2.362)
M IN.
30.40 (1.197)
M A X.
26 .40 (1.03 9)
24 .40 (.9 61 )
NO TES :
1. CO MFORM S TO EIA-418.
2. CONTROLLING DIMENSIO N: M ILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ O UTER EDGE.
This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
IR EUROPEAN REGIONAL CENTRE: 439/445 Godstone Rd, Whyteleafe, Surrey CR3 OBL, UK Tel: ++ 44 (0)20 8645 8000
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IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 011 451 0111
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo 171 Tel: 81 (0)3 3983 0086
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IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673 Tel: 886-(0)2 2377 9936
Data and specifications subject to change without notice. 4/00
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