06/01/07
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HEXFET® Power MOSFET
S
D
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Benefits
lImproved Gate, Avalanche and Dynamic dV/dt
Ruggedness
lFully Characterized Capacitance and Avalanche
SOA
lEnhanced body diode dV/dt and dI/dt Capability
l Lead-Free
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D2Pak
IRFS4410ZPbF
TO-220AB
IRFB4410ZPbF
TO-262
IRFSL4410ZPbF
S
D
G
S
D
G
S
D
G
DDD
IRFB4410ZPbF
IRFS4410ZPbF
IRFSL4410ZPbF
GDS
Gate Drain Source
PD - 97278B
VDSS 100V
RDS
(
on
)
typ. 7.2m:
max. 9.0m:
ID
(
Silicon Limited
)
97c
ID (Package Limited) 75A
Absolute Maximum Ratings
Symbol Parameter Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)
IDM Pulsed Drain Current d
PD @TC = 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
VGS Gate-to-Source Voltage V
dv/dt Peak Diode Recovery fV/ns
TJ Operating Junction and °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy emJ
IAR Avalanche Currentc A
EAR Repetitive Avalanche Energy gmJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case k––– 0.65
RθCS Case-to-Sink, Flat Greased Surface , TO-220 0.50 ––– °C/W
RθJA Junction-to-Ambient, TO-220 k––– 62
RθJA Junction-to-Ambient (PCB Mount) , D2Pak jk ––– 40
300
Max.
97c
69c
390
75
242
See Fig. 14, 15, 22a, 22b,
230
16
-55 to + 175
± 20
1.5
10lbxin (1.1Nxm)
IRF/B/S/SL4410ZPbF
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Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.143mH
RG = 25Ω, IAS = 58A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 58A, di/dt ≤ 610A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
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D
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Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V
∆V(BR)DSS
/
∆TJ Breakdown Voltage Temp. Coefficient ––– 0.12 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 7.2 9.0 mΩ
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
RGInternal Gate Resistance ––– 0.70 ––– Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
gfs Forward Transconductance 140 ––– ––– S
QgTotal Gate Charge ––– 83 120 nC
Qgs Gate-to-Source Charge ––– 19 –––
Qgd Gate-to-Drain ("Miller") Charge ––– 27
Qsync Total Gate Charge Sync. (Qg - Qgd)––– 56 –––
td(on) Turn-On Delay Time ––– 16 ––– ns
trRise Time ––– 52 –––
td(off) Turn-Off Delay Time ––– 43 –––
tfFall Time ––– 57 –––
Ciss Input Capacitance ––– 4820 ––– pF
Coss Output Capacitance ––– 340 –––
Crss Reverse Transfer Capacitance ––– 170 –––
Coss eff. (ER) Effective Output Capacitance (Energy Related) i––– 420 –––
Coss eff. (TR) Effective Output Capacitance (Time Related)h––– 690 –––
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units
ISContinuous Source Current ––– ––– 97cA
(Body Diode)
ISM Pulsed Source Current ––– ––– 390 A
(Body Diode)d
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time ––– 38 57 ns TJ = 25°C VR = 85V,
––– 46 69 TJ = 125°C IF = 58A
Qrr Reverse Recovery Charge ––– 53 80 nC TJ = 25°C di
/
dt = 100A
/
µs
g
––– 82 120 TJ = 125°C
IRRM Reverse Recovery Current ––– 2.5 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
ID = 58A
RG =2.7Ω
VGS = 10V g
VDD = 65V
ID = 58A, VDS =0V, VGS = 10V g
TJ = 25°C, IS = 58A, VGS = 0V g
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 5mAd
VGS = 10V, ID = 58A g
VDS = VGS, ID = 150µA
VDS = 100V, VGS = 0V
VDS = 80V, VGS = 0V, TJ = 125°C
MOSFET symbol
showing the
VDS =50V
Conditions
VGS = 10V g
VGS = 0V
VDS = 50V
ƒ = 1.0MHz, See Fig.5
VGS = 0V, VDS = 0V to 80V i, See Fig.11
VGS = 0V, VDS = 0V to 80V h
Conditions
VDS = 10V, ID = 58A
ID = 58A
VGS = 20V
VGS = -20V
IRF/B/S/SL4410ZPbF
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
≤60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
0 20406080100
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VGS, Gate-to-Source Voltage (V)
VDS= 80V
VDS= 40V
VDS= 20V
ID= 58A
2 3 4 5 6 7
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 50V
≤60µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 58A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
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Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
20
40
60
80
100
ID, Drain Current (A)
Limited By Package
-60 -40 -20 020 40 60 80 100120140160180
TJ , Temperature ( °C )
90
95
100
105
110
115
120
125
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5mA
-10 0 10 20 30 40 50 60 70 80 90 100
VDS, Drain-to-Source Voltage (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Energy (µJ)
0.0 0.5 1.0 1.5 2.0 2.5
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0 1 10 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100µsec
1msec
10msec
DC
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
800
900
1000
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 6.4A
9.4A
BOTTOM 58A
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
Thermal Response ( Z thJC ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
τJ
τJ
τ1
τ1
τ2
τ2
R1
R1R2
R2
τ
τC
Ci i/Ri
Ci= τi/Ri
Ri (°C/W) τi (sec)
0.237 0.000178
0.413 0.003772
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
50
100
150
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 58A
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τj = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
IRF/B/S/SL4410ZPbF
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Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VGS(th), Gate threshold Voltage (V)
ID = 150µA
ID = 250µA
ID = 1.0mA
ID = 1.0A
100 200 300 400 500 600 700
dif/dt (A/µs)
0
50
100
150
200
250
300
350
400
450
Qrr (nC)
IF = 58A
VR = 85V
TJ = 25°C _____
TJ = 125°C
----------
100 200 300 400 500 600 700
dif/dt (A/µs)
0
50
100
150
200
250
300
350
400
Qrr (nC)
IF = 39A
VR = 85V
TJ = 25°C _____
TJ = 125°C ----------
100 200 300 400 500 600 700
dif/dt (A/µs)
0
5
10
15
20
IRRM (A)
IF = 58A
VR = 85V
TJ = 25°C _____
TJ = 125°C ----------
100 200 300 400 500 600 700
dif/dt (A/µs)
0
5
10
15
20
IRRM (A)
IF = 39A
VR = 85V
TJ = 25°C _____
TJ = 125°C ----------
IRF/B/S/SL4410ZPbF
www.irf.com 7
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
1K
VCC
DUT
0
L
S
20K
Vds
Vgs
Id
Vgs(th)
Qgs1
Qgs2QgdQgodr
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
tp
V
(BR)DSS
I
AS
VGS
VDD
VDS
LD
D.U.T
+
-
Second Pulse Width < 1µs
Duty Factor < 0.1%
VDS
VGS
90%
10%
td(off) td(on)
tftr
IRF/B/S/SL4410ZPbF
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TO-220AB packages are not recommended for Surface Mount Application.
TO-220AB Part Marking Information
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
IRF/B/S/SL4410ZPbF
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TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
/2*2
5(&7,),(5
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TO-262 packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
IRF/B/S/SL4410ZPbF
10 www.irf.com
D2Pak (TO-263AB) Part Marking Information
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
'$7(&2'(
<($5 
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
IRF/B/S/SL4410ZPbF
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/07
D2Pak Tape & Reel Information
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html